// AMS netlist generated by the AMS Unified netlister
// IC subversion:  IC25.1-64b.38 
// Xcelium version: 25.03-s005
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: username Pid: 3050583
// Design library name: testcases
// Design cell name: tb_testcase_ams_include_vars
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// HDL file - testcases, testcase_veriloga, veriloga.
// Library - testcases, Cell - tb_testcase_ams_include_vars, View - schematic
// LAST TIME SAVED: Oct  6 10:19:47 2025
// NETLIST TIME: Oct  6 10:39:59 2025

`worklib testcases
`view schematic

`timescale 1ns / 1ns 
(* cds_ams_schematic *)

module tb_testcase_ams_include_vars ( );
wire clk;
wire out_gui;
wire out_file;
testcase_veriloga #(.test_var_file(cds_globals.test_val_file), .test_var_gui(cds_globals.test_val_gui)) I0 (.out_file( out_file ), .out_gui( out_gui ), .clk( clk ));
vsource #(.dc(1), .type("pulse"), .val0(0), .val1(1), .period(1/cds_globals.clk_f), .delay(-(1e-12)/2), .rise(1e-12), .fall(1e-12), .width(0.5*(1/cds_globals.clk_f-(1e-12)-((1e-12))))) V0 (clk, cds_globals.\gnd! );

endmodule
`noworklib
`noview