Hi every one,
We are implementing our circuit in cadence using the cadence format <a:b> for buses. nevertheless, we have the CDL netlist and layout of Digital blocks with format [a:b]. I create a empty schematic and symbol in cadence format <> to use them in our design and later instantiate them with the .INCLUDE....
Finally we will have most of the circuit withs <> format and some with [ ]. Edit the netlists can be ok but i would like do not have to edit the layouts. Is there a way to say to assura LVS that [ is the same than < and ] than > at least in the layouts? if it is possible for netlist as well it is better.
Best regards,
Manuel