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Cadence is a leading provider of system design tools, software, IP, and services.
I have been contacted with some outstanding
new opportunities inside a large corporation that has a big presence in Silicon
Valley, CA and Austin, TX. We are looking primarily for experts in ECAD, EDA,
Place and Route, Layout, etc. There are approximately 30 positions open, which
is a welcome sign of growth within the Technology job-market. These are
opportunities with a dynamic and successful company that is a dedicated
foundry, serving the global marketplace.
#1) Place & Route Technical Engineer/Manager
Job Location: San Jose, California
#2) Automated Place and Route Sr. Engineer and
Job Location: Austin, Texas
#3) Place & Route - Sr. Engineers/Technical
Job Location: San Jose, California
responsible for ASIC integration/implementation projects, and advance design methodology build-up.
#5) Timing Sr. Engineer / Technical Manager
Job Location: Austin, Texas
#6) Sr. Logic Design Engineer/ Manager
Location: San Jose, California
Logic Design Engineer responsible for architecting, implementing highly
integrated and complex multifunctional SOC designs.
have system view to architect, micro-architect, and system analysis on
generate or enhance SOC platforms that could incorporate processor, graphics,
memory and high speed IO.
to drive, manage and implement a complex Chip design from define the goals,
requirements, execution plan, defining critical milestones, create the
specification, RTL coding to Physical Chip implementation.
to do the system level debugging from high level, logic level to circuit level.
detailed specifications; perform static timing, logic synthesis, lab debug and
closely with circuit, physical design, verification, and software engineers to
deliver logically correct and electrically robust designs.
supervise the activities of others.
o PhD and 7+ years’ experience
o M.S./B.S. and 10+ years’ experience
Must have system level view and system debug experience.
Must have previous experience integrating processor with memory
subsystem, and high speed IO’s on a highly integrated SOC chip.
Mobile SoC experience is plus.
Must have prior experience working with tools for:
o Simulation: System Verilog, VCS/IUS
o Modeling: C++, Perl, System C
o Verification: SVA, System-C/Verilog
o Chip Design: RTL and Physical design
independently to determine methods and procedures on new or special assignments.
IF you are interested in exploring one or more of these opportunities to work
with some of the leading technology companies in the world, please respond
with a resume. Referrals, recommendations and suggestions are always
welcome, as are 'random' resume submissions for other possible
opportunities not described above.
Wingate Dunross, Inc.
ph (818)597-3200 ext. 211