Feedback, Suggestions, and Questions - Recent Threads

testing

marcelpreda — Mon, 04 May 2026 09:05:43 GMT

Hi there,

This post is more a test.
I'm trying to start a thread in this forum, but no success.

Either my message is to big, or something else (e.g. I've try some text formatting) but when I push Post the the page is "thinking", see attachment.

I've try it in Chrome and Edge browsers, I've wait almost half hour, noting is happening.
Some advice, should I skip text formatting?

Thank you,

Marcel

NCSU TechLib Ami06 - Diva -> Assura Files

PlexiGlassFish — Mon, 22 Dec 2025 18:05:11 GMT

Hey everyone,

I am running Cadence Virtuoso and I need to convert some NCSU_TechLib_Ami06 library files (divaDRC.rul, divaLVS.rul, tech.db and the techfile) over from its Diva implementation (as of the NCSU_CDK_1.6.0_Beta) to be Assura compatible. I was wondering if anyone has already made this conversion happen for any/all of the listed files, or if people had tips for the conversion process.

SKILL program or a command file to identify the regions where metal layers extend into MOM capacitors

Brad7086 — Thu, 17 Jul 2025 07:42:29 GMT

I would like to write a SKILL program or a command file to identify the regions where metal layers extend into MOM capacitors, in order to prevent any impact on the capacitance value of the MOM capacitors.

My initial idea is to first identify the layers of the MOM capacitors, and then use the ABE API to find the overlapping areas with the metal layers.
I welcome everyone to discuss and share your opinions. Thank you!

DC-DC converter power stage (real switching circuit) transfer function bode plot method

SL202507161758 — Thu, 17 Jul 2025 06:37:44 GMT

I am building a schematic and running simulations in Cadence ADE L.

With a power converter such as a buck converter which is a real switching circuit,

is there a way to obtain the open-loop duty-cycle-to-output transfer function through simulation?

Easy fix >> typo at the "Community" page in the user description "Comunity member" should be "Community member"

Kira M — Wed, 09 Jul 2025 06:03:24 GMT

Easy and quick fix >> typo at the "Community" page in the user description. I suppose "Comunity member" should be "Community member"

Have a good day!

High-Voltage MOSFET Body Diode Behavior and Extraction Issues in Post-Layout Simulation

Xilai — Fri, 27 Jun 2025 19:48:58 GMT

Hello,

I’m working on a design using a TSMC 180nm High Voltage (GEN2) process. The devices in use, according to the PDK model files, include internal body diodes as part of their structure.

Setup:

VDD = 20V supply
Layout passes DRC, LVS, and ANN
SUB terminals for both NMOS and PMOS are connected to GND and VDD respectively

Issues Encountered:

In Calibre PEX, I see warnings like:
- “Area for diode cannot be 0.0, reset to 1e-12”
- “Layout instances ignored due to invalid master”
In Assura layout extraction, I can Diode noted “unmatched”
In Spectre post-layout simulations, DC and transient behavior significantly diverges from schematic-level results.

I suspect that leakage through internal body diodes at high voltage (20V) is causing simulation instability or unexpected current paths—possibly due to how the substrate terminals are connected or how the extraction tool interprets the parasitics.

Questions:

What is the recommended way to connect SUB terminals in high-voltage devices to avoid body diode conduction or leakage?
How can I configure Calibre PEX (or Assura) to extract accurate area/perimeter values and avoid diode mismatch warnings? Since we cannot control or set the internal Diode no matter in schematic or layout.
Is there a specific LPE or netlisting flow required to properly handle HV parasitics and diode modeling in this process?

Any help on preventing diode-related leakage and ensuring post-layout accuracy at high voltage mosfets or any experience about the HV PDK would be greatly appreciated.

Why i can't insert pictures from my computer

littleneil — Fri, 28 Feb 2025 15:41:23 GMT

Hi,everyone.
I'm trying to post a question to the community but find myself can't upload pictures onto the website.
I choose Insert>Image/Video/File>Upload, but every time i click upload there's an orange notice board jump out saying 'An error occurred. Please try
again or contact your administrator', whatever size or formate of pictures I choose.
My broswer is chorme.

How to find the pulse length with MDL?

iaty — Sat, 11 Jan 2025 16:49:36 GMT

I am trying to find the equation to calculate the total length of a signal. So the code should find the moment the signal starts to rise, plateau, and fall duration. After that, the duration of these times should be added. And at the end, I should get 150ns as a result. I tried to implement something like the below but it did not work suggestion are welcome :)

export real rise_time = cross(sig=V(BL), dir='rise', n=1, thresh=0.0)
export real fall_time = cross(sig=V(BL), dir='fall', n=1, thresh=0.0)
export real pulse_length = fall_time - rise_time

Full form of OrCAD SPB

NS202410146147 — Wed, 23 Oct 2024 08:27:11 GMT

What is the full form of "SPB" in OrCAD SPB Build like 16.xx , 17.xx , etc. ?

Assura gives DRC error even for a single device

Sameerpy — Mon, 16 Sep 2024 18:55:42 GMT

Hi , I am manually trying to make layout but when I take PMOS or NMOS for layout from gpdk180nm and run Assura it will show DRC even if the only single device is present in the whole layout. I don't know why it is happening. If someone has idea please help. Thanks in advance

How to three terminal resistor in circuits?

Sameerpy — Sun, 01 Sep 2024 17:54:11 GMT

I have to design an amplifier in CMOS 065nm in which I want to use three terminal resistor from this technology so that when I make layout I can easily generate from it source.
Note - Point to use this resistor because it relatively have smaller length then two terminal resistor.
Question- I want to know how to connect the it's terminal in design and during LVS check does it give error ?

Place Replicate Module

Hussain Aalim — Wed, 14 Aug 2024 19:40:54 GMT

I need a help in the automation using skill language in the process of Place Replicate Apply so far I have created the symbols using below:

axlDBCreateSymbol("C219", list(4353, 2070), nil, 0)
(dbid:00000142F0C78EF8 nil)

axlDBCreateSymbol("C215", list(4353, 2070), nil, 0)
(dbid:00000142BAD212D8 nil)

axlDBCreateSymbol("KM_CSI_S1", list(4453, 2070), nil, 0)
(dbid:00000142EF4A21B8 t)

Now I wanted to select these Symbols and apply the Place Replicate Apply using the module files that I have the .mdd file and make it intelligent and place the module on my desired location.

I am unable to find the command to perform this operation using skill language.

Help is required in this regard.

Thanks

I have created below Three Symbols:

Now I have to automate the process that when I slect all three of them then I right clcik then goes to the option Place Replicate Apply then selects the desired module so it becomes something as below in snap which is my desired goal to place on any location of my interest:

Please help in this regard.

Thanks

how can I go back to blogs from forums?

Mahesh Turaga — Mon, 12 Aug 2024 19:03:39 GMT

I am interested to also access cloud related blogs while I am in forums. how do I go back?

License manager server

razvanolt — Thu, 01 Aug 2024 08:23:50 GMT

Hi,

I installed LCU and XCELIUM on 2 machines. One is the license server where I modified the hostname and opened it on port 5280 tcp and on the other machine I want to use the XCELIUM but I can't checkout the licenses. Any help with actual steps or how can I solve this error?

Trying to check out license...
   Xcelium_Limited_Single_Core 23.00 - Failed
   Xcelium_Single_Core 23.00 - Failed
   Xcelium_Safety_Sim 23.00 - Failed
   Xcelium_Safety 23.00 - Failed
   Xcelium_Multi_Core 23.00 - Failed
   Xcelium_For_Partners 23.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03015'.
TOOL:   xrun(64)   23.09-s001: Exiting on Aug 01, 2024 at 07:36:58 UTC (total: 00:00:30)

[11:22 AM] Alexandra Radu
[azureuser@machines-user-new-1 bin]$ ./lmutil lmstat -a -c 5280@myip

lmutil - Copyright (c) 1989-2023 Flexera. All Rights Reserved.

Flexible License Manager status on Thu 8/1/2024 08:21

License server status: 5280@licensing-server-new

License file(s) on licensing-server-new: /home/azureuser/cadence/installs/LCU43/tools.lnx86/bin/ License_19689_6045bd9f89cf_7_25_2024.txt:

licensing-server-new: license server UP (MASTER) v11.15.1

Vendor daemon status (on licensing-server-new):

cdslmd: Cannot connect to license server system. (-15,570:115 "Operation now in progress")

impossible to manage cookies :"save preference soes nothong (Forefox, up to date

jc teyssier — Tue, 09 Jul 2024 05:54:30 GMT

I try to manage cookies clicking on cookie and red dot on bottom left of this site.

I set as per i want (advertising and analytics), clic on "Save Preferences"...

Returning on red dotted cookie show that nothing have been taken into account..

What is going on?

Tryied to disable/unable uBlock Origin extension change nothing to this behavior

Firefox 127.0.2 64 bits, French langage set

Unusual Behavior of NMOS HVT Transistor in 45nm Technology

AB_1718811953287 — Wed, 19 Jun 2024 16:00:02 GMT

Hi Cadence Community,

I am currently working with Cadence's 45nm technology and have encountered a peculiar issue with the NMOS High-Voltage Threshold (HVT) transistor. Specifically, I'm observing an unexpected relationship between the oxide thickness and the saturation current.

Here's the situation:

When I increase the oxide thickness, the saturation current increases.

Conversely, when I decrease the oxide thickness, the saturation current decreases.

From my understanding, this behavior is counterintuitive since typically, a thicker oxide would lead to a reduction in gate capacitance and consequently a decrease in the drive current. Conversely, a thinner oxide should enhance the gate control over the channel, thereby increasing the drive current.

Has anyone else encountered this issue or could provide insights into what might be causing this anomalous behavior? I am curious if there are any specific aspects of the 45nm technology node or the HVT transistors that might explain this phenomenon. Any suggestions for further investigation or potential solutions would be greatly appreciated.

Thank you in advance for your help!

How do I drive a clock signal to become an output (clock_debug) signal?

jbc0510 — Fri, 10 May 2024 22:38:23 GMT

Good evening everyone,

I'm an undergraduate student and I'm fairly new to VLSI design. I was wondering how I could drive my clock input signal to be an output into another output pin? My approach is to do it on the layout and not change the RTL. Any guidance on this matter or resources that can help me would be greatly appreciated.

net parasitic capacitance

TomVilla — Sun, 03 Mar 2024 13:23:17 GMT

Hello everyone,

I'm currently working on a design block that features two crucial nets for which I need to determine the parasitic capacitance. My goal is to perform a post-layout analysis, so it's vital for me to find a convenient method for this task. I prefer not to use ADE for this purpose. Instead, I'm considering using Calibre for targeted extraction on these specific nets. Could anyone provide guidance or suggest how to proceed with this? Any help or direction would be greatly appreciated.

Thank you in advance.

cadence virtuoso , 1, need to know how can i remove the physical binding(devices) of a layout, 2, depend on the connectivity can we change the binding of devices , once we clear the physical binding??

CDB — Thu, 08 Feb 2024 13:02:24 GMT

HI All,

1, I need to know how can i remove the physical binding(devices) of a layout??

2,Once we clear the physical binding, by connectivity can I update the device correspondence as schematic or is ther any way to update the physical binding(binding option should work i feel)??

Kindly Guide me.

forum notification

masamasa — Sun, 14 Jan 2024 22:19:38 GMT

hello

i do not get any notification from cadence anymore regarding this forum even though i turn on the "notify me when someone replies to this post" option when creating a new post.

i used to get notifications by email from cadence but now no more.

do i need set up another options to get notifications?

Getting of thr Forums

LeavingSoon — Wed, 20 Dec 2023 12:12:30 GMT

I posted an item years ago about PSPICE and now I just get spam (Several today). But when I logged in it created a new account. Maybe because it was years since I posted. So I know have a zombie account on this site spamming me. Can some one explain how I fix that.? I'd be happy to delete the account.

Integrated Phase Noise in dBc

surazms1993 — Mon, 20 Nov 2023 02:38:35 GMT

Hi,

Im trying to measure the phase noise of my driven clock circuit.
After following the tutorials from Cadence, Im doing PSS analysis followed by PNOISE analysis with time-averaged option for pahse noise. I am able to get the phase noise plot which is in dBc/Hz curve in log scale.

From here, Im able to use marker to get the Noise Flooe in dBc/Hz after the curve flattens.

Problem Statement : How can I measure integrated phase noise in dBc for defined integration limits ?

Case1 : to get the curve to calculator and find the area under the curve mathematically. Can anyone help me how to do it?

Case2 : Im using Printed Noise Summary to get integrated Noise but it has only V2 and V units but I need it in dBc. Can anyone help me how to do this?

Its a bit urgent, looking forward to your response.

Email Subscription for posts I create

firebolt2 — Fri, 10 Nov 2023 15:36:36 GMT

This is non-technical question. With subscribe option, I get email for each post created by others. But not for the ones I post. Why? Does anyone facing this? Or is this the only way of how it works?

[Question] Can't find my post and forum "Tensilica IP"

CharlesT — Mon, 30 Oct 2023 12:53:53 GMT

I got a mail that my post is moved to "Tensilica IP".

Then I try to click the 2 link, both my thread and "Tensilica IP" will lead to " Page Not Found ".

Also I found in "community search" page, search results shows some posts labeled with "Tensilica IP" category,
while also shows page not found if trying to click to access.

Is that something relative to account access rights ? Or just link error with incorrect link ?

ASSURA Not Working

ICDesignAddiction — Fri, 27 Oct 2023 18:31:36 GMT

Greetings All,

I hope your day is going well.

First I want to thank you for giving me some of your time to read my problem and help me with it.

This starts with Assura 41, I installed Assura 41 which is compatible with IC 6.1.8, I exported the Unix and the environment variabls paths to the bashrc, I set up the assura_tech.lib in the launch directory. All going well till now, so I launched virtuoso and viola, assura appeared in my layout, but when I installed EXT19.13 and PVS19.10 and exported their paths, unfortunately assura tab disappeared and both quantus and pvs tabs appeared, first CIW started giving me ASSURA not available. I tried removing the paths of PVS and EXT along with Assura and resetting them, it still works with PVS and EXT, but this time Assura not available message disappeared.

I did remove the paths of PVS and EXT while keeping it for assura, yet still assura didn't appear ever again knowing that the first time it appeared it worked very fine I ran an LVS and everything seemed super normal.

I tried a lot of removing paths, changing their orders but nothing work, I always get PVS and quantus to work but assura doesn't want to launch. Also, quantus-Assura is greyed out, and Assura-Calibre is not note that I don't have calibre installed and when I press on it, it shows assura_tech.lib. I need some of your time, so we can figure this out.

Kind regards,

ICDesignAddiction