https://community.cadence.com/general_topics/en-USTelligent Community 12https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/66144/cadence-gem-macb---direct-rgmii-mac-to-mac-communication-without-phy/1408857Tue, 07 Jul 2026 17:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7036e6b0-c240-4b24-99a7-0183395c9f94Andrew BeckettI don't think we have any forums for Design IP (this is certainly not the place for it). You should create a support case by logging onto ask.cadence.com and then use the Case menu to submit a case. That's the correct way to get support for Design IP related questions (AFAIK).https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/66144/cadence-gem-macb---direct-rgmii-mac-to-mac-communication-without-phyTue, 07 Jul 2026 17:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:267bf281-1ce5-44ff-8c2e-0d51012453b9SK202607076945Hi Team, We are working on a direct RGMII MAC-to-MAC communication setup between an NXP i.MX8MP MAC and a Cadence GEM (MACB) integrated in an APSoC. The two MACs are connected directly without an external PHY. We have already performed the following verification to isolate the issue: Verified standalone external loopback on the APSoC by connecting TX and RX locally. Both TX and RX packet counters increase correctly. Verified standalone external loopback on the i.MX8MP. Communication is successful. Verified the RGMII interface using an oscilloscope. TX data and clocks are present, and the electrical interface appears normal. Tried different phy-mode settings ( rgmii , rgmii-id , rgmii-rxid ) without improvement. Since both MACs work correctly in standalone testing, the remaining suspicion is related to the direct MAC-to-MAC RGMII interface and clock timing. We would appreciate clarification on the following: Does the Cadence GEM IP officially support direct RGMII MAC-to-MAC communication without an external PHY? Are there any additional GEM register configurations required specifically for MAC-to-MAC operation? Is the RGMII TX/RX clock skew (internal delay) programmable in the Cadence GEM IP? If programmable, is it configured through: GEM registers, the Linux macb driver, Device Tree, or platform-specific hardware outside the GEM IP? Does the Linux macb driver configure any RGMII delay automatically, or is this expected to be handled by the SoC integration? Are there any application notes, reference designs, or known limitations for GEM MAC-to-MAC operation over RGMII? Any guidance would be greatly appreciated.cadence_gemiprgmii2rgmiiCadence IPhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65985/testing/1408418Mon, 04 May 2026 15:31:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62df83aa-9010-4668-9888-b6872d3dfa4cmarcelpredaHi Andrew, The screenshot was just a ~ 4kb png file. I've try to add it again on this reply. The same message: " An error occurred. Please try again or contact your administrator." My initial problem was related to this question community.cadence.com/.../spectre-nodes-info-pin-names-different-than-what-is-in-schematic-or-input-scs spectre nodes info: pin names different than what is in schematic or input.scs   On that I didn't had any attachment. I was trying just some text formatting (inline code blocks) to make it readable. In the end I had to split it in the original message. Maybe there is a limit to the body message or it has some special (html) chars community.cadence.com/.../inteneded_5F00_message.txt . I've attached it as plain text, in case IT want to debug it. First line is the thread subject, then follow the message body. Thanks a lot for carring, Marcelhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65985/testing/1408417Mon, 04 May 2026 15:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8e44000a-ae72-4a0c-8d2b-8dfebd02df91Andrew Beckettmarcelpreda IT asked me how big was the file you were trying to upload? There's a 2MB limit and exceeding this can cause issues similar to what you described. I'm not sure that's entirely it, because that would only be relevant if you were adding the attachment and I'm not sure that's the only thing you tried? Andrewhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65985/testingMon, 04 May 2026 09:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:18fe4f2d-46e6-46c9-b1df-25501bd11363marcelpredaHi there, This post is more a test. I'm trying to start a thread in this forum, but no success. Either my message is to big, or something else (e.g. I've try some text formatting) but when I push Post the the page is "thinking", see attachment. I've try it in Chrome and Edge browsers, I've wait almost half hour, noting is happening. Some advice, should I skip text formatting? Thank you, Marcelhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/63326/why-i-can-t-insert-pictures-from-my-computer/1407901Tue, 03 Mar 2026 06:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b80dce47-28c3-439e-b2bd-2a6c92f17053Zhifeng JinNo solution. The PC department is really not awesome. I've been facing this issue for over a year and it remains unresolvedhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65591/ncsu-techlib-ami06---diva---assura-files/1407348Mon, 22 Dec 2025 23:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3367b6c1-f602-450a-a677-2fb0bccf3366Andrew BeckettI just checked this with IC25.1. The Diva menus are in the Verify menu (DRC, Extract, LVS etc) once you've set this environment variable. Andrewhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65591/ncsu-techlib-ami06---diva---assura-files/1407347Mon, 22 Dec 2025 22:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:90b3094a-9528-412d-98d7-adf9c827db4ePlexiGlassFishAppreciate the feedback Andrew! Looked into using SKILL commands but it is unfamiliar to me and it seems like there may be extensive additional programming to make it work. Additionally, I am using IC 25.1 and the bash terminal command that was suggested does not appear to add any Diva specific menus in Layout Suite XL. For now, I will read up on the migration guide.https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65591/ncsu-techlib-ami06---diva---assura-files/1407346Mon, 22 Dec 2025 20:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e2d8940c-d074-4f15-9d15-fbbd41f31eedAndrew BeckettIf you really need to do this (you could just continue to use Diva - see Looking for Diva menu in ICADV12.x/ICADVM18.1/ICADVM20.1/IC23.1 release if it's just the menus you're missing), then look at /doc/DivaToAssura/DivaToAssura.pdf - also can be found online here: Diva to Assura Migration Guide -- Preface - Preface You also don't need to migrate the tech.db or techfile (I assume that's the ASCII tech file). Andrewhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65591/ncsu-techlib-ami06---diva---assura-filesMon, 22 Dec 2025 18:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c25d8476-fc5c-4ada-8afa-fdfe9fc2d673PlexiGlassFishHey everyone, I am running Cadence Virtuoso and I need to convert some NCSU_TechLib_Ami06 library files (divaDRC.rul, divaLVS.rul, tech.db and the techfile) over from its Diva implementation (as of the NCSU_CDK_1.6.0_Beta) to be Assura compatible. I was wondering if anyone has already made this conversion happen for any/all of the listed files, or if people had tips for the conversion process.TechfilecadencedivaDRCLVSVirtuosoAssurahttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/15654/deactivate-disable-components-instances-in-cadence-schematic/1406949Tue, 04 Nov 2025 10:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ed9b63fc-d29f-4c16-968d-ec794565eb57YM202511043742Select instances/components you want to disable, then press "shift" and "del"https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/65226/import-hspice-protected-netlist/1406384Wed, 17 Sep 2025 16:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0b910e09-bcb6-4cdd-a4f3-792fddd6c28aAndrew BeckettDuarte, You can't. Cadence tools cannot read files encrypted for HSPICE (a Synopsys simulator) in the same way that their tools can't read files encrypted for Spectre (a Cadence simulator). Andrewhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/64964/skill-program-or-a-command-file-to-identify-the-regions-where-metal-layers-extend-into-mom-capacitorsThu, 17 Jul 2025 07:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:37072680-eae6-4ebb-8981-8ff6b55916f9Brad7086I would like to write a SKILL program or a command file to identify the regions where metal layers extend into MOM capacitors, in order to prevent any impact on the capacitance value of the MOM capacitors. My initial idea is to first identify the layers of the MOM capacitors, and then use the ABE API to find the overlapping areas with the metal layers. I welcome everyone to discuss and share your opinions. Thank you!https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/64962/dc-dc-converter-power-stage-real-switching-circuit-transfer-function-bode-plot-methodThu, 17 Jul 2025 06:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:854134ea-5768-4f40-978c-272b26c0a84cSL202507161758I am building a schematic and running simulations in Cadence ADE L. With a power converter such as a buck converter which is a real switching circuit , is there a way to obtain the open-loop duty-cycle-to-output transfer function through simulation ?capturecadenceVirtuosodesignhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/64926/easy-fix-typo-at-the-community-page-in-the-user-description-comunity-member-should-be-community-member/1405613Thu, 10 Jul 2025 07:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:593e738f-f2ef-4db2-b6cf-91318febe0efKira MIt is here: community.cadence.com /members // This typo for the new users only who has 0 posts and status "Community Level" As soon a new user post something, status changed to level 1 "Community Level 1" and for this description everything is fine You can test it using username "comunity" >> https://community.cadence.com/members/ comunity (also with a typo in the name) I found this user by "search" on the website, when was looking for any topics related to "comunity" to don't create extra topics / tickets.https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/64926/easy-fix-typo-at-the-community-page-in-the-user-description-comunity-member-should-be-community-member/1405596Wed, 09 Jul 2025 11:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ec2932ad-1741-4558-b2cd-436a022bc9ecAndrew BeckettThanks - I'd like to pass this on to our team that supports the forum itself. However, I haven't managed to locate exactly where this misspelling occurs - can you give me the steps you used to find it?https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/64926/easy-fix-typo-at-the-community-page-in-the-user-description-comunity-member-should-be-community-memberWed, 09 Jul 2025 06:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:057ef1d7-5e74-4637-905d-f876ed694679Kira MEasy and quick fix >> typo at the "Community" page in the user description. I suppose "Comunity member" should be "Community member" Have a good day!https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/64887/high-voltage-mosfet-body-diode-behavior-and-extraction-issues-in-post-layout-simulationFri, 27 Jun 2025 19:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0f04390a-0fe5-45be-bcdd-906f234b9071XilaiHello, I’m working on a design using a TSMC 180nm High Voltage (GEN2) process. The devices in use, according to the PDK model files, include internal body diodes as part of their structure. Setup: VDD = 20V supply Layout passes DRC, LVS, and ANN SUB terminals for both NMOS and PMOS are connected to GND and VDD respectively Issues Encountered: In Calibre PEX, I see warnings like: “Area for diode cannot be 0.0, reset to 1e-12” “Layout instances ignored due to invalid master” In Assura layout extraction, I can Diode noted “unmatched” In Spectre post-layout simulations, DC and transient behavior significantly diverges from schematic-level results. I suspect that leakage through internal body diodes at high voltage (20V) is causing simulation instability or unexpected current paths—possibly due to how the substrate terminals are connected or how the extraction tool interprets the parasitics. Questions: What is the recommended way to connect SUB terminals in high-voltage devices to avoid body diode conduction or leakage? How can I configure Calibre PEX (or Assura) to extract accurate area/perimeter values and avoid diode mismatch warnings? Since we cannot control or set the internal Diode no matter in schematic or layout. Is there a specific LPE or netlisting flow required to properly handle HV parasitics and diode modeling in this process? Any help on preventing diode-related leakage and ensuring post-layout accuracy at high voltage mosfets or any experience about the HV PDK would be greatly appreciated.spectre simulationenvironmental variablesimulation problemanalogTransient simulationdesignhttps://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/31357/cadence-16-6-orcommn-2302/1405017Wed, 14 May 2025 06:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7f44d3f3-ec18-46cd-a881-fc3830881439ZZ202505137120Hi,the adress you gived has died,can you give me a new one. Thank you very much. ---From a noob.https://community.cadence.com/general_topics/f/feedback-suggestions-and-questions/63524/how-to-get-the-changes-in-the-layout-before-doing-save-through-skill-code/1403569Thu, 03 Apr 2025 09:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:55b7664e-8b0e-4f9e-a58d-042dddf010fdAndrew BeckettThis is not possible. Andrew