https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/63148/changing-gap-for-routed-diff-pairs/1408741Thu, 18 Jun 2026 20:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3667478f-01f0-4c79-9a2c-c360f5384d79JM20241029170This was a lifesaver. The resize->diff pair isn't listed on my Allegro X Artist.https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/the-three-layer-cake-the-foundation-behind-intelligent-engineeringThu, 18 Jun 2026 14:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a4a27532-a3ce-4806-b523-8f2c92b66e40CorporateArtificial intelligence is rapidly becoming the engine behind the next era of technology innovation. From hyperscale data centers and autonomous systems to robotics and scientific discovery, AI is expanding into nearly every industry. Yet many discussions about AI focus only on what people can see—larger models, smarter assistants, and increasingly capable autonomous systems. The reality is that AI itself represents only the visible layer of a much larger technology ecosystem. Behind every AI breakthrough lies a much larger technology stack that includes advanced computing infrastructure, physically accurate computational software, and intelligent automation working together. As AI expands into hyperscale computing, autonomous systems, robotics, scientific discovery, and intelligent products, success increasingly depends on how effectively these technologies operate as an integrated ecosystem. Cadence has been evolving this systems-oriented view of intelligent engineering for years. Earlier strategies centered on concepts such as pervasive intelligence, system innovation, and design excellence, reflecting the industry's growing need to optimize hardware, computational software, and engineering workflows as interconnected systems rather than isolated domains. By 2023, as AI infrastructure, scientific computing, and intelligent automation increasingly converged, Dr. Anirudh Devgan , president and CEO of Cadence, began referring to this vision as the "Three-Layer Cake" to help visualize how innovation across these interconnected layers must work together to power the next era of intelligent system design. The Three-Layer Cake is a framework that illustrates how innovation depends on the convergence of accelerated computing, computational software, and intelligent automation. The framework describes AI as three interconnected layers: Accelerated Computing and Data Principled Simulation and Optimization AI Agents and Agentic Intelligence The lower layers create the infrastructure and scientific foundation required to build increasingly intelligent systems, while the upper layer applies AI to improve how those systems themselves are designed. Together, these layers form the bridge between building AI technologies and using AI to accelerate engineering innovation. Layer One: Accelerated Computing and Data The foundation of the cake is Accelerated Computing and data infrastructure, the systems responsible for delivering the performance and scale required for modern AI. This layer forms the core of Design for AI because it provides the hardware foundation required to power modern AI workloads, from advanced silicon and memory architectures to large-scale computing systems and AI infrastructure. Over the last several years, the compute foundation has transformed dramatically. Traditional X86-centric environments have evolved into platforms built around GPUs, Arm systems, AI accelerators, emerging XPU architectures, and custom silicon. Recognizing this transition early, Cadence began porting computational software several years ago to operate efficiently across hybrid environments. As AI workloads continue scaling, software optimization across increasingly diverse hardware architectures becomes just as important as raw compute capability. This infrastructure now powers everything from cloud computing environments and AI factories to large-scale training and inference workloads. As AI models become larger and more complex, demands on this layer continue to increase. Performance is no longer determined by silicon alone. It increasingly depends on optimization across the complete system stack, including advanced packaging, chiplets, networking, power delivery, cooling systems, and large-scale data center environments. Equally important is the growing convergence between hardware and computational software. Matching the right software to the right hardware architectures is unlocking orders-of-magnitude improvements in computational performance, scalability, power efficiency, and the ability to analyze increasingly complex datasets and engineering problems. As heterogeneous computing continues to evolve, advances in hardware and software optimization are becoming deeply interconnected drivers of AI innovation. This foundation provides the computational scale needed for the AI era. But raw compute capability alone does not create intelligent systems. Layer Two: Principled Simulation and Optimization Above the compute layer sits the scientific backbone of intelligent engineering: the computational foundation that connects Design for AI and AI for Design . It combines classical algorithms, numerical methods, and science-based models from physics, chemistry, and mathematics to accurately model real-world system behavior. While AI can generate possibilities, this layer determines whether those possibilities work in the world around us. For semiconductor and system design, these models ensure compliance with real-world constraints such as: Thermal behavior Signal integrity Analog characteristics Manufacturability Reliability Power consumption This layer becomes increasingly important as systems become more heterogeneous and interconnected. Continued innovation in the middle layer remains critical because AI cannot compensate for weak engineering foundations. Automation alone does not create better outcomes. A useful analogy is autonomous driving. Adding sophisticated automation to a poorly designed vehicle does not create a better system. The underlying vehicle itself must already operate reliably. Similarly, AI-driven automation requires highly accurate, physically grounded computational engines underneath it. Improvements in simulation, optimization, and core design technologies ultimately amplify the effectiveness of the AI layer above. Intelligence becomes significantly more valuable when built on top of physically accurate and scientifically grounded foundations. This is also where computational software becomes increasingly important, not simply as a collection of tools and solutions, but as the engines that transform raw compute capability into accurate engineering outcomes. Layer Three: AI Agents and Agentic Intelligence At the top of the framework sits AI itself—the layer that increasingly enables AI for Design by embedding intelligence directly into engineering workflows. This layer includes generative AI, reasoning systems, optimization AI, and agentic AI technologies capable of coordinating complex workflows. AI has evolved from optimization AI focused on narrow tasks to more sophisticated agents and now toward super-agent systems capable of orchestrating complete engineering workflows. Importantly, not every engineering challenge requires massive, general-purpose AI models with billions of parameters. Many design problems demand highly specialized optimization approaches tailored to specific tasks. Rather than relying exclusively on large general-purpose models, Cadence also leverages compact domain-specific neural networks, optimization engines, and reasoning systems that can operate in real time while maintaining speed, scalability, and physical accuracy. Cadence is advancing this transition through applying agentic AI to engineering with innovations such as ChipStack AI Super Agent, ViraStack AI Super Agent, and InnoStack AI Super Agent, which use domain-specific knowledge graphs to capture design semantics, hierarchy, and connectivity beyond the context limits of traditional LLMs. These systems can autonomously generate verification plans, refine tests, optimize implementation strategies, and coordinate complex design tasks across engineering environments. Rather than replacing engineering expertise, these systems now function as specialized design partners embedded directly into the engineering process. As AI becomes more tightly integrated with computational software and underlying compute infrastructure, super agents have the potential to transform how engineering work is planned, executed, and optimized across increasingly complex design environments. In many ways, this reinforces the virtuous cycle at the center of Design for AI and AI for Design: increasingly capable AI systems require more advanced engineering, while AI itself increasingly helps engineers create the next generation of those systems. Understanding each layer independently is important. The larger insight, however, comes from understanding how they interact. Why Is It a Cake? The value of the Three-Layer Cake framework is in combining solutions which leverage simultaneous innovation across the full engineering stack. Advances in compute create larger opportunities for simulation and AI. Improvements in computational software strengthen physical accuracy and system understanding. AI then amplifies both through automation, reasoning, and productivity gains. The result is a self-reinforcing cycle where each layer strengthens the others. This interconnected nature is also why Dr. Devgan began referring to the framework as a "Three-Layer Cake." As he later explained, the layers of the cake are not consumed independently like a traditional technology stack; they work together simultaneously. Accelerated Computing and data, principled simulation and optimization, and AI—each layer amplifies the capabilities of the others, and meaningful breakthroughs increasingly happen when all three are optimized together. As the framework gained broader visibility, the "Three-Layer Cake" terminology itself increasingly became shorthand for describing the tight interplay among hardware, software, and AI in industry discussions. The growing adoption of the phrase reflects an important engineering reality: the industry is moving toward tightly integrated systems where compute, software, and intelligence are inseparable. This is also why the Three-Layer Cake serves as the bridge between Design for AI and AI for Design. The lower layers create more capable systems and infrastructure, while the upper layer applies intelligence back into engineering processes. Together, they create a continuous cycle where AI systems and AI-driven engineering reinforce one another. Building the Future Across Every Layer The future of AI will not be defined solely by larger models or faster hardware. Competitive advantage will increasingly depend on how effectively organizations innovate across the complete technology stack. The Cadence Three-Layer Cake illustrates that intelligent engineering requires more than AI alone—it requires advances in Accelerated Computing and data, principled simulation and optimization, and AI-driven intelligence working together. This same framework also serves as the foundation for Cadence's Design for AI and AI for Design strategy, creating a virtuous cycle where AI systems and intelligent engineering continuously strengthen one another. As the industry moves toward physical AI and sciences AI, innovation across all three layers will shape the next era of technology. Explore how AI adoption is evolving from infrastructure AI toward physical AI and sciences AI—and what that means for the future of technology.featuredinfrastructure aiagentic aiPrincipled Simulationphysical aiThree-Layer CakeAI-Driven DesignAI for designAgentsdesign for AIAIhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66087/got-questions-on-sigrity-let-s-answer-them-live-on-wednesday-june-24thThu, 18 Jun 2026 13:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:110ade6d-2f58-46f3-92d8-a70f3aa58a15Renu VibhaCurious about the latest features? Facing real-world design challenges you’d like to crack faster? This is a much awaited interactive live session with Cadence experts to get the answers you need—right when you need them. Join us here on June 24, 2026 at 7:30 – 8:30 PM IST Topics PCB & IC Package S-Parameter Model Extraction PDN Voltage Drop Analysis High-Speed Design Simulation This is your opportunity to: Ask live questions Learn from real use cases Exchange insights with peers Bring your challenges. Share your perspective. Be part of the conversation.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/62813/place-via-array-boundary/1408740Thu, 18 Jun 2026 09:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:96fdf144-0bfa-459d-bb42-258565f427dfzpofrpHi HoangKho and karthikeyank, Could you share the skill to place via on both sides of cline.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66086/how-to-avoid-such-same-shape-spacing-problemThu, 18 Jun 2026 09:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:181a90da-9b1d-4f59-83b4-f4c02248458dJCTEYSSIER0I regurarly have shapes problem feedback from pcb manufacturers. Let me explain with an exemple: we have 0.1mm air gap here but my setup is: min width 0.12 min spacing 0.12 Spacing between via pad and cline is only 0.347mm so i agree shape can not be drawn here (need 3*0.12 mm = 0.36mm to be possible) The problem is 0.1mm between same shape. I do not find any setup to avoid this. Nor to dectec it. How can i get a DRC here: should be one since 0.1mm is less that 0.12mm Jean-Charleshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/65712/newly-created-blocks-in-allegro-24-1-cannot-be-saved/1408739Thu, 18 Jun 2026 08:58:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a580ff90-d6f9-4195-9829-6a46fe504ea0rg13In oreder to generate a VHDL file for a part, please use the following command line. newgenasym -i / -n -thttps://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/66082/i-am-not-able-to-generate-pdf-in-allegro-dehdl-in-24-1-version/1408738Thu, 18 Jun 2026 07:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:747bbbdc-aac5-491a-894d-bf4b55649f2fShashankThank for the reply rg13https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/66083/i-am-not-able-to-generate-pdf-in-allegro-dehdl-in-24-1-version/1408736Thu, 18 Jun 2026 07:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f71947ff-c7de-4213-a555-6c4ca034ed7crg13Hi Shashank, To use this feature, Allegro_Design_Publisher is needed. For more details, refer following link: Article (20492928) Title: Getting ERROR (SPCOCN-152) when trying to use Publish PDF option URL: https://ask.cadence.com/ASK/article-viewer?id=a1O3w00000A44OhEAJ&pageName=article-viewerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/66082/i-am-not-able-to-generate-pdf-in-allegro-dehdl-in-24-1-version/1408737Thu, 18 Jun 2026 07:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5105dffc-b301-4b74-8a79-528fffec24d5rg13Hi Shashank, To use this feature, Allegro_Design_Publisher is needed. For more details, refer following link: Article (20492928) Title: Getting ERROR (SPCOCN-152) when trying to use Publish PDF option URL: https://ask.cadence.com/ASK/article-viewer?id=a1O3w00000A44OhEAJ&pageName=article-viewerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66084/i-am-not-able-to-generate-pdf-in-allegro-dehdl-24-1/1408735Thu, 18 Jun 2026 07:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8879b3a3-2a18-423b-ad79-25cc424e6f03rg13Hi Shashank, To use this feature, Allegro_Design_Publisher is needed. For more details, refer following link: Article (20492928) Title: Getting ERROR (SPCOCN-152) when trying to use Publish PDF option URL: https://ask.cadence.com/ASK/article-viewer?id=a1O3w00000A44OhEAJ&pageName=article-viewerhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66085/sigrity-getting-started-to-sign-offThu, 18 Jun 2026 06:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22c831d9-7ad7-4a7d-b873-f42cff157853SumithAs a new Sigrity user, what was the first setup, modeling decision, or workflow change that helped you move from ‘getting started’ to getting meaningful SI/PI results—and what do you wish you had known on day one?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66084/i-am-not-able-to-generate-pdf-in-allegro-dehdl-24-1Thu, 18 Jun 2026 05:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6061d667-c0fc-4df9-8b92-322ebb79dceaShashankI have below licenses, Allegro Library Authoring (PCB Librarian) Allegro PCB Designer [Schematic] I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF But i am getting below error, ERROR(SPCOCN-152): The license for this feature could not be checked out because it is temporarily unavailable. Contact your administrator to check the license server. How can i resolve this and generate a pdf.https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/66083/i-am-not-able-to-generate-pdf-in-allegro-dehdl-in-24-1-versionThu, 18 Jun 2026 05:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cd63c079-29c6-4337-b0af-0182c85b02d2ShashankI have below licenses, Allegro Library Authoring (PCB Librarian) Allegro PCB Designer [Schematic] I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF But i am getting below error, ERROR(SPCOCN-152): The license for this feature could not be checked out because it is temporarily unavailable. Contact your administrator to check the license server. How can i resolve this and generate a pdf.https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/66082/i-am-not-able-to-generate-pdf-in-allegro-dehdl-in-24-1-versionThu, 18 Jun 2026 05:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ee24884b-92af-4a3b-99a9-3edd9da81007ShashankI have below licenses, Allegro Library Authoring (PCB Librarian) Allegro PCB Designer [Schematic] I am using Allegro PCB Designer [Schematic], and trying to export pdf by going to FILE->PUBLISH PDF But i am getting below error, ERROR(SPCOCN-152): The license for this feature could not be checked out because it is temporarily unavailable. Contact your administrator to check the license server. How can i resolve this and generate a pdf.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66072/how-do-you-route-multiple-nets-like-buses-efficiently-in-allegro-pcb-editor/1408734Wed, 17 Jun 2026 23:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:599ffd08-0af6-47e9-b6e8-7accc80301e7excellon1Hi Electro By default Allegro can route multiple traces at the same time and preserve the spacing between these traces. The spacing would be setup in the constraint manager. Since you are dealing with DDR it might be a good idea to setup in advance of routing some rules to handle your address busses etc, net spacing, net width etc. To route multiple traces general edit mode will work fine. Click Etch edit icon, then hold down the left mouse button and draw a box over the pins or nets. Your traces should appear and can be routed off the pins. When routing multiple traces there are two things to be aware of. Control Trace & Route Spacing. The control trace can cycle which traces the multi line route will follow. It appears as a white x on one of the traces. When the traces are being routed right click and choose "Change Control Trace". The etch will freeze on the screen so another trace can be selected as the control trace. Simply click the trace you wish to use and continue routing. Play around with it to get a feel of how it works. With route spacing you can specify the space between the traces. When you route off the pins you should notice that your traces respect the spacing of the pins. Route away from the pins then right click & choose "Route Spacing" , you can specify the spacing or use minimum spacing. Choose minimum spacing, The traces should taper down into a nice bus that respects the minimum spacing between the traces. Again play around to get a good feel for the mechanics. Sometimes while routing busses to and from IC's it can be a real pain to unwind the ends of the nets so as to get a straight point to point path for easy routing. Allegro does have tools to handle this such as the planner, you could look that up. Another option is to use is a method kind of like from to in Specctra. What you can do is simply draw in your bus and then connect both ends of the nets to that bus. Ideally one would want to do this early on in the design. Click add connect. Then right click and choose "Multi Line Route" Fill in the fields, Quantity, Line Width, spacing etc and just route the etch in. This etch does not contain a net name, but you can route a net to it and from it. Doing this can be handy because you can see visually in advance a good possible path your etch might use. Can be useful for what if situations etc. Best regards.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/1408733Wed, 17 Jun 2026 19:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:849052d6-10b5-4959-b7c6-9248674a294dSF202503203610If I click the image/video file it has for the file or a URL. If I click "upload" and select a file on my computer, I get a small orange window in the upper right that says "An error occurred. Please try again or contact your administrator" It says it can be a file or a URL. If I past a URL to postimages, it shows an image, but the post fails and I get notified that my post was flagged as SPAM and it asks me to write an appeal (which I did). If I post an imgbb link in that window, the image doesn't even show.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/1408732Wed, 17 Jun 2026 19:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:97fbab66-8044-4b7f-a5f1-b1ed1988654cJeetCan you share the error number with us ?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/1408731Wed, 17 Jun 2026 18:59:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:79f7a38c-ceba-47b2-b779-1afd02a2f99dSF202503203610The hierarchical block references another schematic page in the same .dsn file that also contains the hierarchical block. I am unable to upload the Tools -> Annotate snapshot. When I upload the image from my computer the forum gives and error, and when I try to use an image hosting site, it flags my post as SPAM.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/1408730Wed, 17 Jun 2026 18:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:370a1b11-114f-478f-bc16-c8e6438503d9SF202503203610It is a schematic page that is in the same .dsn file as the page with the hierarchical blocks Here is the Annotate screenshot: https://i.postimg.cc/L80Yxfcq/Screenshot-2026-06-17-145133.jpghttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/1408729Wed, 17 Jun 2026 18:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fe6dabdc-4486-4bf9-95dc-ffebfe24e137SF202503203610Thank you for the response. It is an internal schematic that is in the same .DSN file. Here is the snapshot of the Annotate window: