https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74718/why-are-power-pins-not-listed-in-the-power-pins-browserMon, 19 Oct 2026 17:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a44c474e-cfaf-4529-8a9c-022f771e5795LogicNetHi, I have a few components in my design with pins defined as Power type. However, when I go to Edit > Browse > Power Pins, some of these pins are not listed. What determines which Power pins appear in this browser? Thanks!https://community.cadence.com/cadence_blogs_8/b/pss/posts/odyssee-cae-2026-2Mon, 19 Oct 2026 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f8f56fe3-334f-47df-bb8f-c18fb1175de5PMM MichaelEngineering organizations generate vast amounts of simulation and test data. Yet turning that data into fast, actionable insights remains a challenge. Traditional simulation workflows often require significant compute resources and long turnaround times, making it difficult to explore design alternatives quickly. This is where ODYSSEE CAE helps. ODYSSEE CAE is an AI-powered Reduced Order Modeling (ROM), optimization, and data analytics platform that transforms simulation and test data into predictive models. Engineers can use these models to perform real-time analyses, explore design alternatives, optimize designs, and understand parameter sensitivities without running full simulations for every scenario. From Simulation Data to Engineering Intelligence Modern engineering teams need faster ways to evaluate performance, validate designs, and make informed decisions. By combining machine learning, reduced-order modeling, and optimization technologies, ODYSSEE CAE enables engineers to predict system behavior in seconds rather than hours or days. This allows teams to evaluate more design options, identify optimal solutions earlier, and reduce development costs. ODYSSEE CAE supports a wide range of engineering workflows, including: Real-time predictive modeling Design optimization Sensitivity analysis Statistical evaluation Uncertainty studies Animation prediction Automated simulation workflows What's New in ODYSSEE CAE 2026.2 Building on its predictive engineering capabilities, ODYSSEE CAE 2026.2 introduces several significant enhancements focused on simulation efficiency, workflow automation, and advanced modeling capabilities. Free Mesh Animation The new Free Mesh workflow extends animation prediction capabilities to models with varying geometries and mesh topologies. Engineers can now create predictive animation models for more complex simulation datasets through a dedicated workflow designed specifically for Free Mesh applications. GPU Acceleration A dedicated CUDA-enabled version of ODYSSEE CAE is now available, allowing users to leverage GPU computing for accelerated Free Mesh prediction workflows. This enhancement helps reduce computation times for demanding engineering studies. Integrated Adaptive Sampling Adaptive Sampling is now directly integrated into the ODYSSEE CAE interface. The technology automatically identifies the most valuable new simulation points to improve model accuracy and database quality, helping engineers build better predictive models while minimizing unnecessary simulation runs. Automated Simulation Workflows Nastran and LS-DYNA parser execution can now be automated from the command line using JSON-based configurations. This capability simplifies batch processing and enables seamless integration into existing simulation automation workflows. Enhanced Optimization Optimization workflows have been improved with support for starting from the "Optimal of DOE" point and defining constraints directly on design variables. These enhancements provide greater flexibility when solving both single-objective and multi-objective optimization problems. Accelerating Digital Engineering As engineering systems become more complex, organizations need tools that help transform simulation and test data into actionable knowledge. ODYSSEE CAE combines predictive modeling, optimization, and data analytics in a single platform, enabling engineers to explore more possibilities, make faster decisions, and improve product development efficiency. Whether the goal is to build predictive models, automate simulation workflows, optimize product performance, or gain deeper insight into engineering data, ODYSSEE CAE provides a scalable foundation for AI-driven engineering. Ready to accelerate engineering decisions with AI-powered predictive modeling? Visit the ODYSSEE product page for more information.WhatsNewODYSSEE CAEReduced Order ModelingAI for EngineeringPredictive AnalyticsEngineering Data Analyticsdesign optimizationSimulation AutomationIndustrial AIhttps://community.cadence.com/cadence_technology_forums/f/functional-verification/74717/xcelium-24-03-how-to-get-a-single-setuphold-line-in-annotation-summary-without-separate-setup-hold-rowsMon, 19 Oct 2026 12:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4dda86f4-e876-43ac-8984-0926eb55cb4fTU202610195844After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back. What I see My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log , the statistics table now also lists $setup and $hold as separate rows below $setuphold . In 24.03 only the combined $setuphold row was shown. Minimal reproducer design.sv: module dut (input clk, input d, output reg q); always @(posedge clk) q q) = (1.0, 1.0); $setuphold(posedge clk, d, 0.1, 0.1); endspecify endmodule test.sdf: (DELAYFILE (SDFVERSION "2.1") (DESIGN "dut") (DATE "2026-10-14") (VENDOR "Example") (PROGRAM "Custom") (VERSION "1.0") (DIVIDER /) (VOLTAGE 1.0) (PROCESS "typ") (TEMPERATURE 25.0) (CELL (CELLTYPE "dut") (INSTANCE) (DELAY (ABSOLUTE (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0)) ) ) (TIMINGCHECK (SETUPHOLD d (posedge clk) (0.1:0.1:0.1) (0.1:0.1:0.1) ) ) ) ) sdf.cmd: SDF_FILE = "test.sdf", SCOPE = tb.u_dut, LOG_FILE = "sdf_annotation.log", MTM_CONTROL = "TYPICAL"; testbench.sv: module tb; reg clk = 0; reg d = 0; wire q; dut u_dut (.clk(clk), .d(d), .q(q)); initial begin #10 clk = 1; #10 clk = 0; #10 d = 1; #10 clk = 1; #10 clk = 0; #50 $finish; end endmodule Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout Resulting output (relevant part) Path Delays 1 0 1 100.00 $setuphold 1 0.00 1.00 100.00 $setup 1 0 1 100.00 $hold 1 0 1 100.00 The summary lines still say No. of Tchecks = 1 , and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong. Question Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup / $hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?SystemVerilogxrunVerilogxceliumtiminghttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/74716/share-insights-differential-impedance-for-an-opampMon, 19 Oct 2026 10:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0b9ad41c-9b92-4395-b535-880073db8372IshaSYou want to characterize how an OPAMP’s differential input impedance changes with frequency. Which PSpice setup is most appropriate? A. Use a 1 A AC current source across the differential input, perform an AC frequency sweep, and evaluate Vdiff/IAC B. Apply a DC voltage source and perform Transient analysis C. Run a DC Sweep and plot the output voltage only D. Apply a sinusoidal source and calculate only the voltage gain Try this and share your observations. Happy Learning!PSPICEpspice simulationhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/74713/part-developer-pdv-missing-in-spb-24-1-on-linux-how-to-create-de-hdl-library-parts/1434955Mon, 19 Oct 2026 10:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c59fd789-53a4-4c73-8277-df88ce55c120rg13If you are looking for a full-fledged library flow to be used alongside System Capture, then you can go for AXML (Allegro X Managed Library) flow. Separate license Allegro Managed Library Authoring has to be used for that.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/74715/getting-simulation-files-information-using-skillMon, 19 Oct 2026 06:40:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a934b1dd-039a-41ac-8b7a-715c967792eaEO202501269056Hello! I am currently trying to find a way to get 'Parasitic Files (SPEF)' and 'PSpice Files' information from ADE Assembler/Explorer, found under Setup > Simulation Files. I need to automate this process using SKILL. So far, I cannot find a function or a way to extract these two pieces of information. Any advice?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/74714/control-which-properties-are-checked-by-update-part-status-in-orcad-x-capture-cisMon, 19 Oct 2026 06:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bd3885af-d605-458d-b0ce-2f2eeea43192TechnoBobbyIn OrCAD X Capture CIS, Update Part Status helps compare placed schematic components with their linked CIS database parts and identify property differences. Run Tools > Update Part Status in Part Manager to check the components in your design. The resulting status is displayed in Part Manager , helping you identify components that are not synchronized with the database. But what if you do not want a particular property to be checked? Navigate to: Options > CIS Configuration > Setup > Part Database > Configuration In the configuration table, use the Update Part Property column to control this behavior: Enabled : The property is checked during Update Part Status. Disabled : The property is excluded from the check. You can also use Options > Update Part Status > Verify Parts Against (.OLB) Libraries to verify placed parts against their source libraries. Have you explored these Update Part Status options in OrCAD X Capture CIS? Share your experience in the comments below!Capture CIShttps://community.cadence.com/cadence_blogs_8/b/pcbchn/posts/hsd_2d00_pcb_2d00_si_2d00_zhMon, 19 Oct 2026 01:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3f343f6b-9f45-4c3c-9abe-fd03b6155fa6SDA China在 PCIe Gen5/Gen6 、 DDR5 、 USB4 、 100G/400G 以太网、 AI 服务器、高性能计算（ HPC ）以及数据中心设备设计中， PCB 已不仅仅是连接器件的载体，而是高速信号传输链路的重要组成部分。随着数据速率不断提升，信号完整性已经成为决定系统性能、稳定性和产品一次成功率的关键因素。 《 HSD PCB 信号完整性分析指南》系统介绍了高速数字设计（ High-Speed Digital ， HSD ）中 最常见的信号完整性问题及其解决思路，包括阻抗控制、串扰分析、时序偏斜、返回路径以及同步开关噪声（ SSN ）等核心内容。 为什么高速 PCB 设计越来越依赖信号完整性分析？ 现代 PCB 系统广泛采用 PCIe 、 DDR 、 USB 、 HDMI 、千兆以太网等高速接口，并结合 PAM4 、 NRZ 等先进调制方式提升数据吞吐量。随着信号边沿速度进入皮秒级别，传统的经验式布线方法已经难以满足设计需求。任何细微的阻抗变化、串扰耦合或返回路径异常，都可能导致链路性能下降甚至产品失效。 书中指出： 高速信号频谱可能扩展到 GHz 甚至更高频段 PCB 已逐渐表现出明显的传输线特性 SI 与 PI 问题高度耦合 设计阶段的仿真验证远比后期返工更具成本优势 因此，越来越多的企业开始采用 “ 规则驱动设计 + SI 仿真验证 ” 的开发流程，在布局布线阶段提前发现潜在风险。 高速接口为什么必须控制阻抗？ 高速信号在 PCB 上传输时，本质上是电磁波沿传输线传播。 如果走线宽度、介质厚度、参考平面距离或者过孔结构发生变化，就会导致特性阻抗改变，从而产生信号反射。反射会带来： 眼图闭合 抖动增加 链路误码率（ BER ）升高 时序裕量下降 高速 PCB 设计必须从叠层规划开始，建立完整的阻抗控制策略。 差分信号为何成为高速设计的主流方案？ PCIe、 USB 、 Ethernet 、 SerDes 、 CXL 等高速总线几乎全部采用差分传输结构。 差分信号通过两条等幅反相信号线传输数据，可有效抑制共模噪声，提高抗干扰能力。 但这同时也带来了新的设计挑战： 差分阻抗控制 Pair 间距控制 D+/D− 长度匹配 参考平面连续性 Return Path 完整性 当差分对布线不对称时，部分差模能量将转换为共模信号，引发 EMI 和 SI 问题。 高速 PCB 设计最常见的问题之一：串扰（ Crosstalk ） 随着 PCB 密度不断提高，相邻高速网络之间的电磁耦合越来越严重。 串扰主要分为： NEXT （ Near-End Crosstalk ） 近端串扰，出现在接收端附近 FEXT （ Far-End Crosstalk ） 远端串扰，出现在发送端远侧 串扰会导致： 抖动增加 BER 恶化 眼图收缩 EMI 风险上升 书中建议采用以下方法降低串扰： ✅ 增加网络间距 ✅ 保持连续参考平面 ✅ 采用接地过孔栅栏（ Via Fence ） ✅ 使用场求解器进行耦合分析 ✅ 在布局阶段完成 SI 验证 时序偏斜为什么会影响高速链路稳定性？ 对于 DDR 、差分总线和并行数据总线而言，长度匹配直接影响数据同步。 书中指出：即使只有皮秒级别的通道间差异，也可能导致： 数据采样错误 差模转共模 EMI 增加 数据完整性下降 例如 USB SuperSpeed 的对内偏斜预算仅有约 15ps 。 因此，高速设计必须建立： Length Match 规则 Relative Delay 规则 Differential Pair 规则 Propagation Delay 规则 SSN （同步开关噪声）往往被低估 许多设计团队关注高速链路，却忽略了 PDN 质量对 SI 的影响。 当地大量 I/O 同时切换时，寄生电感会产生瞬时电压波动，引发： Ground Bounce（地弹） 电源振铃 时钟抖动 误触发 这些问题往往在后期 SI/PI 签核环节才暴露出来。 书中介绍了利用： 去耦电容优化 PDN 分析 返回路径检查 系统级 PI 仿真 来降低 SSN 风险的方法。 从经验驱动走向规则驱动 随着 AI 服务器、高速通信设备、汽车电子和高性能计算平台不断发展，单纯依赖工程师经验已经难以支撑复杂 PCB 设计。 本书不仅介绍各种 SI 现象背后的物理机制，更强调： 通过规则管理、约束驱动设计和仿真验证，实现高速 PCB 设计流程标准化。 对于以下工程师尤其值得阅读： PCB Layout 工程师 SI/PI 工程师 SerDes 设计工程师 DDR 工程师 AI 服务器硬件开发工程师 通信设备研发工程师 汽车电子硬件工程师 扫描下方二维码，免费阅读全文 获取完整《 HSD PCB 信号完整性分析指南》，深入掌握高速数字设计中的信号完整性挑战与解决方案，减少设计迭代，加快产品开发进度，实现高速 PCB 一次设计成功。 原创内容，转载请注明出处： https://community.cadence.com 。 欢迎订阅“PCB、IC封装：设计与仿真分析”博客专栏， 或扫描二维码关注“Cadence楷登PCB及封装资源中心”微信服务号，更多精彩期待您的参与！ 联系我们：spb_china@cadence.comChinese blog差分信号时钟抖动分析DDR5设计中文高速PCB设计同步开关噪声PCB信号完整性分析https://community.cadence.com/cadence_blogs_8/b/cfd/posts/clipped-voronoi-meshing-industrial-lesFri, 16 Oct 2026 19:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6a73cf73-4a82-4421-aba7-7f5045d24ce5AnneMarie SFor most teams running scale-resolving simulation, the solver is not the constraint. WMLES on a 100M to 1B+ cell grid is a known quantity, resolving separation, vortex shedding, mixing, and acoustic source behavior that no RANS closure will produce. The constraint is upstream. Getting a grid that an LES will tolerate, on real geometry with tight gaps and intersecting passages and thin walls, is where the schedule disappears. A senior engineer spends two weeks on inflation layer tuning and cleanup, nobody else on the team can reproduce the result exactly, and by the time it runs, the design study that justified it has moved on. That cost is labor, not compute. More nodes will not fix it. Figure 1: Full-scale Honda Fit meshed with clipped Voronoi diagrams in Fidelity Stitch. Polyhedral cells throughout, no prism stack anywhere on the vehicle. Topology Stops Being a Negotiation A Voronoi diagram partitions space by Euclidean distance to a set of generating points. Each cell is the region closer to its own point than to any other, and the faces are perpendicular bisectors between neighbors. Clip that diagram against the CAD surface and you get a body-fitted polyhedral mesh: exterior cells cut by the geometry, interior cells defined purely by point spacing. Figure 2: (a) Generating points define cells whose faces are perpendicular bisectors between neighbors. (b) The bounding surface clips the exterior cells, leaving interior cells defined by point spacing alone. Topology never depends on surface topology or domain decomposition. (Brès et al., 2023c) Mesh topology, therefore, depends on the point cloud alone. Not on surface topology, and not on how the domain was partitioned across ranks during parallel generation. Two engineers on two machines, given the same spacing rules, produce the same mesh. Design studies become directly comparable, certification evidence becomes defensible, and you stop paying the quiet tax of a multi-site program where the Detroit mesh and the Stuttgart mesh disagree, and nobody can say why. You specify resolution intent instead of topology. Point placement alone then yields Cartesian-like regions, highly anisotropic cells appropriate for WMLES, and deliberately coarse zones where the physics permits. The Inflation Layer Goes Away This is the largest labor line item removed. Near-wall resolution comes from tightening point spacing toward the surface. No prism stack to grow, no first-layer-height against growth-rate negotiation, no collapsed layers or tangled prisms to diagnose at 11 PM. For conjugate heat transfer, it is structural rather than ergonomic. Clipping produces fluid and solid cells meeting on a shared, perfectly aligned interface, and both domains mesh in one pass. The PAW-05 dual-bypass nozzle work predicted wall heat flux, shock structure, and plume behavior with WMLES plus CHT on automatically generated grids, a case class that historically consumed a meshing specialist for a month. Because volumetric resolution is decoupled from fine surface features, quality holds where body-fitted meshers usually break: turbomachinery tip gaps, automotive underbody and cooling packages, effusion cooling holes, intersecting ducts. Motion works for the same reason. Within an ALE framework with a sliding interface, the per-timestep rebuild updates Voronoi faces on the moving-stationary boundary only, preserving a single conformal grid and a conservative discretization at every step. Figure 3: Near-wall resolution on a rotor blade set by point spacing alone: 0.125 mm wall-normal, 0.5 mm tangential, aspect ratio 4, 5 layers over the surface. No inflation layer was grown to produce this. The Full Methodology and Validation Record The white paper Deterministic Voronoi Meshing for Complex, Multiphysics Geometries covers the clipped Voronoi construction, the NASA validation history, and the propulsion, automotive, turbomachinery, and CHT application cases. Read the white paper. The Solver Has to Deserve the Mesh The Fidelity Charles Solver uses a finite volume discretization built on a generalization of the discrete entropy framework for unstructured meshes, with KEEP schemes. The result is a stable, homogeneous flux discretization without shock sensors, upwinding hybridization, or hand-tuned stability coefficients. You are not spending a week hunting the dissipation setting that stops vortices smearing before they reach the FW-H surface. Coverage runs subsonic through hypersonic, plus a low-Mach Helmholtz formulation whose pressure field carries both hydrodynamic and acoustic components, so FW-H data and vibro-acoustic input come out of one solve. Sub-grid stresses use the Vreman model. Post-processing includes FW-H propagation from permeable surfaces and modal decomposition via POD and DMD. A Production Case, Not a Benchmark Case Toyota Motor Europe ran this stack on the Cadence Millennium M1 platform for HVAC vent noise, across two full-scale duct geometries at 0 and 32 degree blade angles. The Voronoi mesh came to roughly 30 million cells with sub-0.2 mm resolution at blades and outlets, generated in 4 minutes on 96 CPU cores. On-GPU streaming mode computed the acoustic signals during runtime for about 25% additional throughput. Figure 4a: Toyota vent exhaust mesh: Roughly 30 million cells with sub-0.2 mm resolution at the blades and outlets, generated in 4 minutes on 96 CPU cores. Against the facility’s own microphone array the simulation held within 3 dBA from 1 to 5 kHz, the band where HVAC content becomes audible once there is no engine to mask it, and it captured the difference between blade angles in both trend and magnitude. Under 6 hours on 8 GPUs on Millennium M1, against 60-plus hours on 512 CPUs conventionally. That is the difference between comparing vent designs inside a sprint and inside a quarter. Toyota Motor Europe’s full case study, Toyota Cuts HVAC Noise Simulation Time by 90% with GPU-Accelerated CFD , covers the mesh setup, FW-H configuration, and the band-by-band agreement with their rig data. Read the case study Figure 4b: Predicted against measured SPL at microphone 1, vent blades at 0 and 32 degrees. Agreement within 3 dBA from 1 to 5 kHz, including the difference between the two blade angles. What It Costs to Run Mesh generation at the top end: 11.4 billion cells on the NASA HL-CRM in 22 minutes on 43,200 cores, from the NASA-validated Stitch generator developed at Cascade Technologies, now part of Cadence. Solver turnaround as published in the Fidelity Charles Solver technical brief, two Millennium nodes each: DrivAer 144M cells in 4.6 hours, NASA SDT turbofan 142M in 6.7, GE E3 combustor 180M in 7.8, JSM airframe 185M in 13.9. Scaling holds well enough to buy your way out of a deadline. On a 118 Mcv full-scale sedan the low-Mach solver stayed above 90% scalability at 32,768 CPU cores and scaled near-ideally to 32 NVIDIA V100 GPUs at 3.7 Mcv per GPU: 16,000 CPU-hours on 2,560 cores reduced to 50 GPU-hours for identical acoustic spectra. The solver is GPU-resident on both NVIDIA and AMD architectures, with the Honda full-scale eVTOL case run on Mi210. Where This Is Not the Answer RANS is not displaced. For attached-flow parametric sweeps at high Reynolds number, where SST, GEKO, or EARSM closures are calibrated against your own test data and a case turns around in minutes, WMLES is the wrong tool and a Voronoi grid is overkill. The rotor work cited here is wall-modeled, at y+ around 30 with 50 to 100 cv per chord. Wall-resolved LES on complex geometry remains expensive. Judgment does not disappear either, it relocates. Instead of debugging prism stacks you decide where resolution belongs, and a bad spacing specification produces a fast, clean, wrong mesh. The difference is that you find out in minutes rather than a fortnight. See It on Your Own Geometry Benchmark cases prove a method works. They do not tell you what it does to your schedule, or whether it reproduces the one result your team already argues about. Fidelity CFD Software is available as a 30-day trial on your own geometry at your own operating conditions, with a Cadence CFD engineer helping get it running on your setup. The useful test is not a tutorial case. Bring something where you already know the answer: a rig you have measured, a configuration your current RANS setup gets wrong, a geometry whose meshing has cost you a fortnight before. Then compare cell count, turnaround time, and agreement with your own data.large eddy simulationPointwisevoronoi diagramsCharLESMillennium M1Fidelity CFDMeshinghttps://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/74713/part-developer-pdv-missing-in-spb-24-1-on-linux-how-to-create-de-hdl-library-partsFri, 16 Oct 2026 15:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cf52732f-31ce-4acd-923c-ca9a96816fd6DT202608276859What is the supported workflow for creating complete DE-HDL parts in 24.1? Is there a replacement launcher or additional installation component? RHEL 8.10; SPB 24.1 S008. Existing shared, file-based DE-HDL libraries configured through cds.lib . syscap launches successfully with PCB_librarian_expert checked out. Library Explorer offers only Symbols ; Add opens Create New Schematic Model . pdv and pdv.exe exist in 17.4 and 22.1, but were not found in the 24.1 installation or its installed package file lists. Ask: What is the supported workflow for creating complete DE-HDL parts in 24.1? Is there a replacement launcher or additional installation component?https://community.cadence.com/cadence_blogs_8/b/ip/posts/when-ai-moves-the-world-building-a-chiplet-standard-for-physical-aiFri, 16 Oct 2026 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d952b399-ef81-4cc4-af6b-34f7cc8d5986Mick PosnerIntroducing a new OCP FCSA sub-project workstream for real-time, safety-critical physical AI systems Most AI systems return an answer. Physical AI systems must return a motion: a steering correction, a robotic arm trajectory, or an emergency stop. The output is not a prediction on a screen. It is a force applied to the world, on a deadline, often with people nearby. That difference changes what the silicon underneath must guarantee. If that silicon is no longer one monolithic die but a package of potentially independently sourced chiplets, those guarantees stop being any single supplier's problem to solve. To address this, a new physical AI sub-project workstream is being introduced under the Open Compute Project's Foundation Chiplet System Architecture (OCP FCSA). Its purpose is to extend the data center, cloud, and server-centric FCSA baseline with the specification requirements to satisfy real-time, safety-critical physical systems, while retaining everything FCSA already defines. What Makes Physical AI Different A physical AI system must perceive, reason, and act safely within real-world boundary conditions to address the determinism and criticality required in physical world interaction. Because decisions directly affect physical behavior, six constraints apply to every design. Perceiving and Reacting Sensor fusion: One-time-valid view of the environment from camera, radar, and lidar Deterministic timing: Bounded, repeatable latency from sensing to action, worst case. and not just average Acting Safely Reliability and safety: Detect faults, report them, and reach a safe state within the deadline Security and trust: No untrusted actor can command physical motion or alter safety behavior Across the Whole Platform Power and thermal efficiency: Sustain performance inside a fixed power envelope Multi-chiplet scalability: One architecture that grows across product tiers and suppliers Figure 1. Physical AI constraints Why Chiplets Matter, and What They Complicate Chiplets are compelling for physical AI for four reasons: scalable composition of compute (Including CPU and AI scaling), sensor, memory, safety, security, and I/O across product tiers; function partitioning, where sensor, AI, memory, safety, and actuator functions can span several dies; independent sourcing from different suppliers on different update schedules; and reuse, letting one architecture scale from entry-level to high-end products. That flexibility is genuinely needed. Physical AI platforms do not share a single architectural profile. Preliminary comparison across representative categories, including vehicles, robots, drones, and other autonomous machines, suggests very different centers of gravity: high AI throughput and sensor ingress in one case, deterministic control and industrial connectivity in another, compact perception under strict size, weight, and power limits in a third. The same functional partitioning that enables this introduces five new concerns. Latency and jitter uncertainty: No longer fixed by a single design Distributed trust boundaries: The security perimeter now spans chiplets and suppliers Cross-chiplet fault propagation: One die can disturb another die's control path Lifecycle and configuration complexity: Discovery, update, and configuration go package-wide Observability and evidence gaps: No single die can evidence the whole package Each of these crosses a chiplet boundary, which makes them a standardization concern. A Physical AI Profile for OCP FCSA The workstream is proposed as a sub-project under OCP FCSA rather than as a standalone effort, for four reasons. FCSA already owns the chiplet system architecture baseline that physical AI builds on. Real-time and safety-critical concerns go beyond that baseline's current scope. OCP FCSA is the right place to standardize externally visible chiplet behavior. Finally, OCP FCSA delivers a concrete starting point to work from. OCP FCSA rules will be retained, and requirement rules specific to physical AI, such as real-time, secure, reliable, and safety-critical physical systems are added. In practice, that means following the OCP FCSA chapter structure wherever possible, adopting the same rules-based writing model, and applying a strict anti-duplication discipline, especially where an OCP FCSA rule already satisfies a physical AI requirement, reference it rather than restate it. Where a proposed requirement conflicts with the baseline, the conflict is named explicitly and resolved through the OCP FCSA working group. Each candidate is then classified by interoperability impact: baseline OCP FCSA reuse, required physical AI profile, optional profile, or architecture-specific guidance. Classifying candidates this way lets the group standardize what must interoperate across chiplets and leave the rest as guidance. Figure 2. Driving standardization via OCP FCSA From Constraints to Architecture An initial six constraints describe what a physical AI platform must guarantee. Figure 3. The initial six physical AI platform constraints, starting point of the new profile However, these initial six constraints are not directly specifiable. The bridging step maps each one to an architecture requirement area that can actually hold rules. Physical AI constraint Architecture areas it drives Deterministic timing Closed-loop control; deterministic execution; real-time interconnect Security and trust Security for physical action Power and thermal efficiency Energy efficiency and power management; heterogeneous compute Reliability and safety Functional safety; safety management and observability Sensor fusion Sensor fusion and perception data Multi-chiplet scalability Multi-chiplet scalability These initial six constraints, ten areas, and every candidate requirement trace back to a constraint. That traceability is what keeps the supplement from accumulating interface features with no system-level justification. A Worked Example: Functional Safety Failures can occur in sensor interfaces, compute chiplets, die-to-die links, memory, safety controllers, or actuator paths. Because they reach physical behavior, faults must be detected, isolated, and recovered within bounded safety response times. Functional safety therefore, goes beyond the individual chiplet. The platform must provide fault detection and containment, deterministic safety signaling, coordinated safe-state control, degraded-mode operation, and evidence that the sensor-to-action path stays within its safety goals. That single architecture requirement decomposes into six specification mechanisms: platform safety control and recovery coordination; traffic classes and QoS semantics; telemetry, debug, and trace control; safety-critical data protection; reliability, degradation, and link-health reporting; and verification, compliance, and safety-case evidence. Three of those six are shared mechanisms that also serve other constraints. That overlap is the argument for doing this work once, in a common baseline, rather than repeatedly across vendor stacks. Figure 4. Functional safety example Scope, and Just as Importantly, What Is Out of Scope Ensuring the new working group stays focused, boundaries are created for what is defined as in and out of scope. For example: In Scope Externally visible chiplet behavior required by real-time, safety-critical physical AI Classification of candidate requirements into baseline, optional profile, or guidance Overlap resolution with baseline OCP FCSA and UCIe Compliance profiles and the evidence needed to support safety claims Out of Scope Chiplet microarchitecture and implementation choices Die-to-die physical and link layers already owned by UCIe and BOW AI model, algorithm, and training behavior Product certification and vendor-specific software stacks The exclusions do most of the work here. By ceding the physical and link layers to UCIe and BOW, staying out of microarchitecture, and declining to touch models or certification, the group reserves one territory for itself: the observable contract between chiplets, and the evidence that the contract holds. Everything a supplier competes with remains a supplier decision. Why Cadence Is Leading this with Co-Chair imec The two organizations bring complementary solution expertise to the table. Cadence contributes the system and design perspective: chiplet architecture, interface implementation, system analysis, and verification. That matters disproportionately here, because a significant share of the candidate requirements are not about moving data at all. They are about proving things. Verification, compliance, and safety-case evidence is itself a candidate requirement, calling for capability declarations, compliance-profile declarations, test results, counters, logs, timestamped event records, trace snapshots, fault-injection results, timing measurements, and security-attestation records. A specification that defines behavior but not how to evidence it delivers interoperability on paper only. Imec contributes cutting-edge research and expertise in autonomous-edge systems, workload partitioning, chiplet architectures, and advanced integration technologies, helping identify and validate critical requirements before they become formal specifications. This contribution is already reflected in the industry working record and the Autonomous Edge Chiplet Program (AECP), where imec has helped bring together leading ecosystem players to shape the future of chiplet-based autonomous-edge platforms. Through active technical leadership, imec has driven discussions from high-level concepts toward concrete, implementable requirements. Key contributions include defining the scope of system-level interfaces, sideband communication, reset and boot mechanisms, and championing capability discovery as a foundation for interoperability. Imec has also advocated a system-centric management approach, ensuring that power and operational states are managed coherently across the entire chiplet system rather than at the individual die level. Finally, the leadership posture suits OCP. Neither company is arriving with a finished specification to ratify. What is on the table is a baseline choice, a structure proposal, and a candidate requirement list explicitly described as an input for discussion rather than a finalized requirement set. What’s Next The next step is to turn this proposed framework into a community-developed specification. Cadence and imec will work through the OCP FCSA community to refine the architecture requirements, identify where existing standards can be reused, define interoperable profiles and supporting evidence, and validate the approach against representative physical AI platforms. Broad participation from chiplet suppliers, system developers, integrators, and safety and security experts will be essential to ensure the resulting standard is practical, testable, and ready to support trusted physical AI systems at scale.ucieIPchipletsphysical aiOCP FCSAimecOCPhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/74712/performance-advisor-in-allegro-x-pcb-editor-identifying-and-resolving-database-performance-bottlenecksFri, 16 Oct 2026 11:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:15d22453-ce44-41e4-86a4-90ed26413a9evidhyaparameswariLarge and complex PCB designs can sometimes experience slower interactive operations, delayed DRC updates, or reduced editing responsiveness. To help diagnose and address these issues, Allegro X PCB Editor includes the Performance Advisor , a diagnostic utility integrated within the Database Check (DB Doctor) workflow. What is Performance Advisor? Performance Advisor is a specialized analysis tool that examines the PCB design database and identifies conditions that may contribute to degraded application performance. Instead of manually investigating potential causes, designers can use Performance Advisor to pinpoint database settings, constraint configurations, and design characteristics that may be impacting responsiveness. The tool provides actionable recommendations that help improve design efficiency and overall editing performance. Benefits of Using Performance Advisor By routinely running Performance Advisor, users can: Identify database-related performance issues before they become critical. Detect constraint configurations that may cause slow editing operations. Receive practical recommendations for improving design responsiveness. Optimize shape handling and database settings for large designs. Improve overall PCB layout productivity and user experience. How to Access Performance Advisor Performance Advisor is available through the Database Check (DB Doctor) utility in Allegro X PCB Editor. Navigation Path:Tools → Database Check Running Database Check launches the analysis process, where Performance Advisor evaluates the current design and presents any detected performance concerns along with recommended corrective actions.https://community.cadence.com/cadence_blogs_8/b/cic/posts/virtuoso-ai-studio-finding-specific-y-values-with-vertical-markersFri, 16 Oct 2026 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4007d459-0403-4354-826c-84bd293c87f7Udit RajputAs Virtuoso Studio transforms to Virtuoso AI Studio, our ViraStack AI Super Agent reinvents analog and custom design by autonomously orchestrating front-to-back agentic workflows, from design intent to layout, leveraging LLMs in the best possible way. Powered by silicon-proven Cadence engines, ViraStack AI Super Agent reduces manual effort and iterations in the most challenging analog and custom flows, using mental models to understand the design intent and making intelligent trade-offs along the way. In this blog series, learn how ViraStack AI Super Agent can help you design faster, better. Whether you're examining a single waveform or several traces in the graph window of Virtuoso Visualization and Analysis XL, vertical markers make it easy to jump directly to points where a trace reaches a specific y-axis value. With vertical markers and the Specific Y Value point-of-interest (POI) criterion, you can: instantly locate the desired y-axis values across multiple traces in different strips restrict searches to selected traces for more focused analysis find all occurrences of a particular value on a bus signal enter bus values using hexadecimal, binary, octal notations, without requiring manual conversions navigate through successive occurrences using bindkey shortcuts Quickly Locate a Specific Y-Value Across Multiple Traces Suppose you want to find all occurrences where a signal reaches 2.0 V . You can navigate directly between matching points on the trace by first specifying 2.0 V as the target y-value, and then using the Next POI and Previous POI commands or the n and p bindkeys, respectively. Each time you navigate, the selected vertical marker automatically snaps to the next data point where the y-axis value of the trace matches the specified value. The real benefit of this feature becomes apparent when multiple traces are plotted in different strips within the same graph window. With the target y-axis value set to 2.0 V , pressing the n bindkey moves the marker to a point on trace 10 where the y-axis value is 2.0 V . Press the n bindkey again, and the marker jumps to a point on trace 11 where the y-axis value is 2.0 V . When you press the n bindkey again, the marker moves to a point on trace 12 where the y-axis value is 2.0 V. This way, you quickly traverse matching values across all displayed traces without manually switching between them. Search for Specific Y-Values Only Within Selected Traces Sometimes you do not want to search every trace in the graph. Instead, you may be interested in only a subset of signals. Vertical markers support this workflow as well. For example, if traces 10, 11, and 12 are displayed in separate strips, you can limit navigation to traces 10 and 12 while excluding trace 11. With a target y-axis value of 2.0 V , pressing the n or p bindkey navigates only between matching points on the selected traces, 10 and 12. This selective navigation helps you focus only on the signals that matter, making investigations cleaner and more efficient. Find Specific Y-Values on Bus Signals Vertical markers aren't limited to analog waveforms. You can also use them to locate specific y-axis values on bus signals, making it easy to navigate long digital captures and jump directly to the bus states that matter. For example, you want to find every point where a bus signal equals 2F . You can enter the value using different prefixes: 0x2F (hexadecimal), 0b00101111 (binary), or 057 (octal). All three representations correspond to the same value. Regardless of which representation you use, pressing the n bindkey moves the vertical marker to the next location on the bus where the value is 0x2F . This flexibility allows you to specify the bus value in the format that is most convenient for your analysis, without requiring manual conversions. If you specify a bus value without a prefix, its interpretation depends on the currently selected radix of the bus signal. For example, consider a bus displayed with a hexadecimal radix. If you enter, 47 , the value is interpreted as 0x47 , which corresponds to 71 (decimal), not 47 (decimal). This behavior keeps navigation consistent with the way the bus data is currently displayed. However, it is important to keep the active radix in mind when entering values without prefixes. Specific y-value navigation with vertical markers makes waveform analysis more focused and efficient. By quickly bringing relevant data points into view, the feature helps you spend less time searching and more time examining the signal behavior that matters. Related Resources Videos Enhancements in Vertical Markers Product Manuals Virtuoso Visualization and Analysis XL User Guide Contact Us Subscribe to receive email notifications about our latest Custom IC Design blog posts. This upgrade is built with you in mind. Whether you're a long-time Virtuoso Studio user or just getting started, we'd love to know what you think. Share your feedback with us at custom_ic_blogs . For more information on Cadence circuit design products and services, visit www.cadence.com . Happy Reading! Udit RajputAnalog Design EnvironmentVirtuoso AI StudioViVa-XLVirtuoso StudioADE ExplorerbusVirtuoso Visualization and Analysis XLvirtuoso visualization and analysisMixed-SignalVirtuoso Analog Design EnvironmentVirtuosoViVAADE ArtistVirtuoso Video Diaryanalog designCustom ICViraStack AI Super AgentADE Assemblerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59683/tcl-script-to-replace-selected-parts-with-a-component-from-library/1434952Fri, 16 Oct 2026 09:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f40af384-46b5-48ba-a3b6-660c6133c226PatEscherCadAP can you provide information what the following variables are doing? bUpdate: int bNewVersion: int updateDPfromLib: int when we use RepalceInst ..... 1 1 1 1 1, then we ecounter an OrCAD crash when afterwards trying to do an LinkDatabasePart. so it seems that it is related to these booleans (I suspect it is bUdate or bNewVersion)https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/agentic-ai-for-pcb-and-advanced-packaging-designThu, 15 Oct 2026 15:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7dd0c04a-10dc-4963-95f7-7d6143d9d541Reela SamuelAs AI workloads grow, more engineering challenges extend beyond the chip itself to the package that brings compute, memory, power, and cooling together. The HBM4 standard is designed to increase memory bandwidth, while evolving stacking requirements add to the importance of power delivery and thermal management. Co-packaged optics bring optical engines closer to switching or compute ASICs, creating opportunities to support higher-bandwidth interconnects while introducing challenges in signal integrity, mechanical integration, and thermal design. 3D integration increases interconnect density and can concentrate heat, making placement, routing, and power-delivery decisions more consequential. The challenge is to evaluate placement options, routing strategies, and package architectures against electrical, thermal, mechanical, and manufacturing constraints while limiting unnecessary design iterations and rework. Agentic AI offers a way to coordinate this work through established EDA tools. Rather than automating only an individual placement or routing operation, an agentic design flow can coordinate multiple tasks and use analysis results to guide subsequent steps, helping engineers evaluate alternatives within defined constraints. Why PCB and Packaging Workflows Are Difficult to Coordinate Chip design has benefited from decades of mature automation. Synthesis, place-and-route, formal verification, timing signoff, and physical verification have progressively streamlined design implementation and verification. PCB and advanced-package development, by contrast, often requires coordination across layout, electrical and thermal analysis, mechanical engineering, and manufacturing. This coordination becomes more demanding in 2.5D and 3D-IC designs . Multi-die systems, interposers, fan-out structures, HBM integration, and complex substrates introduce constraints that span silicon, package, board, and product enclosure domains. Although these domains may rely on separate tools and engineering workflows, their decisions are interdependent. A change in component or die placement, for example, can affect routing feasibility, signal integrity, power delivery, and thermal performance, triggering further design changes and analysis. Evaluate Component Placement Alternatives Earlier Component placement establishes many of the conditions that shape the rest of a PCB or package layout. These requirements can compete. Moving a high-power device may improve cooling but complicate its power connections. Shortening a critical signal path may increase congestion elsewhere. AI-assisted placement can accelerate the evaluation of candidate arrangements against specified constraints, making it more practical to compare alternatives that would otherwise require substantial engineering time. The Cadence AuraStack AI Super Agent can deliver up to 15X higher productivity and 2X faster time to market. Accelerate Substrate Routing Without Compromising Quality Advanced-package substrates connect dies, bridges, redistribution layers, and external interfaces through dense networks of interconnects. In AI and high-performance computing (HPC) designs, completing these connections within limited routing space and layer budgets can be a substantial implementation task. A route must satisfy more than connectivity. Depending on the interface, it may need to meet impedance and crosstalk limits, preserve return paths, control layer transitions, and comply with substrate manufacturing rules. Changes to individual routes can also affect congestion and neighboring connections. Cadence is advancing AI-driven automation for advanced-package implementation to help customers achieve design convergence for increasingly complex multi-die systems. In a multi-year collaboration, substrate autorouting using the AuraStack AI Super Agent demonstrated up to 100X higher productivity , with a quality of results comparable to manual routing. Automating repetitive connections can free engineers to focus on difficult routes, critical regions, and cases that require engineering judgment. The resulting implementation must still meet the relevant electrical and manufacturing requirements. Multiphysics Analysis Connects Findings to Design Changes A package can satisfy its placement and routing requirements yet still fail to meet electrical, thermal, or mechanical specifications. Signal-integrity analysis evaluates interconnect behavior, while power-integrity analysis examines power delivery under specified operating conditions. Thermal analysis assesses heat generation and dissipation; mechanical simulation evaluates stresses and deformation. Consider a high-power device that meets its routing requirements but exceeds its temperature limit under the expected workload. Engineers may need to relocate the device or revise the cooling arrangement. Either change can affect signal paths, power connections, and routing space. Addressing the thermal issue may require relocating the device or revising the cooling arrangement, followed by renewed checks of routing feasibility and electrical and thermal performance. An agentic design flow can coordinate these steps by identifying relevant tasks, invoking available tools, and using their results to determine what needs to happen next. The analyses themselves remain grounded in the underlying simulation tools, which evaluate the design against the applicable physical models and constraints. AuraStack AI Super Agent Coordinates PCB and Advanced-Packaging Workflows The Cadence AuraStack AI Super Agent brings agentic AI to PCB and advanced packaging design. Powered by Allegro AI Studio it works from engineering intent expressed in natural language and coordinates tasks across the design workflow using Cadence implementation and analysis technologies. The AuraStack AI Super Agent is tightly integrated with Cadence solutions for PCB design, IC packaging, and multiphysics analysis, including Allegro AI Studio , Allegro X Design Platform , Allegro X Advanced Package Designer , Sigrity X Platform , Clarity 3D Solver , and Celsius Studio Platform . A central part of this approach is its mental model , a contextual representation of the design that captures its hierarchy, relationships, constraints, and engineering intent. This model provides the context that the AuraStack AI Super Agent uses to plan and run tasks, rather than treating each request as an isolated operation. Results from implementation and analysis can inform subsequent steps, helping preserve design intent across successive tasks. The AuraStack AI Super Agent supports workflows spanning system planning, library and constraint management, placement, routing, design for manufacturability (DFM), and multiphysics analysis. The tasks it can coordinate depend on the design environment, available data, tool integration, and engineering controls. The underlying EDA tools perform the design and physics-based analysis, with engineers reviewing results and validating that the design meets its requirements. Adopting Agentic Workflows with Engineering Oversight Teams adopting agentic workflows can start with bounded tasks such as library creation, constraint capture, component placement, and repetitive substrate routing. They can then extend the automation to broader implementation and analysis workflows as tool integration and validation processes mature. Engineers need to define the design intent and constraints, determine which tasks can be delegated, and specify the checks required before accepting results. Architectural decisions and changes affecting critical performance margins or compliance require appropriate engineering review. Productivity should be measured alongside design quality. Useful measures include the number of design iterations and rework loops, late-stage violations, the number of viable placement candidates or routing strategies evaluated, and the effort required to validate the resulting design. Faster execution alone does not demonstrate an improvement if it creates additional downstream work. Applying Agentic AI to System-Level Design PCB and advanced-package design increasingly requires engineers to evaluate electrical, thermal, mechanical, and manufacturing constraints together. Agentic AI offers a way to coordinate more of this work within established EDA workflows, helping teams explore design alternatives and manage iterations as system complexity grows. FAQs About Agentic AI for PCB and Advanced Packaging Design What is agentic AI in PCB and advanced packaging design? Agentic AI coordinates multi-step engineering tasks across PCB and advanced-package design workflows. Rather than automating only an individual operation, an AI agent can interpret engineering intent, plan relevant tasks, invoke connected EDA tools, and use their results to guide subsequent steps. This helps engineers evaluate design alternatives while working within defined constraints and engineering controls. How does agentic AI differ from conventional EDA automation? Conventional EDA automation typically executes defined operations, optimization routines, or rule-based workflows. Agentic AI adds a coordination layer that can use engineering context and task results to determine subsequent actions across connected tools. The underlying EDA tools still perform implementation and physics-based analysis; the agent coordinates the workflow rather than replacing those capabilities. How can agentic AI improve PCB and advanced-package design productivity? Agentic AI can help automate repetitive implementation tasks, coordinate work across tools, and evaluate placement or routing alternatives more efficiently. Potential benefits include reduced manual effort, fewer unnecessary iterations, and more time for engineers to address difficult routing problems and critical design tradeoffs. Actual productivity gains depend on the task, design complexity, tool integration, and validation requirements. How does agentic AI support signal integrity, power integrity, and thermal analysis? An agentic workflow can coordinate relevant implementation and analysis tasks, using findings from one step to inform subsequent actions. For example, a thermal analysis result may prompt a placement or cooling change, followed by checks of routing feasibility, signal integrity, and power delivery. The underlying simulation tools evaluate the design using their applicable physical models and constraints. What is the AuraStack AI Super Agent, and how does it support PCB and advanced-package design? The Cadence AuraStack AI Super Agent , powered by Allegro AI Studio , brings agentic AI to PCB and advanced-package design. It uses engineering intent expressed in natural language and a contextual representation of the design, called a mental model, to coordinate tasks across supported implementation and analysis workflows. Its scope includes system planning, library and constraint management, placement, routing, design for manufacturability, and multiphysics analysis, depending on the design environment and available tool integrations. Can agentic AI replace engineers in PCB and advanced-package design? No. Agentic AI can coordinate tasks and automate portions of implementation, but engineers remain responsible for defining design intent, setting constraints, reviewing results, and validating the design. Architectural decisions and changes affecting critical electrical, thermal, mechanical, or manufacturing requirements still require appropriate engineering judgment and verification. How should engineering teams measure the value of agentic AI? Teams should measure productivity alongside design quality. Useful indicators include time spent on repetitive tasks, design iterations and rework loops, late-stage constraint violations, the number of viable placement or routing alternatives evaluated, and the effort required to validate results. Faster execution alone does not demonstrate value if it increases downstream rework or compromises design requirements. Explore how Cadence AI Super Agents apply this approach to digital implementation and signoff in the next blog. Ready to explore agentic AI for your design workflow?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/74699/trying-to-load-a-olb-librray-file/1434951Thu, 15 Oct 2026 14:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:84ddc1e3-ef7e-4a47-9397-c49b174d09a5digital1Hi TechnoBobby Sorry I didn't make myself clear i have already created a dsn project and i want to load the .opj file into the design under the project window unfortunately your answer loaded the .olb file into a differnt session than my original design. What I am doing is converting a kicad schematic into orcad this is so i can import Altium Binary mentor graphics binary cad star and a few others Im starting with the schematic and then i will be doing the pcb thsi will be useful as kicad can convert a gerber into a pcb file you then have to load the components. But i do appreciate the help thank youhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/74710/bulk-hierarchy-path-editing-of-50-deepprobes-is-it-possible-at-all-within-virtuoso/1434950Thu, 15 Oct 2026 13:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:18ce141b-b1d6-4e59-9db6-aa406d9af753rod1This procedure worked for me in the end. t_find and t_replace are strings. procedure(sge_replaceProbeNode(t_find t_replace) prog((cv win selObjs probes updated cdf p oldVal newVal) ; Validate that both arguments are strings unless(stringp(t_find) error("sge_replaceProbeNode: argument 'find' must be a string, got: %L" t_find) ) unless(stringp(t_replace) error("sge_replaceProbeNode: argument 'replace' must be a string, got: %L" t_replace) ) probes = list() updated = list() win = hiGetCurrentWindow() unless(win error("sge_replaceProbeNode: No active schematic window found.") ) cv = geGetEditCellView() unless(cv error("sge_replaceProbeNode: No editable cellview found.") ) selObjs = geGetSelSet(win) ; Filter to deepprobe instances only foreach(obj selObjs when(obj~>objType == "inst" && obj~>cellName == "deepprobe" probes = cons(obj probes) ) ) ; Remind user and exit if no deepprobes selected unless(probes warn("sge_replaceProbeNode: No deepprobe instances are currently selected. Please select at least one deepprobe and run again.") return() ) ; Apply replacement rexCompile(t_find) foreach(inst probes cdf = cdfGetInstCDF(inst) when(cdf p = cdfFindParamByName(cdf "probeNode") when(p && p~>value && rexMatchp(t_find p~>value) oldVal = p~>value newVal = rexReplace(oldVal t_replace 0) p~>value = newVal updated = cons(list(inst~>name oldVal newVal) updated) ) ) ) dbSave(cv) if(updated then printf("sge_replaceProbeNode: Updated %d deepprobe instance(s):\n" length(updated)) foreach(entry updated printf(" %s: \"%s\" -> \"%s\"\n" car(entry) cadr(entry) caddr(entry)) ) else warn("sge_replaceProbeNode: %d deepprobe(s) selected but none had \"%s\" in probeNode." length(probes) t_find) ) return(updated) )https://community.cadence.com/cadence_technology_forums/f/logic-design/74711/lec-logic-equivalence-check-hang-debugThu, 15 Oct 2026 11:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3c3f6282-44cc-43b1-948f-6399150d4577SimhanAnalogFor my small register bank design( with 50 flops and some address decoder logic) after synthesis when I try to run lec the rtl2fvmap lec hangs at the step write_hier_compare_dofile hier_tmp2.lec.do -verbose -noexact_pin_match -constraint -usage \ -replace -balanced_extraction -input_output_pin_equivalence \ -prepend_string "report_design_data; report_unmapped_points -summary; report_unmapped_points -notmapped; analyze_datapath -module -verbose; eval analyze_datapath $DATAPATH_SOLVER_OPTION -verbose" the below is the terminal. It is stuck at this state for several hours. -------------------------------------------------------------------------------- // Starting hierarchical dofile generation ... -------------------------------------------------------------------------------- // Total Matching Module Instance Pairs = 3 // Module Instantiation Ratio in Golden = 1.00 // Module Instantiation Ratio in Revised = 1.00 // Gathering Instance Boundary Information ... // Extracting Constraints in Golden ... By modifying the do file step to below(removed options -constraint and -input_output_pin_equivalence) the lec passes in 2 minutes. I think these 2 options help remove false failures. Since my lec is passing I don't need them I guess. Am I right? And is this a know bug in the lec tool? write_hier_compare_dofile hier_tmp2.lec.do -verbose -noexact_pin_match -usage \ -replace -balanced_extraction \ -prepend_string "report_design_data; report_unmapped_points -summary; report_unmapped_points -notmapped; analyze_datapath -module -verbose; eval analyze_datapath $DATAPATH_SOLVER_OPTION -verbose" The lec also passes without needing any modification if I reduce the flops to 30 or increase it to 70 etc.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/74710/bulk-hierarchy-path-editing-of-50-deepprobes-is-it-possible-at-all-within-virtuosoThu, 15 Oct 2026 10:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8354ad36-4330-45f1-b824-b80e653c0311rod1I got 70 deepprobes with paths like "path.to.block1.nodeN" , where N=1,...70. Now, I need to copy the same deepprobes and change all their paths to "path.to.block2.nodeN", where block2 is simply another instance of the cell instantiated by block1 as well, all nodes are equal. Is there a way to do this without changing each deepprobe's path one by one? If somehow Virtuoso allowed VIM-style editing, this could be done in 5 seconds.VirtuosoSchematic EditorADE Assemblerhttps://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/74709/ai-powered-innovation-meets-next-generation-si-pi-analysis-cadence-sigrity-clarity-2026-1Thu, 15 Oct 2026 05:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:96f8d978-2d56-41f3-bd36-8e183e9061deRenu VibhaIntroducing Cadence® Sigrity ™ & Clarity ™ 2026.1 We are pleased to announce the availability of Cadence® Sigrity ™ & Clarity ™ 2026.1 , delivering new capabilities and workflow enhancements for signal integrity (SI), power integrity (PI), advanced packaging, thermal analysis, and 3D electromagnetic simulation. The 2026.1 release introduces innovations designed to help engineering teams address the growing complexity of AI infrastructure, high-performance computing, networking, advanced packaging, and next-generation electronic systems. Release Highlights AI Antenna Designer in Clarity ™ 3D Layout for antenna topology generation and optimization. Clarity ™ 3D Power Integrity (Clarity PI) for broadband power integrity analysis of ICs, interposers, and advanced package designs. GPU acceleration support in Clarity and Celsius ™ workflows on supported Linux platforms supported GPUs. This includes support for deployments on the Cadence Millennium AI Supercomputer powered by the NVIDIA Blackwell Platform. Monte Carlo and Fast Monte Carlo analysis for statistical design exploration and variability assessment. Enhanced support for rigid-flex design workflows . New ECAD-MCAD co-design capabilities for full-system 3D EM simulation workflows. Productivity enhancements across Sigrity ™ , Clarity ™ , PowerSI®, PowerDC ™ , OptimizePI ™ workflows. The release is now available for download from Cadence Downloads . Download the release from Cadence Downloads . To learn more, explore the latest documentation, videos, tutorials, and training resources available through Cadence Learning and Support We look forward to hearing about your experience with Sigrity & Clarity 2026.1.