https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66216/pcb-substarte-generation-on-virtuoso-and-em-simulation-using-emxWed, 29 Jul 2026 08:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:46fdaa52-a6b0-44ad-883b-8711fdb4923busercpHi I want PCB substarte generation on virtuoso like ads substarte editor. After that, EM simulation using EMX. I want to manually generate and set PCB substate, but I don't know this is possible using GPDK 45nm. Regarding EMX document, we can generate EMX proc file to meet our wants, however it's not compatible with GPDK 45nm layer information.. Could you please help to share how to setup PCB substarte and EM simulation at virtuoso and EMX tool, or any proper tool..?https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66215/simplifying-power-amplifier-design-flowWed, 29 Jul 2026 07:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7fdc215e-3858-48c6-80f0-c33669620500Renu VibhaIs your power amplifier design flow efficient enough, or are you missing optimization opportunities? This Rapid Adoption Kit (RAK) will uncover the findings Power amplifier design flow in AWRDE Big ideas. Bigger impact. Watch this space for more!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66214/your-access-to-on-demand-webinar-from-wall-to-rail-turning-rules-of-thumb-into-proofWed, 29 Jul 2026 05:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:81556c0f-516b-4f14-a04c-39cc6d0ef844Renu VibhaRules of thumb don't pass safety reviews; proof does. This webinar demonstrates constraint-driven flyback design in Cadence’s Allegro X Design Platform and PSpice. See how to verify hot-loop geometry, isolation spacing, and startup behavior before you build hardware. For more details , check From Wall to Rail – Turning Rules of Thumb into Proof | Cadencehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66213/your-access-to-on-demand-webinar-from-wall-to-rail-turning-rules-of-thumb-into-proofWed, 29 Jul 2026 05:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1f7c7459-c6f6-467c-bcb9-19dfcd7f8087Renu VibhaRules of thumb don't pass safety reviews; proof does. This webinar demonstrates constraint-driven flyback design in Cadence’s Allegro X Design Platform and PSpice. See how to verify hot-loop geometry, isolation spacing, and startup behavior before you build hardware. For more details , check From Wall to Rail – Turning Rules of Thumb into Proof | Cadencehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66200/donut-pad/1409011Wed, 29 Jul 2026 02:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c887c89e-6223-4066-9269-9f2ad74952b3ElecguyAre you confused because they both look "donut" shaped? A donut pad offers more versatility when designing it. You get to input the outer and inner diameter. I guess you could create plated thru pads using a donut pad. But I think it has to do with the final use.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66196/automated-gnd-via-shield-fence-generation-for-rf-trace/1409010Wed, 29 Jul 2026 02:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:513826c9-9245-47b7-8225-622648725747ElecguyThe Place -> Via Array command is the way to go. Unfortunately, it's a kind of buggy command of the tool. I'm not saying it's bad, but things like what you're describing happen. My advice is: use it as a guide or whenever it works as you want it to work. For the rest, do it manuallyhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66211/easy-gui-for-shortcut-key-creation-in-allegro-x/1409009Wed, 29 Jul 2026 00:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:dc1f86ed-86bb-48c5-b787-ae6ffedd11d3excellon1So Allegro has four methods to do this. The first is a traditional hotkey. The second is a macro, similar to a hot key that calls a script. The third would be graphical in nature and is called Stroke Editor, lastly Skill would be a programming language that runs under Allegro. One of the barriers is knowing the command to use, however it can be figured out fairly easily by recording a script. Basically a script are the commands behind actions you take in the pcb editor. For example add a connect, add a via etc. These actions can form a hotkey basis or be replayed. You can load the script in a text editor to see the commands If your new to Allegro. The easiest method for you is to go into the find filter and un-check everything first. Then check "Symbols" & "Text" To toggle between the two, you just use the tab key to cycle back and forth between each of them. The slickest Method, would be to use the Stroke Editor where by you can create a graphical doodle to represent the command. In the pcb editor you simply draw the doodle and the command executes. It's extremely fast. It means your hand wont need to leave the mouse to run a command. Have a look, the stroke editor us under tools utilities. Allegro comes with some default strokes. In the pcb editor you hold down the ctrl key and use the right mouse button to draw the doodle on the screen. Best regardshttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66212/how-to-use-variable-in-defcellTue, 28 Jul 2026 19:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:886f48b0-2b6e-4f49-89c9-e330c884e5f6MorrisDHI am open to suggestions if there is a better way to create a symbol cellview but the following is what I am using. defcell("realCellName" defSymbol( nil ) ) It works fine for a basic symbol with no pins which is all I need. It creates a symbol cellview under the cell "realCellName". The following does not work as expected. cellName = "realCellName" defcell(cellName defSymbol( nil )) It creates a new cell named "cellName" instead of parsing the variable. Is it not possible for defcell to recognize variables? Or maybe there is a better way to create simple symbol cellviews. Thankshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66205/unable-to-export-odb/1409007Tue, 28 Jul 2026 15:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:25a9f81f-aa11-4237-920c-9f00177fcbceoldmouldyCheck that you can Generate Artwork / Export Gerber. Check the Classes and Subclasses for all the Films and check that you don't have any entries with (null) for the Class, or Subclass, delete (Cut) any of those that you find.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66210/scheduled-nets---how-to-quickly-remove/1409006Tue, 28 Jul 2026 14:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:38914180-bf27-4b74-a320-34a6c2254978avantThanks Steve! There's always something new to learn in Allegro, even after using it for thirty years.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/66203/can-t-skip-devices-inside-subckt-in-checks-asserts/1409005Tue, 28 Jul 2026 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:948a0d2b-082b-428b-970a-b439abc45744Andrew BeckettThe skip_dev_inside_subckt should be a list of hierarchical paths to specific subckt instances, not the names of the subckt masters that are being skipped. That said, I couldn't get it to work in my quick tests (I may have done something stupid and didn't have time today to experiment properly). For the second, you should be able to cross-select the violating instance from the Checks/Asserts results. I suggest you contact customer support (use the Case menu after logging in to submit a support case). Andrewhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66211/easy-gui-for-shortcut-key-creation-in-allegro-xTue, 28 Jul 2026 14:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6cfe252b-46d8-4d71-8ac2-afd46d225ce9AB202510225018Hello everyone, I was curious if there is a GUI for setting shortcut keys. I am unsure how to do exact functions via the command line. How to remove the funckey after setting it exedra. It seems like it would be easy for Cadence to have a GUI for setting shortcut keys like they do in the Capture program but I haven't seen anything online about it. My main goal is to setup a quick key to toggle selections on the Design Object Find Filter. Example: go from only having symbols selected, to only having text selected. Any help would be greatly appreciated!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66210/scheduled-nets---how-to-quickly-remove/1409004Tue, 28 Jul 2026 14:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bb44789e-a2eb-4de4-936c-43ea90903049steveYou should be able to do this using Constraint Manager. Go to Electrical - Net - Routing - Wiring, look for the Schedule column. It will either have User defined or a schedule type set. Choose the items and right click - Clear.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66210/scheduled-nets---how-to-quickly-removeTue, 28 Jul 2026 13:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8164e31c-084c-41f9-afbd-b24a6c45b52davantIs there a quick way to unschedule nets other than one at a time? Allegro Designer 17.2.https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/66194/join-us-for-our-next-live-experts-session-powersi-s-parameter-analysis-on-july-29th-2026/1409003Tue, 28 Jul 2026 10:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b92ff419-1efc-4f92-af75-3ba0d720cc3aRenu Vibha1 day to go! We look forward to an engaging session, do join on July 29th at 8:30-9:30PM IST .https://community.cadence.com/cadence_blogs_8/b/cic/posts/from-layout-to-silicon-mastering-parasitic-extraction-with-the-quantus-trainingTue, 28 Jul 2026 10:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ffe47706-3712-49ea-ba59-3d2ba7caeb98JentilTomYou have closed timing. Your simulations look clean. Everything seems ready for tapeout. Then comes post-layout simulation—and suddenly, your design behaves differently. What changed? Parasitics . Hidden resistances, capacitances, and inductances can significantly impact timing, power, and signal integrity, especially in advanced-node designs. As a result, parasitic extraction has become essential for achieving design closure. The Cadence Quantus Extraction Solution helps engineers bridge the gap between layout and silicon accuracy. To accelerate learning, Cadence offers the Quantus Training Series: QRCTransT1 – Overview and Technology Setup QRCTransT2 – Parasitic Extraction QRCTransT3 – Extracted View Flows and Advanced Features Why Parasitic Extraction Is Critical in Advanced Nodes Parasitic extraction computes unwanted electrical effects from layout geometry and integrates them into simulation models. At modern nodes: Interconnect delays can dominate up to a significant portion of the total delay Coupling capacitance leads to crosstalk and noise issues Massive parasitic data increases simulation complexity Without accurate extraction: Timing signoff may fail Signal integrity issues go undetected Silicon may not behave as expected This makes parasitic extraction not just important—but mission-critical for first-pass silicon success. Quantus: Built for Today’s Extraction Challenges The Quantus Extraction Solution delivers: Foundry-certified high-accuracy modeling 3D field solver for precise capacitance extraction Support for hierarchical and flat RLCK extraction Massively parallel architecture for faster runtime It supports digital, analog, and RF designs, making it a unified solution across design domains. The Quantus Training Series: A Structured Learning Path The 2-day Quantus Training Series is designed to take engineers from fundamentals to advanced-node mastery. QRCTransT1 – Overview and Technology Setup Core Foundation The journey starts with QRCTransT1, a half-day course in which engineers build a strong conceptual and practical foundation. What You Learn: Fundamentals of parasitic extraction (lumped vs. distributed models) Challenges in design closure due to parasitics Introduction to u nderstand the Techgen–Quantus flow for accurate parasitic extraction and qrcTechFile creation Setting up extraction environments (GUI and command-line) Running extraction and creating extracted views Leveraging parallel processing for performance Outcome: You gain the ability to set up and execute extraction flows confidently. QRCTransT2 – Parasitic Extraction Deep Dive Hands-on Extraction Expertise Once the basics are in place, the QRCTransT2 dives into the core of the extraction process over 8 hours. What You Learn: Complete Pegasus–Quantus extraction flow Running extraction in GUI and batch modes RLCK extraction (resistance, inductance, capacitance, substrate) Handling: Hierarchical extraction Multi-corner extraction Incremental extraction for ECO cycles Advanced reduction techniques for managing large parasitic datasets Practical lab-driven learning: Generating input data from LVS Running RC extraction Configuring extraction settings and filters Outcome: You become capable of handling real-world extraction scenarios in production flows. QRCTransT3 – Advanced Features and EMIR Integration Advanced Node Mastery The final stage, QRCTransT3, a half-day course, focuses on advanced-node challenges and post-extraction analysis. What You Learn: Extraction challenges in FinFET and advanced-node designs Advanced modeling techniques (DPT, airgap dielectrics, 3D-IC) Generated extracted views and integration with simulation EMIR (Electromigration and IR Drop) analysis flows using Voltus Post-layout analysis for reliability and performance Outcome: You gain expertise in advanced-node design validation and reliability analysis. How the Training Aligns with Real Design Flows A typical Quantus extraction flow involves: Creating technology models (qrcTechFile) using Techgen Running LVS (e.g., Pegasus ) Performing extraction with Quantus Generating extracted netlists or views for simulation The training series mirrors this exactly—ensuring engineers are industry-ready. Flexible Learning, Recognition, and Your Next Step The Quantus Training Series is available in both classroom and Interactive Learning (iLS) formats, with an optional Accelerated Learning mode to help engineers gain expertise more efficiently. Accelerated Learning courses are marked with this symbol in our Learning Maps . After completing the training, you can take the post-course quiz to earn a Digital Badge that validates your knowledge and can be shared on professional and social platforms. Whether you are building foundational skills or advancing your expertise in parasitic extraction, now is the time to invest in your skills. Start your Quantus learning journey today and accelerate your path toward silicon-accurate design success. Related Resources Product Page Quantus Extraction Solution Related Courses Quantus Transistor-Level T1: Overview and Technology Setup Quantus Transistor-Level T2: Parasitic Extraction Quantus Transistor-Level T3: Extracted View Flows and Advanced Features Pegasus Verification System Related Blogs Intelligent Custom Signoff Closure with the Quantus Insight Solution Training Insights Accelerated Learning–The More You Know, the Faster You Go Your Skills Deserve a Passport: Showcase Your Expertise with Digital Badges Do You Have Access to the Cadence ASK Portal? If not, follow the steps below to create your account: On the Cadence ASK portal, select Register Now and provide the requested information on the Registration page. You will need an email address and host ID to sign up. If you need help with registration, contact support@cadence.com . To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails. If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training . About Knowledge Booster Training Bytes Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis. Subscribe to receive email notifications about our latest Custom IC Design blog posts. Jentil K Tom, on behalf of the Cadence Training Teamparasitic-aware designparasiticQuantus Extraction SolutionqrcQuantusParasitic extractionparasiticshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66209/modeling-schottky-diodes-in-pspice-understanding-is-and-n-parametersTue, 28 Jul 2026 09:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:130fd8fd-ad13-471e-873a-f63a25816d73IshaSSchottky diodes are indispensable part of modern hardware design. Their low forward voltage drop (typically 0.2–0.45 V versus 0.6–0.7 V for a standard PN junction) and near-zero reverse recovery time make them go-to choice in high-frequency switching power supplies, RF signal detection, OR-ing circuits, and flyback clamp networks. Wherever efficiency, speed, or tight voltage headroom matters, a Schottky is usually in the signal path. But selecting the right device is only half the job. Simulating it accurately is the other half and that's where most designs quietly go wrong. In PSpice, a Schottky diode's behavior is governed primarily by two model parameters: IS (reverse saturation current) and N (ideality factor). These two values define the entire shape of the I-V curve. Get them right, and your simulation predicts forward voltage drop, power dissipation, and switching behavior with confidence. Get them wrong - which happens whenever you use an unverified default model - and every downstream calculation built on that simulation is off including thermal margins, efficiency estimates and gate drive timing. This post walks through how to tune IS and N in PSpice using nested DC sweeps, so your simulation matches the datasheet and holds up on the bench. The diode current is governed by the equation: I = IS (e^(V / (N·Vt)) − 1) This indicates that both IS and N play an important role in determining the forward voltage characteristics. IS (Reverse Saturation Current): Determines where along the voltage axis the I-V curve sits. In Schottky models, IS is typically several orders of magnitude larger than in standard PN junctions — often in the μA to mA range — which is the physical reason Schottky diodes conduct at a lower forward voltage. A lower IS shifts the curve to the right, increasing Vf for a given forward current. A higher IS shifts it left, reducing Vf. N (Ideality Factor): Controls the steepness of the exponential rise. An ideal diode has N = 1; real Schottky devices typically fall between 1.0 and 2.2 depending on the junction technology and operating region. A higher N flattens the curve — you need more voltage to drive the same current — and also makes the forward voltage more sensitive to temperature variation. Together, IS sets the operating point and N shapes the curve around it. Both need to be calibrated to the actual device for the simulation to be trustworthy. Simulation Steps: Perform a DC sweep analysis on a forward-biased circuit. Use Parametric sweeps to vary IS and N independently. Example ranges: IS: 3e-04 to 3e-08 N: 2.2 to 3 Observe resulting changes in forward voltage and current characteristics. Effect of IS (Reverse Saturation Current): Forward voltage drop can be tuned by modifying IS. A lower IS results in a higher forward voltage for the same current. Effect of N (Ideality Factor): Controls the slope of the I-V curve. Changing N modifies exponential behavior and deviation from ideal characteristics. This approach helps in accurately matching the diode model to real device behavior and achieving reliable simulation results. Have you run into a Schottky (or any diode) model that just wouldn’t match the datasheet or your bench data? Drop your experience in the comments – what device, what mismatch, and how you resolved it. Happy Learning!!PSPICE Model Editorpspice probe windowpspice simulationPspice libraryhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66208/how-do-i-use-the-tcl-command-to-save-an-image-and-a-visio-drawing-file-from-a-dsn-file-as-a-new-file/1409002Tue, 28 Jul 2026 08:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6f42b37d-359c-405f-8d37-3588d58cf9a8TechnoBobbyHi FK202606088435 , Please try the following TCL code on a selected image on schematic page: set bmpInst [GetSelectedObjects] set bmp [$bmpInst GetDboBitMap] set outStr [DboTclHelper_sMakeStdStr ""] set status [DboState] DboBitMap_sGetBase64ImageData $bmp $outStr $status set base64Data [DboTclHelper_sGetConstCharPtr $outStr] COrBase64Encoder_decodeToFile $base64Data "c:/temp/image.png" Hope this helps!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66198/spacemousen-3d-mouse-support/1409001Tue, 28 Jul 2026 07:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0b279bc5-247e-4871-8875-72c9526bb5e5rg13An enhancement Cadence change request is already in place for this requirement.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/66208/how-do-i-use-the-tcl-command-to-save-an-image-and-a-visio-drawing-file-from-a-dsn-file-as-a-new-fileTue, 28 Jul 2026 06:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0a6c069e-b008-449b-8f93-4e505539dac8FK202606088435Hi, My current version is 23.1. How do I use the TCL command to save an image and a Visio drawing file from a DSN file as a new file? I've tried the Base64 decoding mentioned on pages 762 and 767 of the OrCAD_Capture_TclTk_Extensions.pdf file, but it's not working. The code snippet provided is: Invalid command name "DboTclHelper_sGetBase64ImageData"