https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66150/feature-quiz-do-you-know-this-awr-toolThu, 09 Jul 2026 05:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a3079e17-e5f1-4f8b-882c-572a84e0cc4eOscPnYou need to quickly see how circuit performance changes when component values are adjusted— without manually editing parameters and re-running simulations each time. Which AWR feature would you use? A. Yield Analysis B. Tuner C. EM Extract D. Design Rule Check Vote your answer below before checking the comments!microwaveRFDesignAWRDEquizhttps://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66131/python-com-api-how-to-set-per-shape-mesh-properties-shape-properties-mesh-on-em-structure-shapes/1408886Thu, 09 Jul 2026 05:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b679dab1-2653-477f-b858-4126cb3a608bOscPnAs far as the documented AWR DE COM/Python APIs show, there is no supported API to create a per-shape mesh override.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66149/shape-degassing-parameters-extraction-using-skill-in-allegro-apdWed, 08 Jul 2026 23:02:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fc82f7a0-54dc-4782-bf33-d356d80fb82aAnanthVedalaLMI'm trying to extract the values set for a specific degassing pattern using skill , but instead of name , i'm unable to get anything else , is there any way we can extract the void array parameters and void spacing constraints that we set in the shape degassing tool, instead of using GUI, is there any other option to set those parameters for a pattern and also extract them usually i'm getting the pattern name in this way shapedbId->shapeBoundary->prop-> DEGAS_SHAPE_PROPERTIES which just leaves me with the name of the pattern used on the shape, but unable to figure out how do we actually get these parameters using skill other questions i have , Are these parameters for the dynamic shapes global or local ? and how are these parameters stored in the databasedegassingDegas patternsAllegro SkillSkill scripthttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65933/default-shortcut-keys-are-not-working/1408882Wed, 08 Jul 2026 21:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3360524c-6415-4aea-98f3-00d317571ca3passedpawnI've had this exact thing happen many times. I did report it to Cadence. Restarting the software fixes temporarily. I have not discovered the cause.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66142/add-collision-detection-and-ability-to-xy-snap-to-faces-to-3dx/1408881Wed, 08 Jul 2026 18:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d085efa5-bb67-4c8a-becf-0835cbeff9b2JM20241029170Thanks Steve, got the collision constraints working. Nice that it can be automated, but way harder to maintain and tell exactly where the collision is happening compared to the old tool. Still having an issue where I can't select a face on the mechanical step model (the red face on the top board) and then XY mate it to a face on the inside of a connector on the main board (the actual brd file that launched the canvas). This used to work in the old tool, I used it to put a 2280 M.2 SSD into a socket that was a component on the main board.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408880Wed, 08 Jul 2026 15:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:120eca6b-845e-4790-a661-23f029831876IshaSThank you everyone for the great questions and engagement today. Appreciate your participation!!https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408879Wed, 08 Jul 2026 15:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bb6ba50f-b5b5-47d0-b840-bf5539f18052IshaSOk, so for your local workspace, projects are stored in home location. Open Fole explorer>In address bar type %home% There you will find folder structure as below The projects are stored here inside projects folder of workspace.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408878Wed, 08 Jul 2026 15:02:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:135465a7-6044-4df4-a661-9637f4d1aca6LogicNetYes this is working. Are the projects which are visible in my local workspace stored in my local PC?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66148/board-geometry-design_outline-vs-outline-and-what-are-the-real-world-implicationsWed, 08 Jul 2026 15:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f5de4e72-1a17-4894-aaf5-7eae91550450Electro NodeHi everyone, I've always been a bit confused about the difference between Board Geometry / DESIGN_OUTLINE and the legacy Board Geometry / OUTLINE subclasses in Allegro X PCB Editor. If the board boundary is defined using Board Geometry / OUTLINE instead of DESIGN_OUTLINE , could that cause any issues during manufacturing, fabrication outputs, MCAD exchange, or other downstream processes? Or is it still generally acceptable in production designs? I'd love to hear how others are handling this in their workflows. Have you encountered any problems, benefits, or best practices related to using one versus the other? Looking forward to learning from your experiences! Best Regards,PCB designAllegro PCB Editorboard outlinehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408877Wed, 08 Jul 2026 14:58:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6833bdcd-320a-479d-b810-c990f1a3fb34TechnoBobbyYou can automate the export of variant.lst from Part Manager by setting the AutomationFlag to 1. For additional details, please refer to the second half of the following article and use the script attached there: Title: How to create Variants.lst file URL: ask.cadence.com/.../article-viewerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/65932/how-to-generate-parasitic-reports-for-all-nets-in-allegro-pcb-editor-and-how-are-they-calculated/1408876Wed, 08 Jul 2026 14:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:45b5b302-c2eb-4433-a001-fa1fb00b05b1Electro NodeHi FXNTX01, The above-mentioned report works fine for generating reports for all nets. However, I have not yet tried generating reports by layers. I will test this as well and let you know my findings. Best Regards,https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408875Wed, 08 Jul 2026 14:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:29d3e21f-3b06-4ef5-b8c8-5e0b49e23edaIS202606094723Hi, How to create variants.lst file using scripthttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66072/how-do-you-route-multiple-nets-like-buses-efficiently-in-allegro-pcb-editor/1408874Wed, 08 Jul 2026 14:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:533f2051-8989-401d-8927-20fdffc2e4c3Electro NodeHi excellon1, Thank you so much for such a detailed explanation. Your explanation will not only help me, but it will also help others as well. I have been exploring the bundling options for routing DDR, and this is a very useful feature. I am still exploring these options, so if you have any additional resources or tips, please feel free to share them with me. These bundling features are very useful in these types of scenarios. I have also been exploring the possibility of routing multiple data buses at a time. Thanks once again for your response. Best regardshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408873Wed, 08 Jul 2026 14:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4e02d3d8-cb6f-4dc8-9cc0-ab20641b1bceIshaSHere is the snapshot from where you can chance the Do Not Stuff text to Do Not Include as per your requirement. Changing this text will reflect for DNI parts. You can access it from Options>CIS Configuration>Administrative Preferences. Hope this helps.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408872Wed, 08 Jul 2026 14:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ff888d85-a2c6-490d-8783-260739fd71cbLogicNetYes, it works. Can you also tell if there is any option to change "Do not Stuff" text to some custom text name like "Do Not Inlcude"?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408871Wed, 08 Jul 2026 14:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1270eaba-01bd-4721-82c6-3a4cc9f3c329IshaSYou can change it from Options>Preferences>Part Not Present. Change the color from grey to different color. This will get reflected for DNI parts. Try this.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408870Wed, 08 Jul 2026 14:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2bc2ae63-b96a-4cb8-8846-72453e7edd25LogicNetIs there any option to change color of my DNI parts in variant view mode?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408869Wed, 08 Jul 2026 14:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:eec5edbc-859d-49f3-9af4-994b5b6fbb4dIshaSHi LogicNet, In workspace we have option to view revisions of project published to shared workspace. You can download and use design compare for making comparison of DSN files. Try this hope it helps.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408868Wed, 08 Jul 2026 14:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:42b906f2-0697-4fee-aa69-f40ff572fdf7LogicNetHi, I am working on a project on shared workspace. Is there any option to see revisions of my design and compare those revisions with each other?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/66130/don-t-miss-our-live-interactive-upcoming-orcad-x-session-on-july-8th-wednesday/1408867Wed, 08 Jul 2026 14:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a96a64ba-dbab-47c7-9001-93c5f095d84fIshaSWelcome everyone and thank you for joining today’s Expert Session. Please feel free to post your questions any time—we’re here to help. Let's keep it interactive!!