https://community.cadence.com/cadence_blogs_8/b/jcid/posts/virtuoso-studio-sTue, 29 Sep 2026 00:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1283a5b3-8baa-49b9-a7fc-6d63b8c47922Custom IC JapanAIを活用した新しいカスタム設計ソリューションであるVirtuoso Studioは、当社が30年にわたり培ってきた業界知識とリーダーシップを生かし、革新的な機能、比類のない生産性を実現するために刷新されたインフラストラクチャ、そして従来の設計領域を超える新たなレベルの統合を提供します。このブログシリーズでは、最高のアナログ設計ツールがさらに進化し、困難な設計課題への対応をどのように支援するのかをご紹介します。 今日のRFおよびマイクロ波設計では、Sパラメータデータ自体は豊富に存在しています。しかし、そのデータから有意義な知見を引き出すためには、追加のシミュレーションやカスタムスクリプト、あるいは手作業による計算が必要になることが少なくありません。 Virtuoso Visualization and Analysis XLのS-Parameterアシスタントは、まさにこの課題を解決するために設計されています。 S-Parameterアシスタントでは、Touchstone（.snp）ファイルを読み込み、スミスチャートを使用してSパラメータの特性を即座に可視化できます。さらに、インダクタンス（L）、抵抗（R）、キャパシタンス（C）、品質係数（Q）、およびその他の周波数依存の指標を含む主要な電気特性を自動的に導出します。これにより、生データから実際の理解へと短時間で移行できます。 次の図は、.s2pファイルから抽出したデータを使用してプロットした、2ポートネットワーク内のシングルエンドインダクタのL、R、C、Q、およびSパラメータを示しています。 受動部品の解析を簡素化 最新のモジュールや基板には、大規模なマルチポートSパラメータネットワーク内に受動部品が組み込まれていることがよくあります。こうしたデータセットからインダクタなどの個々の素子を解析するのは容易ではありません。端子を手作業で特定し、対象部品を分離したうえで、有用な電気特性を抽出する必要があるためです。 S-Parameterアシスタントでは、特定の部品に関連するポートを選択するだけで、残りの処理が自動化されるため、このプロセスを簡素化できます。選択した素子を周囲のネットワークから分離してディエンベディングした後、インダクタンス、インピーダンス、品質係数（Q）などのプロットを生成します。煩雑な手作業が不要になり、複雑なマルチポート設計内に組み込まれた受動部品であっても、性能を容易に検証できます。 Sパラメータアシスタントの使用方法 Sパラメータアシスタントの使用方法は簡単です。 Touchstone形式のSパラメータ（.snp）ファイルを読み込みます。 ［Device Type］のオプションである［Category］と［Device］を指定します。 プロットする電気特性とSパラメータを選択します。 残りの処理はアシスタントが実行します。結果は直感的に理解できる形式で可視化されるため、デバイス性能をすばやく把握し、十分な情報に基づいて設計判断を行うことができます。 関連リソース ビデオ S-Parameter Assistant in Virtuoso: Plotting Device Parameters from S-Parameter Data S‑Parameter Assistant in Virtuoso: Supported Files, Devices, and Calculations S-Parameter Assistant in Virtuoso: Illustrating Supported Device Types and Practical Example 製品マニュアル Virtuoso Visualization and Analysis XL User Guide オンラインコース S-Parameter Simulations Using Spectre in Virtuoso Studio ぜひお楽しみください！ Udit Rajput ケイデンスの回路設計製品およびサービスの詳細については、 www.cadence.com をご参照ください。 お問い合わせ ご質問や一般的なフィードバック、または今後のブログ・トピックのご提案は、日本ケイデンス フィールド・マーケティング部 cdsj_info@cadence.com までメールでお問い合わせください。 カスタムIC／ミックスシグナル Blogs 無料定期購読のご案内 新規ブログが公開された際に通知を受け取る方法を、 こちら にてご案内しています。是非ご登録ください。S-parameter AnalysisS-parameterViVa-XLVirtuoso StudioADE ExplorerVirtuoso Visualization and Analysis XLvirtuoso visualization and analysisS-Parameter Quality Checking toolVirtuoso Analog Design EnvironmentSpectreViVAADE Artistjapanese blogCustom IC DesignADE Assemblerhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/70342/skill-error-if-too-many-arguments-missing-then-error-on-running-if-command/1421106Mon, 28 Sep 2026 23:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e07979c9-24b5-4f33-8fa2-b5d77048d1adDavidJHutchinsWhy doesn't the sklint tool report these issues?https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70344/writing-lists-to-fileMon, 28 Sep 2026 21:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f9c428be-b59a-49b0-b3b3-243e5fbaedadblankmanHi, I have a question in relation to storing captured data to file for recall. Brief background: I have 2 procedures, one stores the list of layers in the Layer Palette that are visible, and the other recalls those layers and sets them visible, ie for storing of custom layer visibility sets. (aware that this feature already exists within Virtuoso, coding as part of a larger project) Question I have: when the layers set is stored, and then Virtuoso is closed and reopened, the layers set is lost. What I want to do is store the layers list to file, so that any stored list is permanently stored irrespective of whether the tool is closed. I also want to be able to store 5 different lists of layers, ie for storing of 5 different custom layer visibility sets at a time. Having not approached a task like this before in skill, I am wondering if there is any examples of this I could reference, or any advice how to go about accomplishing this? Thanks very much in advancehttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70343/placing-a-dock-window-to-left-of-layout-screen-above-the-layer-palette/1421104Mon, 28 Sep 2026 16:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:acee760c-d278-48fe-9ddd-dd42559fc16ablankmanThanks Steve, appreciate the response, though hoping to do this by default upon calling hiDockWindow , ie without having to drag and drop. Know if this is possible? Thanks againhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/66331/how-to-get-ade-outputs-priority/1421103Mon, 28 Sep 2026 15:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:296f12d4-2086-4b6c-ac22-7768213ed8d6kkdesboisThanks for the confirmation. Case created.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70343/placing-a-dock-window-to-left-of-layout-screen-above-the-layer-palette/1421102Mon, 28 Sep 2026 15:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b62ff88b-b94e-4731-9822-b11cc2c9d825SZ20260803361Hello, There is a simple way to achieve this, you can drag the dockwindow to the top of the Palette. Thanks, Stevehttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/70343/placing-a-dock-window-to-left-of-layout-screen-above-the-layer-paletteMon, 28 Sep 2026 14:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6a7237fd-b06d-4cbb-bd16-43ab5ce070bbblankmanHi, I am trying to dock a window to the left of my layout window, and above the existing Layer Palette. However no matter what value I place for "?index" (see below), it always places the dock window on the left side, but BELOW the Layer Palette, ie bottom left of layout window. Is it possible to dock the window to the TOP left of the layout window? Thanks hiDockWindow hiDockWindow( ?window w_dwindowID [ ?session g_sessionWindowID ] [ ?side s_side ] [ ?index x_index ] [ ?unmapped g_unmapped ] [ ?tabOnto w_dwindowID ] )https://community.cadence.com/cadence_blogs_8/b/cic/posts/make-the-right-layout-decisions-earlierMon, 28 Sep 2026 11:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1eeeaf73-6fb2-44a9-a94a-a99d70081635Prasanna KumarImagine planning a complex custom IC layout while several lower-level blocks are still being implemented. The top-level team must make early decisions about block organization, placement, area boundaries, connectivity, routing resources, and ownership, even though the final physical hierarchy is not yet complete. When decisions are made with limited top-level context or early estimates, teams may later need to revisit pin positions, aspect ratios, placement, or routing. Virtuoso Design Planner provides a structured methodology that uses schematic hierarchy, Virtual Hierarchy, connectivity analysis, placement planning, and congestion analysis to develop an informed early design plan and prepare it for team implementation. Why Early Design Planning Is Essential Physical design planning is a critical stage in complex custom IC layout. Traditional bottom-up and top-down approaches each provide useful structure, but they can also introduce challenges when lower-level work proceeds without sufficient full-design context or when top-level decisions rely on estimates that later change. How Virtuoso Design Planner Supports Early Layout Planning Virtuoso Design Planner is a connectivity-based planning capability within Virtuoso Layout Suite EXL. It helps layout teams generate and organize a layout plan, examine hierarchy and connectivity, refine placement, and analyze congestion before detailed implementation is complete. Training Course Offering on Design Planner Cadence Customer Education offers a hands-on training course to help layout professionals use Virtuoso Design Planner effectively. Through structured learning and practical exercises, learners explore how to organize hierarchy, analyze connectivity, refine placement, evaluate congestion, and prepare a design plan for team implementation. The hands-on labs reinforce these concepts through practical exercises covering: Setting up the design planning environment Generating and viewing virtual hierarchies Analyzing net connectivity Building an early design plan Creating rows and running automatic placement Running congestion analysis Preparing the design for team implementation The training features guided, practical labs centered on real-world custom IC layout scenarios. These activities enhance the course material by allowing learners to practice design-planning concepts, refine an initial design plan, and prepare for physical layout implementation in the Virtuoso environment. Enroll in the Course Ready to build a more informed layout plan before detailed implementation begins? Enroll in the Virtuoso Layout Pro: T9 Virtuoso Design Planner course to gain hands-on experience with Virtual Hierarchy, connectivity analysis, CSV-based Soft Block P-cells, placement refinement, congestion analysis, and team-oriented layout implementation. View the VLPT9 course page and datasheet Earn Your Badge This training has a Digital Badge available. You can earn this badge by passing the exam for this course. Take the Training Accelerated Way The faster you finish your online training, the sooner you can claim your Digital Badge . Want to know how accelerated learning works? Our video walks you through the pre-quiz, navigation, and essential features. This is just the beginning. We're regularly adding new Accelerated Learning titles . Accelerated Learning courses are marked with this symbol in our Learning Maps . Videos What Is Virtuoso Design Planner? Features of the Virtuoso Design Planner The Virtuoso Design Planner Flow Advantages of Virtuoso Design Planner Flow Over Bottom-Up and Top-Down Flows Starting the Virtuoso Design Planner: Menu, Toolbar, and Design_Planning Workspace Virtuoso Design Planning: Hierarchical Make Virtual Related Resources Virtuoso Design Planner and Congestion Analysis Virtuoso Design Planning and Analysis User Guide, IC 25.1 Virtuoso Design Planning and Analysis, IC 25.1Virtuoso StudioLayout EXLMixed-SignalLayout SuiteVirtuoso Analog Design EnvironmentLayoutVirtuosoDesign PlannerVirtuoso Layout Suite EXLVirtuoso Layout SuiteCustom IChttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/70340/allegro-x-capture-will-not-launch-again-after-closing-the-application/1421101Mon, 28 Sep 2026 10:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b447a886-60d0-40e4-8cf3-db2b9f5b19d7Zhifeng JinI took these screenshots when I reproduced this issue a moment ago. CPU and memory usage are visible in the images. The background process keeps running; it will auto‑terminate after roughly 10 to 30 minutes. I’ve noticed this problem occurs much more easily if you open many schematic pages and then close the software.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/70340/allegro-x-capture-will-not-launch-again-after-closing-the-application/1421100Mon, 28 Sep 2026 10:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a468fe0e-6618-4082-a1db-8e955113c5ffZhifeng Jinhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/70342/skill-error-if-too-many-arguments-missing-then-error-on-running-if-commandMon, 28 Sep 2026 10:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2bea1d7b-56bc-4cca-9fa0-7401389821f8JuanCRCheck out the following statement: if( order parameters = foreach( mapcar param order (get cdfgData param)) parameters = (getq cdfgData parameters) ) It seems a then keyword is missing, and the tool does not complain . Now let's say you add a printf command like: if( order parameters = foreach( mapcar param order (get cdfgData param)) parameters = (getq cdfgData parameters) printf("%L" parameters~>values) ) In this case, you'll get the following error: *Error* if: too many arguments (missing then?) - (order (parameters = foreach(mapcar param order get(cdfgData param))) (parameters = (cdfgData->parameters)) printf("%L" (parameters~>values))) Why did you get this error, and how can you fix it? I'll show you: Consider a simpler example. In the command line, type: x = 2 Then enter this expression: if( (x > 5) 1 0) The tool will evaluate whether x > 5; if so, a "1" will be returned; otherwise, a "0" will be returned. Since 2 is less than 5, you will see the returned value as follows: => 0 This is because the "if" command falls into the following syntax: if( g_condition g_thenExpression [ g_elseExpression ] ) Now, if a fourth argument is added ("3" in this case) as follows: if( (x > 5) 1 0 3 ) You will now see the following error: *Error* if: too many arguments (missing then?) - ((x > 5) 1 0 3) You get it because the ' compact ' form of the if command is no longer applied. The syntax now becomes: if( g_condition then g_thenExpr1 ... [ else g_elseExpr1 ... ] ) Thus, you need to add a " then " for a complete "if" command. If it is not present, the tool will generate an error message. It is recommended to use the " then " and " else " keywords to avoid such syntax errors and reduce confusion. There are times when the 'compact' form is handy without the bloat of then...else , but it is generally recommended to add these keywords. Check the SKILL Language Reference for details. Here's an excerpt from the input for the if conditional: Description This command selectively evaluates two groups of one or more expressions. The syntax is as follows: if( g_condition g_thenExpression [ g_elseExpression ] ) => g_result The "if" form evaluates g_condition , typically a relational expression, and executes g_thenExpression if the condition is true (that is, its value is non-nil); otherwise, g_elseExpression is executed. The value returned by "if" is the value of the corresponding expression evaluated. The "if" form can therefore be used to evaluate expressions conditionally. if( g_condition then g_thenExpr1 ... [ else g_elseExpr1 ... ] ) => g_result The second form of "if" uses the keywords "then" and "else" to group expressions into a conditional execution sequence. If the condition is true, the sequence of expressions between "then" and "else" (or the end of the if form) is evaluated, with the value of the last expression evaluated returned as the value of the form. If the condition is nil instead, the sequence of expressions following the "else" keyword (if any) is evaluated instead. Again, the value of the last expression evaluated is returned as the value of the form.Allegro Skillhttps://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/trusted-autonomy-with-cadence-ai-super-agents-and-nvidia-agent-safety-platformMon, 28 Sep 2026 09:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:630b1d7a-68ac-41bd-ae6e-e64ffaceed93CorporateCadence AI Super Agents bring engineering trusted autonomy to semiconductor workflows, enabled by NVIDIA Open Agent Safety Platform. Autonomous engineering is no longer about whether AI can reason about chip design. The harder question is whether that reasoning can safely translate into actions inside a complex semiconductor engineering environment. The answer requires more than a capable model. It requires governance across the systems in which autonomous agents operate. Cadence and NVIDIA are addressing this challenge with Cadence AI Super Agents operating within NVIDIA Open Agent Safety Platform . The platform provides full-stack governance and control for autonomous agents, with NVIDIA OpenShell providing the secure runtime boundary in which agents can run under defined policies, and NVIDIA Sentry, running on NVIDIA BlueField-4 and built on NVIDIA DOCA , enforcing policy outside the agent’s execution environment. For semiconductor engineering, that distinction matters. An agent may need to access design artifacts, invoke EDA technologies, launch simulations, inspect results, modify RTL, and determine what to do next. Giving it the intelligence to perform those actions is one problem. Giving it the authority to perform them without unrestricted access to the surrounding environment is another. An agent can determine an action without being able to grant itself permission to perform that action. That separation is the foundation for trusted autonomous engineering. Three Forms of Authority Autonomous engineering requires three different forms of authority. Reasoning authority - What should I do next? Cadence AI Super Agents interpret engineering intent, understand workflow context, and determine the next action. Engineering authority - Did the action produce a valid engineering result? Cadence EDA technologies provide the domain-specific computation and evidence needed to evaluate the design and determine whether it meets the relevant requirements. Execution authority - Am I permitted to perform that action? The NVIDIA Agent Safety Platform provides governance and control across the agent stack, with NVIDIA OpenShell establishing the runtime boundary that governs what an agent can access and execute. These roles are complementary but not interchangeable. An agent can determine that RTL should change without having unrestricted permission to modify files or invoke arbitrary processes. A simulation or formal engine can establish that a design change failed verification without deciding what resources the agent may access. An execution environment can enforce a policy without determining whether a particular RTL change is the right engineering decision. Cadence makes the autonomy engineering-aware. NVIDIA provides the governance architecture that makes autonomous execution controllable. An Architecture for Governed Autonomy The architecture connects those forms of authority while keeping their responsibilities distinct. Layer Role Technology Engineering intent Defines the objective, constraints, and success criteria Engineer Reasoning authority Interprets intent, plans actions, and orchestrates the workflow Cadence AI Super Agents Engineering authority Performs domain-specific analysis and establishes engineering evidence Cadence EDA technologies Governance and control Defines and enforces boundaries for autonomous execution NVIDIA Agent Safety Platform Runtime execution Provides the secure execution boundary for agents NVIDIA OpenShell Engineering results Provide evidence that informs the next action Cadence EDA technologies From Runtime Boundary to Full-Stack Agent Governance NVIDIA OpenShell addresses the execution boundary around the agent. The NVIDIA Open Agent Safety Platform extends that governance across the broader stack that supports autonomous systems. NVIDIA Sentry adds an out-of-band watchdog that runs on NVIDIA BlueField-4 DPUs to continuously monitor agent behavior. Sentry can quarantine agents that attempt to move outside their boundaries in milliseconds. The platform brings together agent runtime software, security enforcement, monitoring, and infrastructure controls. This includes NVIDIA OpenShell for the secure runtime boundary, NVIDIA Sentry , an out-of-band watchdog for monitoring and enforcing agent behavior and thinking on NVIDIA BlueField-4, and NVIDIA Vera CPU infrastructure for efficient agent execution. This broader architecture is relevant as autonomous engineering moves beyond individual tool calls. An agent may interact with files and processes, consume compute resources, access network services, and coordinate work across multiple engineering technologies. Governance therefore needs to extend beyond the agent itself to the systems that enable its work. For Cadence workflows, this provides a foundation for scaling autonomous engineering while keeping access, execution, and system-level controls governed independently of the agent's reasoning. Separating Governance from Engineering Truth Governance answers one question: What is the agent allowed to do? Engineering answers another: What happened when it did it? That distinction is critical in semiconductor design. A language model can generate RTL. But generating a plausible artifact is only the beginning. The design has to be exercised through engineering technologies that can establish whether it behaves as required. Cadence AI Super Agents bring that engineering context into the autonomous loop. They can understand the design objective, orchestrate the workflow, invoke the appropriate Cadence technologies, interpret engineering results, and determine what to do next. The resulting loop is: Reason → Execute → Measure → Diagnose → Modify → Re-execute In a digital design workflow: RTL → Testbench → Simulation → Evidence → Diagnosis → RTL Modification → Formal Verification → Regression → Next Iteration A failed simulation is evidence that can change the next engineering decision. A formal violation can change the design hypothesis. A successful run provides evidence that allows the workflow to advance. The workflow responds to what it discovers. From Architecture to Measurable Engineering Impact The value of this architecture is ultimately measured by what it changes in an engineering workflow. Cadence has demonstrated that impact with ChipStack AI Super Agent . At NVIDIA, engineers are using ChipStack AI Super Agent to run dynamic simulations with Cadence Xcelium Logic Simulator and Jasper Formal Verification . The resulting workflow delivers more than 40X faster RTL validation, reducing a typical five-week verification loop to less than one day. The result provides a concrete example of the three forms of authority working together: Reasoning authority: ChipStack AI Super Agent determines what to do next based on the engineering objective and observed results. Engineering authority: Xcelium and Jasper provide the computational evidence used to evaluate the design. Execution authority: NVIDIA's governance and execution technologies provide the environment in which those autonomous actions can occur. Traditionally, engineers coordinated these stages manually. ChipStack can connect them into an autonomous loop, using intermediate results to determine the next action and continue toward closure. The significance of the result is not simply the reduction in elapsed time. It demonstrates that simulation, formal analysis, debug, and RTL modification can operate as a connected autonomous process rather than a series of manually coordinated tasks. NVIDIA is also applying ChipStack AI super Agent to the verification of its own chip designs. The collaboration therefore spans both the technology stack and its practical application: Cadence brings autonomous engineering and EDA technologies, while NVIDIA provides the accelerated infrastructure and agent safety architecture for governed execution. From Individual Agents to Agentic Engineering ChipStack AI Super Agent is one example of this model in digital front-end design and verification. The same approach extends across other parts of the semiconductor workflow. Cadence AI Super Agents can specialize around different engineering domains: ChipStack AI Super Agent for digital front-end design and verification. ViraStack AI Super Agent for custom and analog design. InnoStack AI Super Agent for digital implementation and signoff workflows. AuraStack AI Super Agent for PCB design and advanced packaging. AgentStack for orchestration across specialized agents and engineering tasks. As these capabilities expand, autonomous workflows can move beyond a single agent and task to coordinate specialized agents across a larger engineering flow, with the same governance principles applying across the environment. The result is a model in which agents reason about engineering objectives. Cadence technologies establish engineering truth. The execution environment governs what agents are permitted to do. What Changes When Engineering Becomes Autonomous? Traditional automation executes a sequence defined in advance. Autonomous engineering starts with an engineering objective and determines the work required to move toward it. The engineer still defines the objective, constraints, success criteria, and boundaries. What changes is how the work between those conditions is managed. Instead of specifying every transition, the engineer can allow the autonomous system to evaluate results, choose the next step, and continue until the defined conditions are met or human intervention is required. This changes the unit of automation from an individual task to a workflow. Simulation, formal analysis, debugging, design modification, and subsequent verification can become part of one continuous engineering process rather than separate activities coordinated manually. It also changes where engineers spend their time. The focus moves from managing routine transitions between tools toward defining objectives, reviewing results, handling exceptions, and making decisions that require engineering judgment. As autonomous systems take on more of the workflow, the engineering environment must support that autonomy without removing human control. The objective remains defined by the engineer, while the system manages execution within the boundaries established for the work. Why Engineering Context Matters An agent that can call an EDA tool is not necessarily an engineering agent. Semiconductor design depends on relationships between specifications, RTL, verification environments, simulation results, formal properties, implementation constraints, and signoff requirements. Cadence AI Super Agents are being built around these workflows and technologies. They connect engineering intent to the appropriate technologies, interpret the evidence those technologies produce, and use that evidence to determine what happens next. The agent, therefore, needs to understand not only what it can do, but what an action means in the context of the design. The Path Forward As autonomous workflows expand across the semiconductor design flow, the challenge shifts from making individual agents capable to making them reliable participants in real engineering environments. Cadence AI Super Agents bring engineering intent and workflow context into that environment. Cadence technologies provide the evidence needed to evaluate each step. NVIDIA provides the infrastructure and agent safety architecture that governs autonomous execution, with OpenShell providing the runtime boundary. Trusted autonomy does not require giving an agent unrestricted authority. It requires giving it enough authority to do meaningful work, grounding its decisions in engineering evidence, and keeping execution within explicit boundaries. That is the foundation for autonomous engineering that can scale without requiring engineers to surrender control. Explore trusted autonomous engineering with Cadence AI Super Agents and NVIDIA Open Agent Safety Platform technologies. See how engineering-aware AI and governed execution can work together to automate complex semiconductor design workflows. Written by Reela Samuel, Sr. Manager, Marketing Writingfeaturedagentic aiautonomyNVIDIASuper AgentNVIDIA Open Agent Safety PlatformAI/MLhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/70340/allegro-x-capture-will-not-launch-again-after-closing-the-application/1421099Mon, 28 Sep 2026 08:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4d324463-9a4e-4b42-a90d-b4f9fe2b918cIshaSHi Zhifeng, When Capture remains running in the background, what is the CPU and memory utilization of the Capture.exe process. Also, how much time it takes for the process to be killed automatically?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/70337/how-to-set-the-voltage-value-and-type-within-start_reliability-in-site-cpm/1421098Mon, 28 Sep 2026 08:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:773bed13-009c-40ee-a22e-a8b41ad6910drg13Which all nets should be included as Power/Ground, that can be mentioned under START_RELIABILITY section of cpm file but what should be the value of voltage and what should be the type, that has to be defined in Schematic Audi settings GUI.https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/66336/error-orcommn-2302-cannot-initialize-profile/1421097Mon, 28 Sep 2026 06:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:80c0d058-1fd4-45ba-8621-dd57607cf8fdIshaSHi Volker, Yes, please delete the complete CaptureWorkspaceEx folder/ or create backup of it by renaming it to CaptureWorkspaceEx_backup.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/70341/airgap-is-reduced-after-uprevMon, 28 Sep 2026 05:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9deef923-eb27-4b42-8a3f-49e0bb1a33b6SiriHello, After upgrading from version 16.6 to 24.1, the airgap is getting reduced automatically. Could you please let me know what could be causing this behaviour? Is there any setting or change in the newer version that could affect the airgap? Thankshttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/70340/allegro-x-capture-will-not-launch-again-after-closing-the-applicationSun, 27 Sep 2026 15:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e7a3f04d-f374-468c-9356-636ffba96698Zhifeng JinDear Cadence Experts, I frequently run into an issue where Allegro X Capture 25.1 fails to launch again after closing the software. My operating system is Windows 11 25H2, software build is OrCAD Capture 25.1 S050. This problem is not limited to S050; it also existed in previous releases. I’ve just found the root‑cause of this issue. Sometimes after closing OrCAD Capture, its background process does not actually exit. Since OrCAD Capture does not allow multiple instances to run simultaneously, there is no response when you try to launch the software again. My screenshot shows that the OrCAD Capture process remains active in Windows Task Manager even after I close the application. Why the process keeps running after the GUI is closed will need further investigation by Cadence experts.OrCAD X Capture 25.1OrCAD Capturehttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66340/extract-areas-on-the-fpcb-that-do-not-contain-arcs/1421096Sun, 27 Sep 2026 07:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ecd3b6a6-d9f1-4b57-a893-761e7d6a1620HoangkhoipcbThank you! I completely agree.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66340/extract-areas-on-the-fpcb-that-do-not-contain-arcs/1421095Sun, 27 Sep 2026 01:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:09a30b65-6766-4de4-9216-952980fc2b5cSG20260713408Hi Hoangkhoipcb I think other users might need your feature, so I am uploading the modified code. However, the UI window is small. Thank you. axlCmdRegister("create_arc_chk" 'create_arc_chk) (defun create_arc_chk () (let () prog(() all_layers = append(list("All_Layer") axlSubclassRoute(?field 'isEtch)) sel_layer = nth(axlUIMultipleChoice("Select a Layer" all_layers "All Etch Layer") all_layers) when(sel_layer if(sel_layer == "All_Layer" then axlSetFindFilter(?enabled '("noall" "CLINES" "INVISIBLE") ?onButtons '("all")) axlAddSelectAll() clines = axlGetSelSet() else axlVisibleDesign(nil) axlVisibleLayer(strcat("ETCH/" sel_layer) t) axlVisibleLayer(strcat("PIN/" sel_layer) t) axlVisibleLayer(strcat("VIA CLASS/" sel_layer) t) axlVisibleLayer("BOARD GEOMETRY/OUTLINE" t) axlVisibleUpdate(t) axlSetFindFilter(?enabled '("noall" "CLINES") ?onButtons '("all")) axlAddSelectAll() clines = axlGetSelSet() ) ;;if sel_layer axlClearSelSet() tmp_list = nil seg_list = nil Out_file = outfile("create_arc_chk.log" "w") fprintf(Out_file "%-5s %-7s %-10s %s\n" "No" "Angle" "Layer" "Location" ) foreach(cline clines segs = cline->segments foreach(seg segs if(length(member(seg segs)) > 1 then next_seg = cadr(member(seg segs)) if(seg->xy == nil && next_seg->xy == nil then ol = axl_ol_ol2(seg->startEnd next_seg->startEnd) if(member(car(ol) tmp_list) == nil then angle = abs(axlRadToDeg(axlGeoAngleBetweenLines(seg->startEnd next_seg->startEnd))) if(axlGeoEqual(angle 0.0) || axlGeoEqual(angle 180.0) then else push(car(ol) tmp_list) fprintf(Out_file "%-5d %-7.2f %-10s %L\n" length(tmp_list) angle cadr(parseString(seg->layer "/")) car(ol) ) push(seg seg_list) push(next_seg seg_list) ) ) ) ) ) ) close(Out_file) if(length(tmp_list) > 0 then axlHighlightObject(seg_list) axlUIViewFileCreate("create_arc_chk.log" "Arc Segments Check" nil) printf("Errors : %d\n" length(tmp_list)) ) ) ) ) )https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/66340/extract-areas-on-the-fpcb-that-do-not-contain-arcs/1421094Sat, 26 Sep 2026 08:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8a42e346-8faa-435c-ad96-b6c7099f0fc9HoangkhoipcbHi SG,