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See AuraStack AI Super Agent in Action!

Modern AI systems are pushing electronic design into a new phase of complexity. High…

Reela Samuel
• 3 min read
AuraStack AI Super Agent , Allegro X AI , featured , agentic ai , Super Agent

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Corporate
• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design
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Blog - Post List
Latest blogs

Physical Systems Simulation (CAE)

CAE vs CAD vs FEA: Comparing Simulation Methods and When to Use Each

Understand the differences between CAE, CAD, FEA, and physical testing. Learn when…

• 6 min read
Actran , computer-aided engineering , CAE , CAD , FEA , CAE Software

Corporate News

See AuraStack AI Super Agent in Action!

Modern AI systems are pushing electronic design into a new phase of complexity. High…

• 3 min read
AuraStack AI Super Agent , Allegro X AI , featured , agentic ai , Super Agent , AuraStack , AI for design , design for AI , AI

Analog/Custom Design

Achieve Real-World Noise Simulation with Spectre Transient Noise Analysis

From Ideal Signals to Real-World Behavior In today's advanced analog and mixed…

• 5 min read
blended , blended training , Cadence blogs , cadence , learning , Spectre Circuit Simulator , training , Virtuoso ADE , Virtuoso Analog Design Environment , Cadence training , digital badges , training bytes , Virtuoso , Spectre , Cadence certified , learning map , Virtuoso Video Diary , spectre x , online training , Custom IC

Physical Systems Simulation (CAE)

SimManager 2026.1: Streamlining Simulation Data Management for Engineering Teams

Engineering organizations generate and manage vast amounts of simulation data every…

• 2 min read
WhatsNew , EngineeringDataManagement , DataAnalytics , SimManager , SimulationDataManagement , EngineeringAnalytics , MSC Software , CAE , 2026.1 , SimulationProcessManagement , simulation , DataManagement , SPDM

PCB、IC封装：设计与仿真分析

存储接口设计为何不能再忽略电源噪声？

从“信号完整性”走向“兼顾电源影响的信号完整性分析” 随着 DDR4、LPDDR4 等高速存储接口速率持续提升，工程师面临的挑战已不仅是阻抗控制和布线优化，更重要的是在分析信号的同时…

• less than a min read
Chinese blog , DDR4 , 存储接口设计 , 中文 , 信号完整性

PCB、IC封装：设计与仿真分析

为什么只做 SI 或 PI 仿真，已经不足以支撑高速设计签核？

随着 SerDes、DDR5、224Gbps 高速链路等技术快速发展，PCB 设计中的信号完整性（SI）与电源完整性（PI）之间的关系越来越紧密。然而，许多工程师的分析流程仍停留在…

• less than a min read
Chinese blog , 高速设计 , 中文 , SI分析与建模

PCB、IC封装：设计与仿真分析

电动汽车电源模块设计：如何同时解决可靠性与安全性问题？

随着电动汽车续航里程和快充需求不断提升，功率器件正向更高电压、更高电流和更高功率密度演进。但与此同时，电源模块的可靠性挑战也愈发严峻。一个看似微小的封装缺陷或散热问题…

• less than a min read
Chinese blog , 热分析 , 汽车电子 , 中文

PCB、IC封装：设计与仿真分析

AI/ML 如何优化 IBIS-AMI 模型参数？

摘要 随着高速串行链路速率持续提升，IBIS-AMI 模型的参数空间变得更加复杂。传统手动寻优需要大量仿真，成本高且效率低。本文结合 Cadence Sigrity…

• less than a min read
Chinese blog , ml , 中文 , Sigrity , 信号完整性

Analog/Custom Design

Virtuoso Studio: Turning S-Parameter Data into Actionable Insights

Read this blog to learn how the S-Parameter Assistant simplifies RF and microwave…

• 2 min read
S-parameter Analysis , S-parameter , ViVa-XL , Virtuoso Studio , ADE Explorer , Virtuoso Visualization and Analysis XL , virtuoso visualization and analysis , S-Parameter Quality Checking tool , Virtuoso Analog Design Environment , Spectre , ViVA , ADE Artist , Custom IC Design , ADE Assembler

Digital Design

The Odyssey of a Great Floorplan

With the recent release of The Odyssey , audiences are once again following an epic…

• 5 min read
Foorplanning , training bytes , digital implementation , Innovus

Physical Systems Simulation (CAE)

Adams 2026.1: Modernizing the Simulation Experience for Rapid Innovation

As Adams continues to evolve as a trusted solution for multibody dynamics, helping…

• 2 min read
Multibody Dynamics , simulation software , Adams

RF Engineering

Accelerating ASTRO SDR Carrier Board Design with Cadence Visual System Simulator

The Slipstream Design ASTRO Ecosystem platform provides a software-defined radio…

• 4 min read
RF , RF Simulation , analog/RF , VSS , microwave office

System, PCB, & Package Design 

Register Now: Tackling the Complexity of Next-Generation IC Packaging

Today’s IC packaging solutions continue to grow in complexity, posing several challenges…

• less than a min read
Sigrity Aurora , IC Packaging , Sigrity X , Allegro X Advanced Package Designer , Power Integrity , Allegro Package Designer , Signal Integrity , Thermal Analysis

Physical Systems Simulation (CAE)

What Is CAE Software? Computer-Aided Engineering from Simulation to Signoff

Discover what CAE software is, how computer-aided engineering integrates FEA, CFD…

• 10 min read
Beta CAE , CAE , CAE Software

Analog/Custom Design

Analog Design Migration Made Easy With Migration Cockpit

Analog IP remains one of the most valuable and difficult-to-scale assets in semiconductor…

• 5 min read
analog IP , Automated test bench migration , parasitic aware optimization , Front to back Analog Migration , PPA , Analog Design Migration , schematic migration

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design , design for AI , millennium

Digital Design

The 0.1 ns Mistake That Delayed an Entire Chip!

We’ve all been there. You wake up early, get ready on time, leave home exactly as…

• 3 min read
digital badge , digital design , Setup Time , Static timing analysis , Hold TIme , Low Power , Genus , Signoff Analysis , Timing Violations , RTL-to-GDSII , training , OCV , training bytes , Digital Implementation , Innovus , online training , tcl

Digital Design

Stop Coding RTL First - A Smarter Path to Hardware Design Using SystemC

Modern hardware design keeps demanding more -- more speed to market, more flexibility…

• 5 min read
digital badge , Training and Support , Stratus HLS , Cadence blogs , online courses , cadence , training , Stratus , SystemC , Cadence support , cadence learning and support

Physical Systems Simulation (CAE)

Speed Up External Superelement Reduction by 30x with AMSR in MSC Nastran

MSC Nastran pioneered superelements almost four decades ago and, still today, continues…

• 3 min read
physical systems simulation , MSC Nastran , MSC Software , simulation software , CAE
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