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Featured

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
Corporate 22 Jul 2026 • 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
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Blog - Post List
Latest blogs

Life at Cadence

The Power of Yet in the Age of AI

How one keynote on reinvention changed the way I think about careers, AI, and the…

Reela Samuel 3 Aug 2026 • 6 min read
Voices India 2026 , Power of Yet , Voices , AI

Physical Systems Simulation (CAE)

Breaking the Memory Bottleneck with scFAST Solver in Cradle CFD

In large-scale computational fluid dynamics (CFD) , speed is often framed around…

Veena Parthan 3 Aug 2026 • 5 min read
CFD , Aerospace , Cradle CFD , simulation software , scFLOW , scFast Solver

Digital Design

Beyond Moore's Law: Advances in Modern Semiconductor Design

The Shifting Landscape For decades, Moore's Law delivered a simple promise: more…

Udaya Shankar 31 Jul 2026 • 6 min read
digital badge , artificial intelligence , 3D-IC , Cadence Online Support , Logic Design , Cadence training , training bytes , implementation , online training , Full-Chip , DFM , verification

Academic Network

A Scholarship and a Summer at Cadence

The Cadence Future Innovators Scholarship was established to support students working…

Yesenia Carrillo 31 Jul 2026 • 4 min read
CadenceCares , Cadence interns , LifeAtCadence

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai , NVIDIA , advanced packaging , Samsung , AI for design , Ambarella , design for AI , advanced nodes , 3D-IC Technology , design stack , 2nm

Digital Design

Power Grid Verification Flow: A Methodology for High-Coverage Signoff

As semiconductor designs continue to scale in complexity, ensuring robust power integrity…

Vinod Khera 31 Jul 2026 • 3 min read
Power Integrity , voltus training kit , Power Grid Verification

Verification

When the Bug Is in the Waveform, the UALink Story Should Be There Too

Real design debug often ends in the same place: a waveform window full of DUT signals…

Sandeep Grover 31 Jul 2026 • 5 min read
bug , waveform , UALink , Verisium Debug , debugging , verification

SoC and IP

Scale-Up Ethernet Ecosystem Ramps Up: Cadence ESUN Controller IP Available

AI Infrastructure Networking Demands The AI Infrastructure industry is investing…

Ray Davtyan 30 Jul 2026 • 3 min read
controller IP , Design IP , IP , controller , Ethernet standards , Ethernet

Corporate News

AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP

As AI workloads scale in size, complexity, and performance requirements, delivering…

Corporate 30 Jul 2026 • 4 min read
advanced nodes , 3dfabric , AI silicon , TSMC-COUPE , system integration

Corporate News

HPE: Designing Data Centers for AI at Scale

One of the biggest inefficiencies in modern data centers is the disconnect between…

Tanushri Shah 30 Jul 2026 • 2 min read
digital twin , designed with cadence , Cadence Reality Digital Twin Platform

Digital Design

The PPA Grand Prix: Fine-Tuning Designs with Advanced Synthesis

Ever watched a Formula One race and wondered what makes the winning car just a little…

Neha Joshi 30 Jul 2026 • 3 min read
online courses , advanced synthesis , optimization , training bytes , Genus Synthesis Solution , online training

Analog/Custom Design

Virtuoso Studio IC25.1 ISR7 Now Available

Virtuoso Studio IC25.1 ISR7 production release is now available for download.

Virtuoso Release Team 29 Jul 2026 • 5 min read
IC25.1 , Cadence blogs , Virtuoso Studio , IC Release Announcement blog , IC Release Blog , Custom IC Design

Physical Systems Simulation (CAE)

New Software Version Release Announcement for BETA CAE Systems Suite 2026.1

BETA CAE Systems is thrilled to announce the release of the major version 2026.1…

Cadence BETA CAE Software 29 Jul 2026 • 20 min read
CFD , Automotive , physical systems simulation , SPDRM , Aerospace , KOMVOS , computer-aided engineering , Safety , FATIQ , Beta CAE , EPILYSIS , ANSA , design , simulation software , NVH , CAE , BetaCAE , SDA , FEA , CAE Software , meta

Analog/Custom Design

From Layout to Silicon: Mastering Parasitic Extraction with the Quantus Training

From fundamentals to advanced nodes, discover how Quantus training helps VLSI engineers…

JentilTom 28 Jul 2026 • 6 min read
parasitic-aware design , parasitic , Quantus Extraction Solution , qrc , Quantus , Parasitic extraction , parasitics

Digital Design

Your Phone Gets Updates, So Does Your Synthesis Expertise!

Most of us update our phones without ever knowing about the coolest new features…

Neha Joshi 27 Jul 2026 • 2 min read
online courses , training , optimization , training bytes , Genus Synthesis Solution , online training

System, PCB, & Package Design 

Designing Integrated SOI X-Band Radar Switches with Cadence Workflow

RF systems operate under tight budgets for loss, coupling towards unwanted paths…

MSATeam 27 Jul 2026 • 3 min read
Radar Switches , Power Integrity , IC package design , Signal Integrity , Sigrity , Clarity 3D Solver

SoC and IP

Why AI Factories Need Great Interconnect IP, Not Just More Compute

AI infrastructure is often evaluated based on compute: how many accelerators, how…

MBhatnagar 27 Jul 2026 • 3 min read
ucie , IP , AI data center , AI Factories , HBM , memory IP , SerDes IP , interface design

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design , Process Design Kit , Intel Foundry

Learning and Support

Come Join Us and Learn from the Cadence Training Offerings

Are you wondering how to learn Cadence tools and technologies for free? Cadence offers…

Sree Parvathy 27 Jul 2026 • 5 min read
college grads , onboarding , videos , Customer Training , CadenceASK , Self Learning , Cadence Online Support , becomeproductivefast , training , Cadence training , training bytes , Cadence certified , bridgingthelearninggap , cadencetraining , Cadence ASK , Cadence Education Services , learning and support , ask , Cadence Learning and Support portal , TrainingBlogs , support resources , online training , Cadence Support Portal , Cadence support , cadence learning and support
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