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The New Engineering Stack at NVIDIA GTC 2026

Together, accelerated computing and agentic AI are redefining both the engine and…

Corporate
• 4 min read
featured , GTC , NVIDIA , data center , digital twin

Cadence Japan

日本ケイデンス、「働きがいのある会社」 ベスト１００に5年連続で選出

日本ケイデンス・デザイン・システムズ社（横浜市港北区新横浜）は、Great Place To Work® Institute Japan（以下、GPTW Japan…

Cadence Japan
• less than a min read
news story , Culture , featured , japanese blog

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture
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Blog - Post List
Latest blogs

Corporate News

The New Engineering Stack at NVIDIA GTC 2026

Together, accelerated computing and agentic AI are redefining both the engine and…

• 4 min read
featured , GTC , NVIDIA , data center , digital twin , accelerated compute , AI

Data Center

Edge and Micro Data Centers: Powering the Real-Time Digital World

The modern world no longer runs on delayed responses. It runs on immediacy. When…

• 7 min read
edge data center , Micro Data Center , Digital Twins , simulation software

Corporate News

Celtro – Making Medical Implants Battery-Free

The average battery in a pacemaker occupies approximately 60 to 80% of its space…

• 1 min read
designed with cadence

Digital Design

New Year, New (Smarter) You!

Gallop into the Lunar New Year with faster timing, quieter nets, and fewer headaches…

• 3 min read
training bytes , Digital Implementation , Innovus

Corporate News

Inside Cadence Digital Design and Signoff Excellence Event

If there was one unmistakable message from the Advancing Digital Design and Signoff…

• 4 min read
Cadence Connect , Digital Design and Signoff Excellence

Data Center

Data Center Digital Twins: How Simulation Improves Design and Performance

Data center digital twins are transforming data center design from assumption-based…

• 7 min read
stranded capacity , data center , Computational Fluid Dynamics , Cadence Reality Digital Twin Platform , data center digital twin

Analog/Custom Design

Virtuoso Studio: Layout Editor Productivity Enhancements Blog Series

In the complex world of custom IC layout, every click and keystroke counts towards…

• 2 min read
Virtuoso Studio , Custom IC Design

Data Center

Data Center Operations, DCIM, and Monitoring

In today’s digital world, data centers underpin cloud services, streaming, enterprise…

• 7 min read
data center , Data Center Operations , DCIM Software , Cadence Reality Digital Twin Platform , BMS

Computational Fluid Dynamics

Predicting High-Lift Aerodynamics of the Dornier 228 Using Fidelity CFD

The paper “Computational and Experimental Investigation of Dornier 228 Aerodynamic…

• 5 min read
RUAG , Computational Fluid Dynamics , Fidelity CFD , high-lift prediction , Aerodynamics

SoC and IP

The Memory Imperative for Next-Generation AI Accelerator SoCs

The tremendous growth in large language model (LLM) size corresponds with an equally…

• 4 min read
HBM , SoC , AI

Analog/Custom Design

Virtuoso Studio: Excellent XL - Next-Gen Layouts with Virtuoso Layout XL

The ‘Excellent XL’ blog series explores what makes Layout Suite XL so powerful for…

• 5 min read
Layout XL-compliance , Schematic Assistant , Virtuoso , Custom IC Design , Application Readiness Checker , IC23.1

SoC and IP

Accelerating Chiplet Interoperability

In the chiplet marketplace, the vision of a library of chiplets that can be mixed…

• 2 min read
chiplets , OCP FCSA , CSA , OCP , FCSA , Arm CSA , ARM

System, PCB, & Package Design 

A Journey Through 2025: PCB and Package Design Learning in Motion

2025 was a year of innovation and learning for PCB and Package Design, with 17 new…

• 6 min read
blended , digital badge , System Capture , Allegro X PCB Editor , OrCAD Capture , accelerated learning , Academic Learners , training , webinar , training bytes , GenAI , PCB design , ask , Celsius PowerDC , RAKs

Verification

Breaking Down UPLI: A Protocol-Level Perspective on UALink 200

In the evolving landscape of high-performance computing, particularly in AI and ML…

• 3 min read
UAL , protocol layer , AI Accelerator , UALink , UPLI , AI

Data Center

Choosing the Right Data Center Strategy: Colocation vs Hyperscale vs Enterprise

It is essential to understand how colocation capacity planning differs from hyperscale…

• 7 min read
Colocation Data Center , enterprise datacenter , data center , hyperscale data center , digital twin , Celsius Studio , Cadence Reality Digital Twin Platform

Corporate News

Pointcloud – Helping Machines View the World in 3D

For humans, understanding the world in three dimensions comes naturally. We can instantly…

• 1 min read
designed with cadence

Verification

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that…

• 5 min read
UAL , protocol layer , VIP , UALink , UPLI

SoC and IP

Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology

With the rapidly increasing connectivity demands driven by AI/ML and HPC/datacenter…

• 3 min read
ucie , Design IP , chiplets , d2d

Verification

Cadence VLAB at the Automotive Software Frontier

The VLAB team at Cadence is participating in the 11th Automotive Software Frontier…

• less than a min read
Automotive , vlab , virtual platform , embedded software , event
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