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IEDM: TSMC N3 Details
As you know from previous blog posts, I attended IEDM in San Francisco in December. There were two presentations about TSMC…
Malcolm Penn: “We Are Stoking Capacity Just When We Don’t Need It”
On Tuesday this week, Malcolm Penn of Future Horizons gave one of the three annual presentations on the outlook for the semiconductor…
Computational Fluid Dynamics (CFD)
On-Demand Webinar - End-to-end Design and Modeling of Turbo Compressors for Hydrogen Applications
Hydrogen fuel is considered one of the most promising means to achieve decarbonization and reach the world's ambitious CO2…
CS + Math
In most domains, a million is a large number. In EDA, a hundred billion is normal, and predictions are for trillion-transistor…
Sunday Brunch Video for 29th January 2023
Made at Steamers, Los Gatos (camera Carey)
Monday: Design Enablement of 2D/3D Thermal Analysis…
January 2023 Update: Automotive Security, Chiplets...and Roman Emperors!
Wow, it's already the last Friday in January, so time for one of my monthly update posts where I cover anything that doesn…
HPSC: RISC-V in Space
NASA needs a new computer. Being NASA, of course, this has an acronym, HPSC. Unusually for NASA, this has four letters, not…
Corporate and Culture
Computational Fluid Dynamics
System, PCB, & Package Design
The India Circuit
Cadence Academic Network
Made at Steamers, Los Gatos (camera Carey)
Monday: Design Enablement of 2D/3D Thermal Analysis and 3-Die Stack
Tuesday: IEDM: TSMC N3 Details
Wednesday: Technology and the American Trucking Industry
Wow, it's already the last Friday in January, so time for one of my monthly update posts where I cover anything that doesn't justify its own full post or which is an update to something I wrote about earlier.
I have writte...
Verification(Verification of System and Software)
Training Insights – Webinar –: Solve Tricky SVA Problems with Jasper Visualize and WaveEdit: Recording Now Available
Are you experienced in using SVA?
It’s been around for a long time, and it’s tempting to think there’s nothing new to learn.
Have you ever come across situations where SVA can’t solve what appears to be a simple problem?
Corporate and Culture
Mimi Is Creating a Sustainable Audio Experience
According to Mimi’s database of 2.25 million hearing tests, over 55% percent of the adult population have some form of hearing loss. In order to combat this growing global crisis, the Mimi team have created a flexible software kit to provide he...
Opra Turbines: Gas Dispersion Analysis and Explosion Protection of a Gas Turbine
"A good mesh is one of the fundamentals to run the CFD analysis successfully. Cadence's meshing suite significantly reduced our meshing time and improved the mesh quality resulting in better CFD simulations." OPRA Turbines International BV. Read about how they use Fidelity Automesh in their workflow, describing the particular case of designing a marine version of their OP16 gen-set for use onboard ships.
NASA needs a new computer. Being NASA, of course, this has an acronym, HPSC. Unusually for NASA, this has four letters, not three. Remember back in the Apollo program (assuming you were born) when we all knew what TLI, LEM, and all the rest stood for...
Technology and the American Trucking Industry
I have kept an eye on trucking over the last few years. Trucks are not technically cars, but from a semiconductor point of view, they are part of the automotive market segment. We're talking about big trucks here, not pickups or Amazon ...
System, PCB, & Package Design (System Analysis: EMI/EMC/ET, PCB)
BoardSurfers: Exploring the Dimensioning Environment
Dimensioning features specify the measurements of different design elements, such as the board outline, mounting holes, components, and so on. Adding dimensions to a PCB design is a crucial step in the design process for conveying the design intent ...
As you know from previous blog posts, I attended IEDM in San Francisco in December. There were two presentations about TSMC's N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the ...
Flex Ethernet (FlexE): Unlocking the Physical Bandwidth Constraints
Efficient and flexible use of bandwidth is the key to optimizing traffic flow for any communication channel, and so for Ethernet. FlexE (Flex Ethernet) is a standard developed by the Optical Internetworking Forum (OIF) that allows for efficient and flexible use of Ethernet bandwidth. It enables the aggregation of multiple different bandwidths, such as 100G, 50G, and 25G, into a single logical channel known as a FlexE…
Start Your Engines: ミックスシグナル・ビヘイビア・モデリングのレビューとコーチング
Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Engines! ブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。
Last Week at Fidelity CFD
While a large contingent of Fidelity CFD team members are at the AIAA SciTech Forum this week, let's take a look back at what happened here last week. This post's featured image is a blast from the past of flow through a valve. (Image created...
Design Enablement of 2D/3D Thermal Analysis and 3-Die Stack
At CadenceLIVE Europe back in November, one of the presentations was by Mohamed Naeim titled Design Enablement of 2D/3D Thermal Analysis and 3-Die Stack. Mohamed is officially a Cadence employee, but he's also a Cadence PhD resident at imec ...
5 Small Features for Easy Meshing in Fidelity Pointwise
The big powerful features such as unstructured quadrilateral surface meshing, unstructured hexahedral layer extrusion in the anisotropic tetrahedral extrusion (T-Rex) technique, and tetrahedral mesh clustering sources often overshadow the small yet formidable features in Fidelity Pointwise. This blog enlists the top five small features for easy meshing in Fidelity Pointwise.
Sunday Brunch Video for 22nd January 2023
Made at Castle Rock State Park (camera Carey)
Previous Monday: CES 2023 Trends
Monday: Martin Luther King Day (no post)
Tuesday: DesignCon 2023 Preview
Wednesday: Improving RISC-V Processor Quality with Verifica...
ST's Experience with Cadence Cerebrus
At CadenceLIVE Europe back in Thanksgiving week, one of the presentations was by Olivier Uliana of STMicroelectronics titled Cerebrus PPA Optimization on the Next-Generation High-End Microcontroller CPU Core. In case you've forgotten what Cadence...
AMD Is Designing Their EPYC Server Processors with the Dynamic Duo
AMD are known for creating some of the world’s most advanced processors. AMD’s EPYC server processors represent a big step forward for high-performance computing, cloud, and enterprise workloads. When it comes to the emulation stage of th...
On Tuesday this week, Malcolm Penn of Future Horizons gave one of the three annual presentations on the outlook for the semiconductor industry. I last wrote about a presentation by Malcolm what feels like "recently" but was, in fact, in 2021. That po...
Analog/Custom Design (Analog/Custom design)
Running Post-Layout Mixed-Signal Simulations with a More Complex Configuration
Cadence®︎ Spectre®︎ With the DSPF-in-the-middle feature, designers can easily set up complex configurations in the Hierarchy Editor (HED) and run a post-layout mixed-signal simulation with just a few clicks. View this blog to know more.
SoC Integration (IP for SoC design)
FMEDA-driven SoC Design of Safety-Critical Semiconductors
The growing complexity of electronics in modern cars is driving the automotive industry to adopt even more stringent processes throughout the supply chain. The lack of tools and methodologies to enforce a traceable safety lifecycle and exchange of safety-relevant information has created the need for an integrated design flow that addresses the safety requirements…
What Makes a Next-Generation Debug Solution?
For the past few decades, design and verification technology have made great progress. More sophisticated designs are verified with faster simulation and emulation. However, the debug is pretty much the same as 20 years ago. The most bothersome thing for engineers is why there’s no way to automate the process. What engineers typically do is, check the log file and see if there are any errors from verification tools such…
Spectre Tech Tips: Dynamically Changing Spectre X Solver Settings
Spectre APS supports dynamically changing errpreset or reltol during a transient simulation. This feature is used by advanced Spectre users to optimize simulation performance when different time windows of the simulation have different accuracy requirements. The use model for this feature is the following:
The errpreset parameter is not available in…
Improve Regression Throughput and Find Bugs at Pace
Scaling chip size and increasing functionality over SoCs has increased complexity and verification time. Verification teams are concerned about the bugs that may have slipped to silicon earlier and their discovery rate. Moreover, completing the verification and achieving the desired coverage is tricky. It looks arduous to complete the verification and meet the time constraints, especially when the specifications change…
Improving RISC-V Processor Quality with Verification Standards and Advanced Methodologies
At the RISC-V Summit in December, there were presentations halfway between a keynote and a technical session. known as RISC-V Spotlights. These were presented to the entire group of attendees but were not blessed with the keynote title. Maybe this is...
Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL Interfaces
2023 is here, and technology trends around Compute Express Link (CXL) and the next generation of AMBA protocols (CHI-E/F) are getting more traction. The biggest challenge of today is the complexity of handling enormous data flow owning to AI, ML, and deep learning applications. To keep up with the pace, new generation interfaces introduce specialized semantics catering to memory disaggregation, cache consistency, techniques…