• Home
  • :
  • Community

Cadence Blogs

Read our latest blog posts and find in-depth technical information in our forums

Go To Forums
Cadence Members

Login with a Cadence account.

LOG IN

Not a member yet?

Register | Membership benefits
  • All Blog Categories
  • Breakfast Bytes
  • Cadence Academic Network
  • Cadence Support
  • Computational Fluid Dynamics
  • CFD(数値流体力学)
  • 中文技术专区
  • Custom IC Design
  • カスタムIC/ミックスシグナル
  • 定制IC芯片设计
  • Digital Implementation
  • Functional Verification
  • IC Packaging and SiP Design
  • In-Design Analysis
    • In-Design Analysis
    • Electromagnetic Analysis
    • Thermal Analysis
    • Signal and Power Integrity Analysis
    • RF/Microwave Design and Analysis
  • Life at Cadence
  • Mixed-Signal Design
  • PCB Design
  • PCB設計/ICパッケージ設計
  • PCB、IC封装:设计与仿真分析
  • PCB解析/ICパッケージ解析
  • RF Design
  • RF /マイクロ波設計
  • Signal and Power Integrity (PCB/IC Packaging)
  • Silicon Signoff
  • Solutions
  • Spotlight Taiwan
  • System Design and Verification
  • Tensilica and Design IP
  • The India Circuit
  • Whiteboard Wednesdays
  • Archive
    • Cadence on the Beat
    • Industry Insights
    • Logic Design
    • Low Power
    • The Design Chronicles
  • Ashish Patni
    Virtuosity: Custom IC Design Flow/Methodology – Circuit Layout
    By Ashish Patni | 19 May 2022
    Read this blog for an overview to the Circuit Layout design stage in Custom IC Design methodology and the key design steps which can help you achieve this.
    0 Comments
    Tags:
    Virtuoso Schematic Editor | Virtuoso Space-based Router | Virtuoso Placer | Layout Suite | Layout | ICADVM20.1 | Custom IC Design | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | IC6.1.8 | Virtuoso Layout Suite XL
  • Paul McLellan
    Photonics Keynote: Transitioning from Electrical to Optical I/O
    By Paul McLellan | 19 May 2022
    At last year's Photonics Summit, actually held earlier this year due to technical issues when the videos were meant to go live, the keynote was given by James Jaussi, Senior Principal Engineer and Director of the PHY Research Lab in Intel La...
    0 Comments
    Tags:
    Intel | Photonics Summit | silicon photonics | photonics
  • Custom IC Japan
    Spectre Tech Tips: Spectre Strobe機能の使用
    By Custom IC Japan | 18 May 2022
    Spectre®回路シミュレータをご利用のお客様で、SpectreのStrobe機能で対応可能な用途にmaxstep機能を使用しているケースが時々見受けられます。そこでこのブログでは、SpectreのStrobe機能の使い方を中心に説明します。 Virtuoso® Visualization and Analysis XL (ViVA XL)やOCEANなどのツールで波形のポストプロセスを行う目的でSpectreシミュレーションを実行し、このポストプロセスを等間隔で行う...
    0 Comments
    Tags:
    Fast Fourier Transform | ADE Explorer | strobe | Spectre Circuit Simulator | Virtuoso Analog Design Environment | Virtuoso IC6.1.8 | japanese blog | ADE Assembler
  • Anton Klotz
    Organic Printed Electronics PDK Education Kit Available Now
    By Anton Klotz | 18 May 2022
    The Virtuoso Education Kit has just been released and now there is already a new kit available: The Organic Printed Electronics PDK Education Kit ! This kit also uses Virtuoso as the main Cadence tool, allowing schematic creation, layouting, and paras...
    0 Comments
    Tags:
    Cadence Academic Networ | Education Kits | Virtuoso | Organic Printed Electronics
  • Lunch & Learn and Women in Engineering at the ASME Turbo Expo 2022
    By Veena Parthan | 18 May 2022
    Cadence is looking forward to meeting with you at the 'Lunch and Learn' and 'Women in Engineering' sessions at ASME Turbomachinery Expo 2022. Seats are limited! Register today to ensure your spot.
    0 Comments
    Tags:
    CFD | Lunch and Learn | turbomachinery | ASME Turbo Expo | Pointwise | Turbo Thursday | Cadence Fidelity | women in engineering | engineering | simulation software | NUMECA | Women in CFD
  • Paul McLellan
    Arm SystemReady Compliance Using Emulation
    By Paul McLellan | 18 May 2022
    Yesterday in my post Cadence and Arm I wrote about how Cadence has worked with Arm over the last decade or more. Well, it is Arm again today since there is an Arm event at which Cadence is giving one of the presentations. Today is the second day...
    0 Comments
    Tags:
    AVIP | Perspec | systemready | Palladium | Emulation | ARM
  • Virtuoso Release Team
    Virtuoso ICADVM20.1 ISR25 and IC6.1.8 ISR25 Now Available
    By Virtuoso Release Team | 18 May 2022
    The ICADVM20.1 ISR25 and IC6.1.8 ISR25 production releases are now available for download.
    0 Comments
    Tags:
    Analog Design Environment | Cadence blogs | Virtuoso RF Solution | Virtuoso Visualization and Analysis XL | Virtuoso RF | Layout EXL | Virtuoso Analog Design Environment | Virtuoso | ICADVM20.1 | IC Release Blog | Virtuoso ADE Explorer | Virtuoso Layout Suite | Custom IC | Virtuoso ADE Assembler | IC6.1.8
  • Supriya Srivastava
    ASCENT: Training Insights: Get Rid of Design Errors in Allegro System Capture
    By Supriya Srivastava | 18 May 2022
    With thousands of components connected across a multi-layered board, anticipating the complexity of your layout design at the logic design stage can be quite a challenge. For example, how to ensure that the logical design you are trying to create fun...
    0 Comments
    Tags:
    System Capture | 17.4 | Design Rule Checker | 17.4-2019 | Training Insights | Allegro System Capture | ASCENT | Schematic
  • Parula
    Virtuoso Meets Maxwell: Improving Manufacturability and Yield
    By Parula | 17 May 2022
    This blog is to announce the official release of the Fillet capability. The Fillet capability is another remarkable addition to our existing Virtuoso RF features portfolio. For analog and high-speed circuits, or areas of a design where shock and vibration to the design might disrupt connections, adding...
    0 Comments
    Tags:
    fillet | metal density | Virtuoso Meets Maxwell | Virtuoso RF Solution | T connections | Improving Manufacturability and Yield | Virtuoso RF | tapered traces
  • Paul McLellan
    Cadence and Arm
    By Paul McLellan | 17 May 2022
    I've been working with Arm for longer than Cadence has. In fact, I was working with Arm before it was Arm, back when the Arm 1 was a processor developed by Acorn Computers (the A in Arm originally stood for Acorn). I described my early involveme...
    0 Comments
    Tags:
    vlsi technology | cerebrus | Innovus | ARM
  • Veena Parthan
    Less than a Minute to Water-tight Geometry Using Fidelity CFD AutoSeal
    By Veena Parthan | 16 May 2022
    Cadence Fidelity CFD offers AutoSeal technology, a geometry clean-up tool for faster results for multiple design tests, reducing the time to meshing towards an efficient design process.
    0 Comments
    Tags:
    CFD | AutoSeal | geometry cleanup | Pointwise | CAD preparation | Fidelity CFD | engineering | simulation software | NUMECA | preprocessing
  • Sherry Hess
    Frequency Matters Podcast: System Analysis Solutions
    By Sherry Hess | 16 May 2022
    By Sherry Hess Recently I posted a blog on LinkedIn called "High Tech Everything" and it caught the attention of Microwave Journal.  As such, it have spawn a similar podcast on how Cadence is expanding into multiple verticals with system analysis solutions...
    0 Comments
  • Paul McLellan
    The 2022 Kaufman Dinner
    By Paul McLellan | 16 May 2022
    On May 12th, it was the Kaufman Award Ceremony and Banquet at which Cadence's CEO Anirudh Devgan was awarded the 2021 Phil Kaufman Award. Yes, I know it is 2022. Normally the award dinner is held late in the year, but for Covid-reasons, it was postpo...
    0 Comments
    Tags:
    kaufman dinner | Kaufman Award | Anirudh Devgan | kaufman award 2021
  • Paul McLellan
    Sunday Brunch Video for 15th May 2022
    By Paul McLellan | 15 May 2022
    https://youtu.be/F-dN8wy-iNc Made at Steve Brown's "moving to San Diego party" (camera Larry Lapides) Monday: no post Tuesday: TechInsights: Foundation for the Future Wednesday: Open RAN Phase 2 Thursday: What Is High-NA EUV? Friday: N...
    0 Comments
    Tags:
    sunday brunch
  • Kira Jones
    Searching on Cadence Support Is Now Even Easier!
    By Kira Jones | 13 May 2022
    The Cadence Learning and Support Portal is useful to academia in many ways: Online Training, Rapid Adoption Kits (RAKs), Generic Process Design Kits (GPDKs), troubleshooting database, and so much more. But with so many benefits, it is helpful to be a...
    0 Comments
    Tags:
    Cadence Academic Network | Cadence Online Support | online training | university program
  • Paul McLellan
    New Book: Hyperscale Computing Trends 2022
    By Paul McLellan | 13 May 2022
    Cadence has a new book out. Written by Frank Schirrmeister and myself, it is called Hyperscale Computing Trends: 2022 Outlook. In some ways, it is similar to the Year of Breakfasts books that I have done each year for the last few years, a sort of be...
    0 Comments
    Tags:
    hyperscaler | Schirrmeister | McLellan | book
  • Sangeeta Soni
    Demystifying CXL.cache
    By Sangeeta Soni | 13 May 2022
    If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you might have heard Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Of course, CXL buzz is for real and is well resonating...
    0 Comments
    Tags:
    CXL | Functional Verification | pcie 5 | VIP | PCIExpress | coherency | verification
  • Sanjiv Bhatia
    IC Packagers: Three Reasons for Allegro Package Designer Plus Users to Move to OrCAD/Allegro 17.4 (SPB174) - HotFix028 Release
    By Sanjiv Bhatia | 13 May 2022
    The HotFix 028 of our 17.4-2019 release was rolled out at the end of March and is now available for download and installation. The release brings critical bug fixes, product enhancements, and new features. Let’s talk about some of the exciting...
    0 Comments
    Tags:
    IC Packaging | APD | IC Packaging & SiP design | IC Packagers | Allegro Package Designer | 17.4-2019 | 17.4 QIR4
  • Paul McLellan
    What Is High-NA EUV?
    By Paul McLellan | 12 May 2022
    I'm sure you know that the lowest levels of ICs fabricated at the most advanced nodes, basically anything at 5nm and below, use EUV lithography (extreme ultraviolet). You probably also know that only one company in the world, ASML in the Netherla...
    0 Comments
    Tags:
    asml | imec | SPIE | high-na euv | EUV
  • CadenceLIVE Silicon Valley 2022 - CFD Track: Seven Reasons to Attend
    By AnneMarie CFD | 12 May 2022
    On June 8th and 9th, it is CadenceLIVE Americas. It is planned to be in-person at the Santa Clara Convention Center in Silicon Valley and that is already your first important reason to join us! We are finally getting back to face-to-face networking, enjoying wonderful food and drinks, and seizing invaluable...
    0 Comments
    Tags:
    Computational Fluid Dynamics | fluid dynamics | CFD events | CFD Applications | simulation software
  • Paul McLellan
    Open RAN Phase 2
    By Paul McLellan | 11 May 2022
    I first wrote about Open RAN in my post Fourth 4G Network Goes Live in Japan . Open RAN is a program driven by a group of European operators to build specifications for common architecture instead of getting "locked into" the closed architec...
    0 Comments
    Tags:
    oran | mobile | o-ran alliance | openran
  • Vinod Khera
    Renesas Leverages Palladium + System VIP Solution for System Verification and Performance Optimization
    By Vinod Khera | 10 May 2022
    Verifying bus performance by analyzing bandwidth and latency over time in chips is tricky. Renesas in collaboration with Cadence used a comprehensive emulation package and designed a new efficient bus performance verification scheme that helped them to witness a stellar performance with 160x speedup...
    0 Comments
  • Neha Joshi
    Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With Low Power During Design Synthesis; How?
    By Neha Joshi | 10 May 2022
    Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various techniques. We understand that it is not always easy to estimate power, but Cadence offers a solution...
    0 Comments
    Tags:
    Low Power | Genus | Digital Implementation | Synthesis | power optimization
  • Sigrity
    Clarity 3D Solver 2022版本闪亮登场
    By Sigrity | 10 May 2022
    最新的电磁设计同步分析功能有助于提高 IC、IC 封装和高性能 PCB 设计的速度 美国加州圣何塞(DesignCon)—楷登电子(Cadence Design Systems, Inc.)在近期结束的 DesignCon 2022 展会上发布了用于 IC、IC 封装和高性能 PCB 设计电磁 (EM) 设计中同步分析的 Cadence® Clarity 3D Solver 最新版本。该版本的新功能和工作流程包括: 新的分布式网格划分功能,可提供至少 10 倍性...
    0 Comments
    Tags:
    网格划分 | Chinese blog | ml | 机器学习 | EM分析 | PCB设计 | 电磁分析 | 设计同步分析 | EM | Clarity 3D Solver | 人工智能 | 刚柔结合 | AI | clarity
  • Paul McLellan
    TechInsights: Foundation for the Future
    By Paul McLellan | 10 May 2022
    The second day of the Linley Spring Processor Conference opened with a keynote by Jason Abt, the Chief Technology Officer of TechInsights, titled Foundations for the Future. There's a good chance you don't know who TechInsights is. Well, firs...
    0 Comments
    Tags:
    linley processor conference | Linley | reverse engineering | techinsights
>