Palladium Z1, an Enterprise Server Farm in a Rack

If you put together your dream emulation system, it would have:

• Infinite throughput
• Scalability from small blocks to the largest SoC your company will work on
• Very low total cost of ownership (small physical size, consumes little power, cost amortizable over many use models, fire-and-forget IT support)
• Accessible to all engineers simultaneously
• Available resources always usable (jobs do not block each other unless resources are exhausted)
• Access to any target you want, with no need for manual re-cabling
• Fast flexible design compilation with no need to alter source code
• Everything observable for free for optimal debugging
• Links to other aspects of verification, such as virtual platforms and power measurement
• And a pony

Today, Cadence announced the latest enterprise emulation platform, the Palladium Z1. So how close does it get to your dream?

• Up to 5X greater emulation throughput compared to other emulators, 2.5X better than the prior generation Palladium XP II platform
• Scalability from small blocks up to 9.2 billion gates (from 4M to 576M gates per rack)
• Rack-based form factor giving best-in-class total cost of ownership (92% smaller footprint, 44% better power density than the prior generation), high redundancy for high availability
• Up to 2304 simultaneous users
• Jobs are virtualized and can be relocated and reshaped dynamically to free up space, no need to wait for existing jobs to terminate and flush
• Up to 24 targets (USB, PCIe, video, Ethernet, custom...) per cluster with no physical re-cabling required
• Compilation speed doubled, source code unchanged from Incisive RTL simulation (and other tools)
• High trace depth, virtual verification machine allows for offline debug with no re-running needed
• Links to Incisive VSP, Joules, Indago debug, Perspec, vManager, and VIP solutions
• Pony not included

Historically, emulation has always been fast. Just how fast has depended on what semiconductor technology was available in that era. But emulation used to be weaker at getting the design into the emulator and debugging it there. In fact, in the early days of emulation, it would take several months to get a design up and running in an emulation system. Emulation, like a baseball player, circles around four bases:

• Build: Compile databases for different workloads. Need high compile speed, high automation, ability to use available workstations
• Allocate: Allocate as many workloads as possible. Need high number of simultaneous jobs, relocation, interface to job schedulers
• Run: Speed, speed, interface solutions. And speed.
• Debug: For both pre-silicon and post-silicon bugs. Needs high trace depth, dynamic trigger, software traces

The Palladium Z1 platform does well on each of the four bases. It varies a bit but basically it is about twice as fast as the previous generation, Palladium XP, and two to five times as fast as other emulation systems.

Each of the four bases on the throughput loop are important in their own right, but the real measure is how fast the entire loop can be circled. Because it isn't just circled once. The loop is repeated many, many times over the course of a whole SoC project. The four-base loop is, however, not always the same. Sometimes it is being used for RTL debug, at other times for software debug, or power analysis, or architectural analysis. Each of these use cases requires a slightly different set of capabilities. In fact there are at least 22 use-case models.

Perhaps surprisingly, there is a lot of evidence that semiconductor companies do not spend enough on tooling for verification and software validation. They spend 80% of their resources on software development and verification, and only 20% on design and IP qualification, actual chip design. But they spend 80% of their tooling budget on tools for chip design and only 20% for verification and software. Some of this is that software development uses open-source tools that have no (or small) cost, but mostly it is that there is a huge automation gap. Software and verification engineers are not capitalized to the same level as design engineers. With engineering salaries as high as they are, undercapitalizing them is not the best tradeoff.

There is no getting away from the fact that emulators are not cheap. However, I have seen keynotes at DVCon showing that an emulation cycle is the cheapest verification vector you can buy...obviously so long as you want a lot of them. On a panel session at the recent Jasper User Group (JUG) meeting here at Cadence, Ali Habbibi from Qualcomm said that they do most of their simulation on a 100,000 core server farm. That is capacity for a lot of vectors too, and the reason that is attractive is not the cost (100,000 core server farms are not cheap) but the historic difficulty of using emulation with large numbers of users, huge numbers of jobs, wildly varying job sizes, and the other realities of a chip design in progress. Of course, simulation is not going away, verification is all about the combination of technologies, but emulation is one of those core technologies, as is formal (non-dynamic), and even high-level synthesis (HLS), which allows C-level verification.

The Palladium Z1 platform is the first datacenter-ready emulation system. I don't want to push the analogy too far, but it is a huge server farm in a rack, with much higher speed. The small simulations and the huge simulations can both be run. At the same time. And debugged. With all your interfaces to the external world. Untouched by human hand. Virtualization of emulation has finally arrived.