IC designers and foundries typically have different objectives. IC designers want to achieve the greatest performance while performing the least amount of guard-banding. Schedules and predictability are also paramount concerns for designers. IC Foundries want designs to adhere to design for manufacturing (DFM) and design for yield (DFY) rules and recommendations for their advanced process nodes to achieve the highest yield. A common misconception is that these IC design and manufacturing objectives are always in opposition. However, with the Cadence Space-based Router (also available as the Virtuoso Layout Suite XL/GXL integrated Space-based Router) and Cadence Chip Optimizer, IC designers can achieve both their custom IC design and manufacturing objectives.
Fewer products with higher volumes at advanced process nodes put more economic pressure on first-time success. Therefore a concurrent convergent solution to meet both design and manufacturing objectives is required and is available.
Typically design and DFM implementation tools are discussed and advertised separately with different solution objectives. Additionally, conventional custom IC implementation tools create an oversimplified model of the interconnect and associated advanced process rules. The Cadence Space-based Router and Cadence Chip Optimizer use a patented three-dimensional, space-based approach to model and analyze true shapes and intervening physical spaces. It allows shapes and spaces to be positioned in the exact configuration and location required to correct sub-wavelength manufacturing effects. This capability affords greater precision and flexibility when optimizing interconnects using tiered foundry and recommended design and manufacturing constraints.
Space Tile Geometry Engine
3D Net Tube Data Model
Dynamic Incremental Extraction and Timing
The Cadence Space-based Router is a silicon validated, three-dimensional, hierarchical, grid-less, space-based, full-chip and block routing convergence system for advanced mixed-signal, analog, and custom digital designs at 65nm and below. Its constraint-driven, interactive/ automatic physical design interconnect environment offers a streamlined flow, from constraint definition and routing through analysis, verification and refinement. The router models advanced processes and design constraints, providing maximum control and exceptional results upfront in the design process for high-performance chips. It also features specialty mixed-signal and analog routing (e.g. diff pair, shield, bus, symmetry, length control, etc.), and incremental in-core electrical timing and R/C extraction analysis.
The Cadence Chip Optimizer provides unique DFM / DFY inter-connect optimization capabilities to insure advanced process node DRC correctness, improved yield (Wires and Vias), improved manufacturability (Litho, CMP, CAA) and preservation of design intent and electrical constraints during custom and digital IC design. These capabilities enable optimization of the design interconnect based on both the design and manufacturing objectives. It can be used after conventional place and route in Cadence or 3rd party digital design flows or after custom A / MS flows improving timing, yield, manufacturing and performance with features to address late design ECO’s.
Online demos are available for viewing using these links Cadence Space-based Router and Cadence Chip Optimizer
In subsequent blogs on this topic I'll talk about some specific customer success stories where concurrent design and manufacturing convergence were achieved and transistor device level solutions found in the IC 6.1 Virtuoso Layout Suite environment integrated version of the Space-based Router.