Custom IC Design Blogs

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.

Concurrent Layout Editing enables more than one designer to work in a hierarchy at the same time. Check out this blog to know more.

The ICADVM20.1 ISR27 and IC6.1.8 ISR27 production releases are now available for download.

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this...

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides support to the Voltus-XFi Custom Power Integrity Solution.

The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for download.

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In this post, we will learn about the most important parameters for the analog simulators that affect the accuracy of the simulation results. We will also understand how each parameter limits the accuracy of the measurements for the DC and transient analyses.

I have been involved in the Virtuoso RF Solution for the last four years. Most of the customers I work with have a SiP package already in progress. They often ask "How do I get my SiP design into Virtuoso RF Solution?" I am excited about new functionality in the latest ICADVM20.1 ISR25 release. It is a new GUI under the Tools menu called Enablement.

Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.

The three-day Virtuoso Digital Implementation online training course can get you up to speed on the product. If you pass the exam for the course, you will receive a badge which you can display on LinkedIn.

Two years of knowledge booster blogs series, what happened during this time, important information and developments at one glance. There are more blogs to come in this series.

Simulation performance is a critical factor in the time required for chip design, verification, and sign-off. The more efficient the simulations are, the less resources and turnaround time are required for each tapeout. Increasing the awareness among designers on how to optimize the simulation will show a big increase in the design team productivity and efficient use of the design resources from license usage to the...

Check out this blog to see how you can debug shorts using Interactive Shorts Locator (ISL)

Read this blog for an overview to the Circuit Layout design stage in Custom IC Design methodology and the key design steps which can help you achieve this.

This blog is to announce the official release of the Fillet capability. The Fillet capability is another remarkable addition to our existing Virtuoso RF features portfolio. For analog and high-speed circuits, or areas of a design where shock and vibration to the design might disrupt connections, adding fillets to your design is probably the solution to improve yield and manufacturability.

From time to time, we observe Spectre customers using the maxstep feature for applications that can be better addressed with the Spectre strobe feature. Therefore, in this blog, we focus on explaining the usage of the Spectre strobe feature.

We are going to host a webinar on Virtuoso Layout Pro Training in the upcoming month. Check out this blog to know all the details.

Read this blog for an introduction to the Custom IC Design methodology and the key design challenges that the methodology can help you address.

DSPF files are an integral part of post-layout simulations. This blog introduces you to the commands and utilities provided by the Spectre circuit simulator to help you run simulations with DSPF netlists.

The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for download.

Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow the P&R routing style and are readable in Innovus.

Virtuoso Electromagnetic Solver integration allows layered parasitic extraction and electromagnetic simulation with Cadence Quantus Extraction Solution and Cadence EMX Planar 3D Solver. The seamless integration automatically ensures that parasitic effects are neither missed nor double-counted during post-layout circuit simulation. But what am I doing with custom passive devices? How can I include the parasitics of the...