Custom IC Design Blogs

This blog shows how to efficiently use the Virtuoso ADE Assembler and Virtuoso ADE Explorer by using the available assistants in the Assembler and setting up a Monte Carlo run in the ADE Explorer.

Understanding the thermal performance of integrated circuits has been essential to avoid the overheating that can cause circuit malfunctions.  With greater integration, the power dissipation in integrated circuits is becoming increasingly impor...

Before the creation of die and package layout can begin, logical connectivity between these two fabrics need to be established. Based on the number of input or output and power or ground connections needed, the physical size and pin arrangement of the IC and package can start.

Cadence Learning and Support portal has introduced a new one-stop learning resource to guide you about different features of the Virtuoso Layout Suite products. Click here to know more.

In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz using the Cadence Virtuoso multi-technology framework.

Gone are the days of exporting results from multiple interactive runs and combining them into Excel spreadsheets for analysis. The new Reference Histories and Merge Histories flows address all these concerns. Click here to know more.

In circuit design, wrong connectivity may cause undesired leakage paths that may result in current hotspots. These current hotspots can be quickly identified with Spectre’s dynamic design checks. This blog describes how to use the Spectre design checks to identify the root cause of leakage path current hotspots.

Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis XL to analyze waveform data. Click here to know more.

The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for download.

Do you work with RF designs that contain both active and passive devices? Have you been running electromagnetic simulations for those designs by making a copy of the design and removing active devices? So you have not explored the advanced full-cellview extraction feature yet. Read this blog to know more..

In this blog. we would like to let you know the information on how to achieve complete full-chip DRC signoff on advanced-node designs and efficiently run multiple DRC signoff iterations.

Hi all, this is my first blog for the Virtuoso Meets Maxwell series. It builds on the Virtuoso Meets Maxwell 2021 introduction blog. Today I get to discuss one of my favorite topics, electromagnetic (EM) analysis of RFICs using Cadence EMX Planar 3D Solver.

Spectre XDP-HB was released in the SPECTRE 20.1 base release as part of the new Spectre X-RF simulation technology. Spectre XDP-HB uses a highly distributed multi-machine multi-core simulation technology to perform HB and HB small-signal analyses. In this blog, we introduce the Spectre XDP-HB technology.

Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.

In many ways 2020 was an exceptional year with extraordinary challenges for all of us. Despite the unusual circumstances of a global pandemic, it was an exciting year with lot of product innovation that lies behind. To start with the Virtuoso Meets Maxwell series in 2021, let’s take a moment to look back at what we have achieved since the inception of the Virtuoso RF Solution.

You can now use the Performance Diagnostic tool in the Virtuoso custom IC design platform to diagnose issues that might be causing your system to slowdown or freeze. Click here to know more.

Continuing our momentum with the Knowledge Booster blogs in the year 2021 , this blog informs you how to overcome DC Convergence issues and errors for a Spectre Simulation by modifying associated parameters.

The ICADVM20.1 ISR16 and IC6.1.8 ISR16 production releases are now available for download.

In the Spectre 20.1 base release at the end of September 2020, we released Spectre X-RF. The Spectre X-RF technology integrates the Spectre X engine into Spectre’s RF analyses. In this blog, we introduce the Spectre X-RF technology.

Have you missed out on any of the In the Line of Veri-Fire blogs? Here's your chance to fix it...

Do you want to know how discovering the path of least resistance for the devices of your design much ahead of your power planning can make your life easier? Then go ahead and read the blog.

The Spectre X distributed simulation is an extension to the multithreaded simulation where cores from different machines are used. The Spectre X distributed simulation provides access to more cores, thus increasing the performance and capacity and providing more value for large designs.

Fast growing markets like 5G, automotive, and IoT are driving the development of advanced semiconductor technologies and silicon-integrated circuits. In particular, the high cutoff frequency of advanced CMOS and Silicon-Germanium (SiGe) bipolar devices allow the integration of millimeter-wave circuits with good high-frequency performance and high integration level at moderate mask costs.

The Allegro Package Designer product line offers everything needed to take an IC package from idea to manufactured part, and this is where the journey takes us today. It is available from your Virtuoso environment as Virtuoso MultiTech Framework.

If you have been following the Conserve Power blog series, you will probably have an idea of what next I am going to talk about. Yes, we have now reached the finale, the last and the most intriguing piece in the entire story. It is the formal verification and sign-off of the IP to make it ready to be integrated into an SoC.