Custom IC Design Blogs

This blog shows how Quantus Geometry Viewer (Quview) can be used to view various geometries like 3d views of an area generated by Quantus for debugging purposes. In addition, it shows the Connectivity checker which is is a netlist comparison utility to check the connectivity of the Quantus output netlist against the incoming LVS netlist data.

Read through this blog to know more about the usability enhancements made to the graph summary label in Virtuoso Visualization and Analysis XL.

Starting with ICADVM20.1 ISR20, you can write Design Intent notes in languages that use non-Latin character sets, for example, Mandarin Chinese, Japanese, and Hindi.

The ICADVM20.1 ISR21 and IC6.1.8 ISR21 production releases are now available for download.

This blog shows how you can easily navigate through tabbed Training byte channels and how you can discover many new tutorial videos around different topics in multiple tabs.

This Blog shows how the Virtuoso Schematic Editor tool provides numerous capabilities to facilitate fast and easy design entry. The main key benefit of speeding the common design entry tasks by 5x. It also mentions about product family providing a flexible set of product performance levels, such as Virtuoso Schematic Editor L and Virtuoso Schematic Editor XL, to best suit your design flow needs.

Paying attention to how you mesh your EM structures is as important as quality port definitions. The density of your mesh plays a big role in the accuracy/performance tradeoff that you make in the EM simulations. EMX Planar 3D Solver provides several controls to define mesh density in conductors and vias, and by default, uses techniques like regularity in structures to accelerate the meshing operation. And once your mesh...

As a design gets bigger, simulation generates big data. As data gets bigger, so does the demand to post-process and to efficiently save big data on disk. This blog describes how Spectre supports SQLite for an efficient management of big data.

This Blog shows how the Virtuoso Module Generators provide a way to generate multiple Pcell instances into a complex, highly matched, structured array and how you can control the routing style and generate internal routing geometry. In addition, you get an insight into Floorplanner that consists of automatic and interactive floorplanning tools and technologies that help the mixed-signal designers to develop a layout from...

The ICADVM20.1 ISR20 and IC6.1.8 ISR20 production releases are now available for download.

The SPECTRE 21.1 release is now available for download at Cadence Downloads.

A guest blog to let you know about Cadence’s recent ventures into the world of Computational Fluid Dynamics.

Die export has evolved and it’s time to introduce the new look and feel of the GUI alongside the new features added to bring an abstract view to the next level. The GUI has been redesigned to offer improved usability that matches the evolving use model. The new tab-based GUI has also been made scalable to facilitate the inclusion of further options in the future.

Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise and fall times. In this blog, we'll discuss the high impedance node checks available in Spectre and when to use each check.

We've been busy improving the usability of the Analog Design Environment products Virtuoso ADE Assembler and Virtuoso ADE Explorer over the recent releases. Click here to check out some of these usability updates that have been added between IC6.1.8/ICADVM20.1 ISR13 and ISR18 in this blog.

Details on a dedicated tab "Resources" in Job Policy form, which helps to do resource estimation while firing jobs in distributed farms like LSF, SGE, etc

The ICADVM20.1 ISR19 and IC6.1.8 ISR19 production releases are now available for download.

Virtuoso RF Solution is known for its extensive problem-solving capability that touches many product lines of the Virtuoso, AWR, and Allegro platforms. The Virtuoso RF Solution product page on the Cadence Learning and Support portal serves as a one-stop shop to showcase all the features on offer, the various flows in the overall solution, and related collateral for different modes of learning.

The new Large-Scale Cloud Simulation (LSCS) job control mode is highly scalable and can handle thousands of netlisting and simulation jobs in parallel. This job control mode supports all available job distribution methods in Virtuoso ADE Explorer and Virtuoso ADE Assembler. LSCS is an enabler for cloud-based simulation jobs. Read more...

This blog describes the behavioral modeling aspects of Verilog-AMS language that helps you to create and use modules for mixed-signal verification.

SPECTRE 19.1 ISR18, the last ISR of the SPECTRE 19.1 ISR release, was released on May 31st, 2021. This means that if you are still using the SPECTRE 19.1 release, you will not have access to any new features and enhancements made in Spectre. Read this blog to know more on how you can get the latest features and enhancements related to Spectre.

One of the strengths of the Virtuoso RF solution is the ability to handle connectivity across multiple fabrics. We have recently extended some the IC tools you already know and have used. They now comprehend connectivity across a multi-fabric system. You can trace a physical net from the package into the ICs that it hosts, and use connectivity checking to ensure your system layout’s nets match your schematic.

Read on to know the usefulness of the .simrc file and how and when it is picked by Virtuoso for netlist customization.

You can use Virtuoso keyboard shortcuts called bindkeys in Virtuoso Layout Suite to perform certain tasks. Check out this blog to see how you can download a printable document for bindkeys used in different Virtuoso Layout applications.

Fast and accurate electromagnetic simulation is becoming critical in a growing number of applications, and defining ports correctly is one of the most important things to get right to ensure accuracy. In this blog I will share some insights on defining ports for the EMX Solver.