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Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct

By NamrataM | 14 Feb 2019

Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster...

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electromigration | ICADV12.3 | ICADVM18.1 | EM/IR | Layout Suite | IC6.1.7 | EM | electrically-aware design | IR drop | IC6.1.8
Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design

By Hiro Ishikawa | 7 Feb 2019

How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.

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Analog Design Environment | Virtuoso New Design Platform | Physical placement and layout | Advanced Node | Virtuoso | Custom IC Design
Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!

By Rashmi G | 7 Feb 2019

Cutting-edge innovation … Top-down planning … Reliable and formalized verification … Scalable performance ! These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso ® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification...

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verifier | PVT | ICADVM18.1 | custom/analog | Formalized Verification | Analog Simulation | ADE | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | space | Custom IC Design | ADE Verifier | IC6.1.8 | ADE Assembler | verification
Virtuosity: Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

By Virtuoso Release Team | 6 Feb 2019

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download.

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Analog Design Environment | ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | ADE | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Virtuoso: The Next Overture | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

By Yagya Mishra | 31 Jan 2019

An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This...

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verifier | PVT | coverage | Analog Coverage | Analog Simulation | Virtuoso Analog Design Environment | space | Custom IC Design | Assembler | verification
Virtuosity: Introducing the Pin Tool

By Priya Sriram | 28 Jan 2019

The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the various menus in the Pin Tool. The tool includes several new options that let you perform a wide range of pin-related tasks.

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Spectre Tech Tips: Optimizing Spectre APS Performance

By Stefan Wuensche | 24 Jan 2019

This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions for typical setup problems causing performance issues, and delivers tips on advanced methods for optimizing simulation performance.

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spectre aps | Circuit simulation | ADE Explorer | simulation performance | Simulation Accuracy | Spectre XPS MS | ADE | Spectre Tech Tips | Spectre
Virtuosity: What's New in Run Plan – Part III

By Priyanka Dadwal | 17 Jan 2019

After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you the latest features introduced in the IC6.1.8 and ICADVM18.1 releases.

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Analog Design Environment | ICADVM18.1 | Rapid Adoption Kit | ADE | worst case corners | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | Run Plan | Custom IC Design | RAKs | IC6.1.8 | ADE Assembler
Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using Advanced Adaptive Mesh Extraction Technology in Quantus

By Shritam | 11 Jan 2019

In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy current losses in return paths of a transmission line/coiled spiral inductor. Current flow in such slotted metal structures is non-uniform, hence, traditional parasitic extraction approaches with predefined fracture length...

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Extraction | Quantus
Virtuosity: Saving Time, Effort, and Money with Express Pcells

By Pallabi R | 10 Jan 2019

Use the Express Pcell feature and see for yourself how you can save time, effort, and money!

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Advanced Node | Express Pcell | pcell | Virtuoso | Virtuosity | Layout design | Custom IC Design | Virtuoso Layout Suite | Parameterized Cell | Custom IC | Layout Editing
Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available

By Virtuoso Release Team | 20 Dec 2018

The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads . IC6.1.7 ISR23 ICADV12.3 ISR23 For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see: IC6.1.7 ISR23 README ICADV12.3 ISR23 README The links above are functional at the time of publishing. If you encounter...

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TAGS:

Virtuoso ICADV12.3 | Analog Design Environment | ICADV12.3 | Routing | IC 6.1 | Mixed-Signal | Virtuoso | Schematic Editor | IC6.1.7 | Virtuoso IC6.1.7 | Virtuoso Layout Suite | ADE Assembler
Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?

By Stefan Wuensche | 20 Dec 2018

This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. In addition, Spectre...

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spectre aps | Spectre EMIR | Virtuoso ADE | Spectre | EMIR | Voltus-Fi XL
Virtuosity: Doing Placement in a Row-Based Environment

By Priya Sriram | 17 Dec 2018

At advanced nodes, Virtuoso provides the capability of defining row templates and generating row regions in the layout design. You can then use the automatic and assisted placement options to place devices, Modgens, and standard cells in these rows.

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ICADVM18.1 | Advanced Node | Virtuoso Placer | Virtuoso Layout Suite | Custom IC | Row-Based Placement
Virtuosity: What Did I Miss in Virtuoso Visualization and Analysis and ADE during the IC6.1.7/ICADV12.3 ISRs?

By Arja H | 17 Dec 2018

Maybe you've been stuck on a project that used an older version of Virtuoso, maybe you've just subscribed to these blogs or maybe you're a new user to Virtuoso and perhaps you don't know about the new cool features that have been added over the course of the IC6.1.7/ICADV12.3 ISRs. We have packed a huge amount of enhancements in, the count is over 1600! I can't detail all of them here, but I'll outline the major enhancements...

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ICADV12.3 | ADE Explorer | Virtuoso | ViVA | IC6.1.7 | Custom IC Design | ADE Assembler
Virtuosity: Designing a Row-Based Layout Methodology – Why does this Make Sense at Advanced Nodes Today?

By Akshat | 6 Dec 2018

At advanced nodes, the complexity and volume of design rules have been growing exponentially. These challenges have contributed to the evolution of a row-based structured layout methodology, which lets you achieve a deterministic layout and increased layout efficiency.

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ICADVM18.1 | Advanced Node | Virtuoso Placer | Virtuoso | Virtuosity | Custom IC Design | Virtuoso Layout Suite | Row-Based Placement
Virtuosity:"What's In a Name?"

By Vani V | 29 Nov 2018

It discusses the benefits of introducing tooltips in the Simulator Options and Analysis Options forms in Virtuoso ADE Explorer and Virtuoso ADE Assembler.

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ADE Explorer | options | Analysis Options | Choose Analysis | Analysis | ADE | Virtuoso Analog Design Environment | Virtuoso | Custom IC Design | Options form | ADE Assembler
Virtuoso: The Next Overture – Concurrent Layout – a New Methodology for Team Design

By Sucharita | 15 Nov 2018

Any task when divided among multiple people gets done quickly... right? What if we told you that the new Layout XL ICADVM18.1 release features a concurrent layout methodology that lets multiple designers work on the same cellview at the same time! … interested to know more? Read on…

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Chip finishing | Virtuoso Next | Virtuoso Overture | ICADVM18.1 | Virtuoso New Design Platform | Virtuoso Advanced Release | Layout | Custom IC Design | Virtuoso Layout Suite | VLS XL | Virtuoso Layout Suite XL
Virtuosity: Is the Coloring Data Compliant with the MPT Flow?

By KomalJohar | 31 Oct 2018

In advanced node designs, to help you create designs that are compliant with the Multi-Patterning (MPT) flow set up, we have introduced the methodology compliance checker on the Multi-Patterning toolbar.

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Advanced Node | Multiple Patterning Technology | Virtuoso | Coloring Engine | Custom IC | Layout Editing
Virtuosity: Updated ADE Assembler and ADE Explorer Rapid Adoption Kit

By Arja H | 25 Oct 2018

The Virtuoso ADE Assembler and Virtuoso ADE Explorer Rapid Adoption Kit (RAK) has been updated for IC6.1.8/ICADVM18.1 to cover the new features. These include Setup Library Assistant Worst Case Corners in Run Plan Minor usability improvements

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ADE Explorer | Setup Library | Rapid Adoption Kit | Run Plan | ADE Verifier | IC6.1.8 | VVO | ADE Assembler
Virtuoso IC6.1.8 and ICADVM18.1 Now Available

By Virtuoso Release Team | 18 Oct 2018

The IC6.1.8 and ICADVM18.1 production releases are now available for download. To find out what new and enhanced features have been introduced, click here…

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Analog Design Environment | ICADVM18.1 | ADE Explorer | ADE | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Virtuoso: The Next Overture | Custom IC Design | Custom IC | IC6.1.8
Virtuoso: The Next Overture - Virtuoso RF Solution for High Frequency Product Designs

By deeptig | 8 Oct 2018

The latest Advanced Methodology Virtuoso release (ICADVM18.1) introduces Virtuoso RF Solution that allows you to create modules and packages in Virtuoso by leveraging new package design capabilities.

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Virtuoso Overture | custom/analog | Virtuoso New Design Platform | VRF | vsdp | Virtuoso | RF design | Custom IC | Virtuoso Layout Suite XL
Virtuoso - The Next Overture: Introducing Simulation Driven Routing

By Parula | 25 Sep 2018

The new release of the Virtuoso platform (ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven interactive routing for more robust and efficient design implementation as well as extending our support for the most advanced users.

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Interactive Routing | EAD | Virtuoso Next | Virtuoso Overture | Virtuoso New Design Platform | electrically aware design | Simulation-driven interactive routing | Mixed-Signal | Layout | Virtuoso | Custom IC Design | Custom IC
Virtuoso: The Next Overture - Congestion Analysis with a New Perspective

By Parula | 12 Sep 2018

Watch out for the exclusive set of routing features, along with the newly introduced Design Planner features in ICADVM 18.1, and then take a fresh new look at the new Congestion Analysis assistant.

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Congestion Analysis | Virtuoso Next | Virtuoso Overture | ICADVM18.1 | Virtuoso New Design Platform | Virtuoso Space-based Router | Routing | Virtuoso Advanced Release | Congestion Assistant | New in EDA | Custom IC Design | Virtuoso New Design | Design Planner | Custom IC
Virtuoso: The Next Overture – Introducing Design Planner

By Rishu Misri Jaggi | 7 Sep 2018

Watch out for our new layout design capability that allows you to plan more efficiently at the top level, block level, and at the cell level..

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Virtuoso Next | Virtuoso Overture | ICADVM18.1 | Virtuoso New Design Platform | Virtuoso Advanced Release | Virtuoso | New in EDA | Custom IC Design | Design Planner | Custom IC | Layout Editing
Virtuosity: Opening Old ADE States and Views with ADE Explorer and ADE Assembler

By Arja H | 3 Sep 2018

Have you found it a pain that when opening a Virtuoso ADE L state or a Virtuoso ADE XL view that the default application is still the old ADE L or XL? If you've moved on to Virtuoso ADE Assembler or Virtuoso ADE Explorer world then you need to change the application in the Open File dialog to ADE Explorer or ADE Assembler. To set the application by default we have added a couple of environment variables that you can set...

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TAGS:

Explorer | ADE Migration | ADE | Virtuoso Analog Design Environment | Analog Design Environment | Virtuosity | IC6.1.7 | Custom IC Design | Assembler

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