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Virtuosity: Spring-Cleaned Virtuoso Doc Closet

By Rishu Misri Jaggi | 19 Apr 2019

Most of us know how a spring-cleaned house can look like. But, do you know how the spring-cleaned Virtuoso documentation closet could look like?

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legato | Virtuoso Schematic Editor | ICADVM18.1 | Routing | ADE L | Virtuoso RF | Layout EXL | layout XL | Virtuoso | Layout L | Cadence Help | Virtuoso Doc | Virtuoso Design Environment | Virtuoso Layout Suite | IC6.1.8
Virtuoso Video Diary: Tune In to the MPT Video Channel

By KomalJohar | 9 Apr 2019

Tune In to the MPT Video Channel to check out a wide range of features easily accessible through the MPT toolbar.

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TAGS:

ICADVM18.1 | video | Layout | Virtuoso | Virtuoso Video Diary | advanced nodes | multi-patterning technology | Custom IC
Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts

By NamrataM | 4 Apr 2019

How about checking your designs for electromigration (EM) compliance before creating layouts? Why not? Read further to know more ...

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TAGS:

EAD | electromigration | ICADVM18.1 | electrically-aware design flow | Virtuoso electrically-aware design flow | EM | Virtuoso Layout Suite | IC6.1.8
Spectre Tech Tips: Spectre Assert and Design Check Overview

By Stefan Wuensche | 28 Mar 2019

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Besides performing Spectre simulations to verify that the design works as expected, you may want to check your design for critical device conditions, or typical design problems, such as high impedance nodes, leakage paths, or power consumption problems. This blog provides an overview of the Spectre...

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TAGS:

spectre aps | Circuit simulation | asserts | Spectre | SOA Checks | Design Checks
Virtuoso Video Diary: What Makes EM/IR Analysis A Significant Sign-Off Step?

By Vani V | 20 Mar 2019

This blog describes the EM and IR analyses in Virtuoso ADE as a design sign-off step. It take you to the videos demonstarting the analyses and how to set them up.

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TAGS:

ADE Explorer | EM/IR | power integrity | IC layout | ADE | Virtuoso Analog Design Environment | Virtuoso Video Diary | sign-off | Custom IC Design | Custom IC | IC design | EMIR
Virtuoso IC6.1.8 ISR2 and ICADVM18.1 ISR2 Now Available

By Virtuoso Release Team | 19 Mar 2019

The IC6.1.8 ISR2 and ICADVM18.1 ISR2 production releases are now available for download.

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TAGS:

ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | ADE | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Maestro Plotting Templates

By Chandrika Durbha | 18 Mar 2019

Waveforms, plots, graphs, measurements, markers... are all a part and parcel of any circuit designer’s everyday life. For a regular user of Virtuoso ADE Explorer or Virtuoso ADE Assembler and the ADE waveform window, packaged with IC6.1.6/IC6.1.7 release, it was a common task to redo the measurements on plots every time the plot was refreshed or when a new simulation was set up. How about a feature that lets you save...

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ICADVM18.1 | ADE Explorer | ViVA | plotting templates | maestro plotting templates | Custom IC Design | IC6.1.8 | ADE Assembler
Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis

By Arja H | 8 Mar 2019

Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with the applied stimuli, it was necessary to run the simulations using both digital and analog solvers. This could be a time-consuming process. However, now you can read in the digital stimuli files directly into Cadence Virtuoso Visualization and Analysis, the ADE waveform window. In addition, you can plot the analog waveforms using the stimuli...

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TAGS:

VCD | Analog Design Environment | ICADVM18.1 | analog | ViVA | Virtuosity | analog stimuli | IC6.1.8 | vector
Virtuosity: Identifying Those Traces

By AdityaMainkar | 6 Mar 2019

With the ever-increasing number of simulations required to be run these days, the sheer number of plots can be overwhelming and it can be difficult to figure out which Cadence Virtuoso ADE XL, Virtuoso ADE Assembler or Virtuoso ADE Explorer history, test or corner each plot belongs to. To help with this, from IC.6.1.8/ICADVM18.1 Virtuoso Visualization and Analysis we have made identifying and comparing traces across...

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TAGS:

Explorer | plotting | ADE XL | Virtuoso | Analog Design Environment | ViVA | ADE-XL | Virtuosity | Assembler
Spectre Tech Tips: Device Aging? Yes, even Silicon wears out

By Moustafa Moham | 28 Feb 2019

While most of us would like our electronic gadgets to last forever, the reality is that these gadgets have a lifetime. Most of the time, the lifetime of devices is limited by either mechanical (switch, relay), or thermal (fuse, capacitor) failures. However, as microchips designed in advanced technologies become more pervasive, the lifetime of microchips has become an additional issue. Several effects contribute to...

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TAGS:

stress analysis | TDDB | PBTI | native reliability analysis | Spectre | reliability analysis | HCI | NBTI | reliability
Virtuosity: New Flexible Subwindows

By Arja H | 26 Feb 2019

Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or subwindow. Subwindows allow you to see plots from different analyses side by side. Until IC6.1.8/ICADVM18.1, the subwindows were not very flexible. Now, we've improved these so that you can choose any grid layout of subwindows up to a 6x8 grid. In addition, you can resize the subwindows easily and move them around. These subwindow configurations...

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TAGS:

ICADVM18.1 | subwindows | waveforms | Virtuoso Analog Design Environment | ViVA | Virtuosity | plotting templates | Custom IC Design | IC6.1.8
Virtuosity: A Smart Extracted View

By Arja H | 21 Feb 2019

The Cadence Quantus Smart View is the next generation of the Extracted View in the Virtuoso environment. The Smart View provides the same functionality as the Extracted View, but it uses a highly efficient and scalable storage mechanism. This means that Smart View can manage larger, more complex designs at advanced nodes with a reduced overall extraction run time and netlist size. In fact, the Smart View not only helps...

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Smart View | PAD | ICADVM18.1 | ADE Explorer | Virtuoso | Virtuosity | Quantus | IC6.1.8 | parasitics | ADE Assembler | Virtuoso Layout Suite XL
Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct

By NamrataM | 14 Feb 2019

Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster...

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TAGS:

electromigration | ICADV12.3 | ICADVM18.1 | EM/IR | Layout Suite | IC6.1.7 | EM | electrically-aware design | IR drop | IC6.1.8
Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design

By Hiro Ishikawa | 7 Feb 2019

How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.

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TAGS:

Analog Design Environment | Virtuoso New Design Platform | Physical placement and layout | Advanced Node | Virtuoso | Custom IC Design
Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!

By Rashmi G | 7 Feb 2019

Cutting-edge innovation … Top-down planning … Reliable and formalized verification … Scalable performance ! These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso ® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification...

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TAGS:

verifier | PVT | ICADVM18.1 | custom/analog | Formalized Verification | Analog Simulation | ADE | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | space | Custom IC Design | ADE Verifier | IC6.1.8 | ADE Assembler | verification
Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

By Virtuoso Release Team | 6 Feb 2019

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download.

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TAGS:

Analog Design Environment | ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | ADE | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Virtuoso: The Next Overture | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

By Yagya Mishra | 31 Jan 2019

An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This...

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TAGS:

verifier | PVT | coverage | Analog Coverage | Analog Simulation | Virtuoso Analog Design Environment | space | Custom IC Design | Assembler | verification
Virtuosity: Introducing the Pin Tool

By Priya Sriram | 28 Jan 2019

The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the various menus in the Pin Tool. The tool includes several new options that let you perform a wide range of pin-related tasks.

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Spectre Tech Tips: Optimizing Spectre APS Performance

By Stefan Wuensche | 24 Jan 2019

This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions for typical setup problems causing performance issues, and delivers tips on advanced methods for optimizing simulation performance.

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TAGS:

spectre aps | Circuit simulation | ADE Explorer | simulation performance | Simulation Accuracy | Spectre XPS MS | ADE | Spectre Tech Tips | Spectre
Virtuosity: What's New in Run Plan – Part III

By Priyanka Dadwal | 17 Jan 2019

After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you the latest features introduced in the IC6.1.8 and ICADVM18.1 releases.

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TAGS:

Analog Design Environment | ICADVM18.1 | Rapid Adoption Kit | ADE | worst case corners | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | Run Plan | Custom IC Design | RAKs | IC6.1.8 | ADE Assembler
Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using Advanced Adaptive Mesh Extraction Technology in Quantus

By Shritam | 11 Jan 2019

In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy current losses in return paths of a transmission line/coiled spiral inductor. Current flow in such slotted metal structures is non-uniform, hence, traditional parasitic extraction approaches with predefined fracture length...

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TAGS:

Extraction | Quantus
Virtuosity: Saving Time, Effort, and Money with Express Pcells

By Pallabi R | 10 Jan 2019

Use the Express Pcell feature and see for yourself how you can save time, effort, and money!

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TAGS:

Advanced Node | Express Pcell | pcell | Virtuoso | Virtuosity | Layout design | Custom IC Design | Virtuoso Layout Suite | Parameterized Cell | Custom IC | Layout Editing
Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available

By Virtuoso Release Team | 20 Dec 2018

The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads . IC6.1.7 ISR23 ICADV12.3 ISR23 For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see: IC6.1.7 ISR23 README ICADV12.3 ISR23 README The links above are functional at the time of publishing. If you encounter...

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TAGS:

Virtuoso ICADV12.3 | Analog Design Environment | ICADV12.3 | Routing | IC 6.1 | Mixed-Signal | Virtuoso | Schematic Editor | IC6.1.7 | Virtuoso IC6.1.7 | Virtuoso Layout Suite | ADE Assembler
Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?

By Stefan Wuensche | 20 Dec 2018

This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. In addition, Spectre...

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TAGS:

spectre aps | Spectre EMIR | Virtuoso ADE | Spectre | EMIR | Voltus-Fi XL
Virtuosity: Doing Placement in a Row-Based Environment

By Priya Sriram | 17 Dec 2018

At advanced nodes, Virtuoso provides the capability of defining row templates and generating row regions in the layout design. You can then use the automatic and assisted placement options to place devices, Modgens, and standard cells in these rows.

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TAGS:

ICADVM18.1 | Advanced Node | Virtuoso Placer | Virtuoso Layout Suite | Custom IC | Row-Based Placement

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