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Virtuoso Video Diary: Reusing Variables through CSV Export and Import

By Rashmi G | 5 Apr 2018

Do you have some specific variables in a test and wonder if you could have a way to reuse them globally for all tests or locally in a particular test? You will be glad to know that Virtuoso ADE Assembler and Virtuoso ADE Explorer offer you a simple and time-saving solution to perform this task. You can now export variables in a CSV file and then use the same file to import them as global or local variables in any session...

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Analog Design Environment | custom/analog | Explorer | Analog Simulation | analog | ADE | Virtuoso Analog Design Environment | Virtuoso | Virtuoso Video Diary | Custom IC Design | Assembler | ADE Assembler
Virtuosity: What if I Want to Disable the Filtered Corners?

By Arja Hunkin | 29 Mar 2018

You'll now be an expert at using the Corner Filters in Virtuoso ADE Assembler and Virtuoso ADE Explorer, I'm sure. But so far, you could only enable the corners you found during filtering. Now, we can offer even more flexibility. You can now disable the corners you find using the filters, and also incrementally enable or disable the filtered corners.

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Corners | ADE Explorer | filter | Filtering | ADE | Virtuoso Analog Design Environment | Virtuoso | Analog Design Environment | Virtuosity | Custom IC Design | Custom IC | ADE Assembler
Virtuoso IC6.1.7 ISR18 and ICADV12.3 ISR18 Now Available

By Virtuoso Release Team | 21 Mar 2018

The IC6.1.7 ISR18 and ICADV12.3 ISR18 production releases are now available for download. To find out more, click here…

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IC | ICADV12.3 | ADE | Layout | Virtuoso | Virtuosity | IC6.1.7 | Custom IC Design | Custom IC
Virtuosity: Signal Browsing Gets Easier with Advanced Search Options

By Ashu V | 14 Mar 2018

Imagine what would happen if we were living in the world with no search engines. Wouldn’t we find ourselves lost in the deep information ocean, struggling to find the relevant stuff? The situation would be chaotic and nothing short of a nightmare. Cutting-edge search technology has given us unprecedented access to information at the click of a button—something that our previous generations could only dream of. Web search...

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ViVa-XL | custom/analog | Virtuoso Analog Design Environment | ViVA | Virtuosity | Circuit Design | Custom IC Design | Custom IC
Virtuosity: Do I Need To Run a Simulation To Plot From a Text File?

By Arja Hunkin | 8 Mar 2018

You'll be glad to hear the answer is No! In Virtuoso Visualization and Analysis, we have a Calculator function available called getAsciiWave, which will create a plot from your text file without the need to create a schematic or a testbench, or run simulation. Let's see how easy it is with the help of an example.

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Analog Design Environment | ViVa-XL | ADE Explorer | Explorer | Analog Simulation | ADE XL | ADE | Virtuoso Analog Design Environment | Virtuoso | Analog Design Environment | ViVA | Virtuosity | Assembler | ADE Assembler
Virtuosity: New Eye Diagram Measurements

By Arja Hunkin | 23 Feb 2018

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create eye diagrams, add masks and also calculate some standard measurements. The measurements have recently been enhanced by adding more jitter calculations, maximum eye height and width calculations, level annotations and Bit Error Rate (BER) curves.

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Eye Mask | Analog Design Environment | ViVa-XL | ADE Explorer | Explorer | ADE XL | ADE | eye diagram | Analog Design Environment | ViVA | ADE-XL | Virtuosity | Custom IC Design | ADE Assembler
Virtuoso Video Diary: Self-Paced Learning through Training Bytes

By Uma Peethambaran | 14 Feb 2018

Cadence Education Services offers several online training courses and training bytes addressing specific features of Virtuoso products. This blog gives you a brief overview about how to find them and enroll.

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training bytes | Virtuoso | Virtuoso Video Diary | Virtuoso Layout
Virtuoso Video Diary: Stranded Wire – A New Sapling in Interactive Routing

By Parul Agarwal | 9 Feb 2018

In order to drive high current and to minimize routing resistivity, it is desirable to draw wide wires. But, in mature nodes, maximum width or maximum density constraints on some metal layers prevent the designers to create wide wires. Another challenge when working with designs at advanced nodes less than 22nm is that it is only possible to route with wires at minimum width. This leads to situations where the current...

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interactive coloring | stranded wire | Virtuoso Space-based Router | weStrandedColorMode | leHiCreateStrandedWire | blockage avoidance | weStrandedAlignCollinearMode | Virtuoso | Stranded Wire Context-sensitive Menu | Virtuoso Video Diary | tieout | weStrandSpacing | tapering in stranded wire | Custom IC Design | WSP support in Stranded Wire | space based router | Custom IC | weStrandedLadderAtTurn | weStrandNum
Virtuosity: Sharing Custom SKILL Calculator Functions

By Arja Hunkin | 2 Feb 2018

Have you ever written a fantastic piece of SKILL to carry out a calculation and wanted to tell the world about it? Or maybe you really need a calculator function to perform a calculation but Cadence does not supply that function with the Calculator or Expression Builder? We have a new Custom IC Calculator SKILL Function Library where you can visit and download custom SKILL scripts and upload any of your own that you...

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Analog Design Environment | ADE Explorer | Virtuoso | ViVA | Custom IC Design | SKILL | ADE Assembler
Virtuosity:Expression Builder - Now Plots ALL!

By Arja Hunkin | 19 Jan 2018

The Expression Builder has simplified writing complex expressions and has the ability to plot or evaluate particular points and corners. But we wanted it to do more, recently we added the ability to plot or evaluate across all points and/or all corners.

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ADE Explorer | ADE | Expression Builder | Virtuoso | ViVA | Virtuosity | ADE Assembler
Virtuosity and Virtuoso Video Diary: Onwards and Upwards

By Ashu V | 16 Jan 2018

Looking back at 2017, I note with satisfaction that it was a phenomenal year of blogging that saw us achieving tons more than we’d dreamed of. Our twin series of blog posts—Virtuosity and the Virtuoso Video Diary—garnered appreciation from all around the world and made it to that coveted special zone in the web browser of our readers—Favorites! Beginning small sometime in the middle of 2016, these series now attract a...

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Cadence blogs | custom/analog | Virtuoso | RF design | Virtuosity | Virtuoso Video Diary | Custom IC Design | Custom IC
Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together

By Rishu Misri Jaggi | 14 Dec 2017

“The reason birds can fly and we can't is simply because they have perfect faith, for to have faith is to have wings.” ― J.M. Barrie, The Little White Bird When a few of us in the Cadence CAS Technical Communications Engi...

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Cadence blogs | Virtuoso | RF design | Virtuosity | Virtuoso Video Diary | CPG Technical Communications Engineering
Virtuosity: SKILLful Virtuoso Visualization and Analysis

By Ashu V | 10 Dec 2017

If you’re a SKILL enthusiast, you’ll be happy to know that the latest IC6.1.7 ISR release offers some very useful and handy SKILL functions to perform certain tasks in ViVA. You may find them useful too. Let’s take a quick look at them.

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Analog Design Environment | ViVa-XL | custom/analog | Analog Simulation | SKILL for the Skilled | ADE | Virtuoso | ViVA | Virtuosity | Custom IC Design | SKILL | Cusstom IC Design
Virtuosity: Can I Graphically Edit Width Spacing Patterns?

By Komal Johar | 7 Dec 2017

We have enhanced the editing modes available for WSPs. In addition to the text-based editing, you can now graphically edit WSPs in the preview mode.

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Routing | Advanced Node | width spacing patterns | Layout | Virtuoso | Virtuosity | Custom IC Design
Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

By Arja Hunkin | 5 Dec 2017

Have you been frustrated trying to drag signals around in Virtuoso Visualization and Analysis only to see this icon telling you that you can't drag the signal there? You can right-click on the axis and check the Allow Any Units option,...

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virtuoso visualization and analysis | Virtuoso Analog Design Environment | Analog Design Environment | ViVA
Virtuosity: CDNLive India—Our Window to KYC!

By Rishu Misri Jaggi | 4 Dec 2017

In line with the recently-implemented mandate in India requiring banks and financial institutions to regularly run “Know Your Customer (KYC)” cycles, CDNLive India has become a reliable event for the Technical Communications Engineering team to regularly touch base with customers, and to ensure the team knows their customers in order to exceed customer expectations. The Publications Infrastructure and CPG Technical...

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CDNLive India 2017 | Cadence Help Future | Virtuosity | Virtuoso Video Diary | Cadence Help 3.0
Virtuosity: Organizing Waveform Families

By Arja Hunkin | 21 Nov 2017

When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you might want to group plots with the same values together, or display each corner in the same color etc. Of course, you can right-click on the plot and select Copy to or Move to and move the plots manually, but did you know there was an assistant to do this for you?

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ADE GXL | ADE Explorer | ADE XL | ADE | Virtuoso Analog Design Environment | Analog Design Environment | ViVA | Virtuosity | ADE Assembler
Dealing with AOCVs in SRAMs

By Priya Balasubramanian | 16 Nov 2017

Systems on Chip, or SoCs as they’re more commonly called, have become increasingly more complex, and incorporate a dizzying array of functionality to keep up with the evolving trends of technology. Today’s SoCs are humongous multi-billion-gate designs with huge memories to enable complex and high-performance functions that are executed on them. It is quite common to have about 40% of an SoC’s real estate used for Static...

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legato | custom/analog | Monte Carlo analysis | Monte Carlo | Spectre | Custom IC Design | Custom IC
Virtuosity: All New XStream In - The Translation Expressway

By Sucharita Mehta | 10 Nov 2017

A layout design has to go through several iterations and multiple data exchanges across tools for different types of processing during the designing process. At each stage, a large-sized, hierarchical layout needs to be imported into Virtuoso. Therefore, you need a translation tool that is fast and reliable. The new IC617/12.2 XStream In translator with its latest performance upgrades ensures this and a lot more. Read...

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xstream in | design data translator | xstream in import | eda import
Art of Analog Design Part 7: Mismatch Tuning

By Arthur Schaldenbrand | 3 Nov 2017

In days of future past, we looked at DC mismatch analysis and compared it to Monte Carlo analysis for analyzing the effect of device mismatch on the offset voltage of a differential amplifier. We found that DC mismatch does provide good estimates of the effect of mismatch with the limitation that the offset voltage has a Gaussian distribution. Since DC mismatch analysis only needed a single simulation to generate an...

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mismatch tuning | Monte Carlo analysis | DC Mismatch
Simplifying the Memory Design Process

By Kimberly Khoury | 30 Oct 2017

On today’s SOC designs, the memory control logics and memory arrays take up a lot of real estate in terms of area and as a part of the larger system since it mostly determines the performance of the application. Regardless of the processors and the interconnect, the memory system provides the instructions and operands and the application cannot be executed any faster than the memory system can handle. Due to this constant...

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Memory | custom/analog | Spectre | Custom IC Design | Custom IC
Virtuosity: Read Mode Done Right

By stacyw | 26 Oct 2017

Because of the ease with which you can set up complex sweep, corner and Monte Carlo simulations, the Virtuoso ADE tools are frequently used to perform verification and regression simulation runs. Those runs are most commonly done by accessing cellviews in read-only mode (RO), so that the “golden” simulation setups are not modified and there is no need to check out the cellviews from the design management (DM) vault. ...

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ADE Explorer | Custom IC Design. Read only | ADE | Analog Design Environment | ADE Assembler
The Art of Analog Design Part 6: Response to Frank’s Question to Part 4

By Arthur Schaldenbrand | 23 Oct 2017

In the comments to blog #4, Frank Wiedmann asked about the correlation between the results of mismatch from Monte Carlo analysis and DC mismatch analysis. It is a fair question and here is a short blog to explore the topic. The example may not be realistic, but it is a useful for exploring the effects of mismatch on a circuit. Let’s start with a simple circuit—A resistively loaded differential amplifier with cascodes...

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spectre aps | Virtuoso Variation Option | ADE Explorer | mismatch analysis | Analog Simulation | Monte Carlo analysis | DC Mismatch | Custom IC Design
The Art of Analog Design Part 4: Mismatch Analysis

By Arthur Schaldenbrand | 15 Oct 2017

In Part 3 , we started to explore how to analyze the results of Monte Carlo analysis. In Part 4, we will consider the question, what is the relationship between process variation and the circuit’s performance variation? The tool for exploring the relationship process variation and circuit performance variation is mismatch analysis in the tool Virtuoso ® Variation Option (VVO). Let’s start by looking at a simple example...

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spectre aps | Analog Design Environment | Virtuoso Variation Option | mismatch analysis | Analog Simulation | Monte Carlo | Custom IC Design
The Art of Analog Design Part 5: Mismatch Analysis II

By Arthur Schaldenbrand | 13 Oct 2017

In Part 4 of the series, we looked at applying mismatch analysis as a design tool. In Part 5, we will continue to look at mismatch analysis by applying the technology to other types of designs.. The first case we will look at is a circuit without a DC operating point. A dynamic comparator, see Figure 1, doesn’t have a quiescent operating point making it difficult to analyze. In this case, the offset voltage is...

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spectre aps | offset voltage | mismatch analysis | Analog Simulation | ADE | Monte Carlo analysis | Strong Arm latch | dynamic comparator

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