Custom IC Design Blogs

You can now use the Performance Diagnostic tool in the Virtuoso custom IC design platform to diagnose issues that might be causing your system to slowdown or freeze. Click here to know more.

Continuing our momentum with the Knowledge Booster blogs in the year 2021 , this blog informs you how to overcome DC Convergence issues and errors for a Spectre Simulation by modifying associated parameters.

The ICADVM20.1 ISR16 and IC6.1.8 ISR16 production releases are now available for download.

In the Spectre 20.1 base release at the end of September 2020, we released Spectre X-RF. The Spectre X-RF technology integrates the Spectre X engine into Spectre’s RF analyses. In this blog, we introduce the Spectre X-RF technology.

Have you missed out on any of the In the Line of Veri-Fire blogs? Here's your chance to fix it...

Do you want to know how discovering the path of least resistance for the devices of your design much ahead of your power planning can make your life easier? Then go ahead and read the blog.

The Spectre X distributed simulation is an extension to the multithreaded simulation where cores from different machines are used. The Spectre X distributed simulation provides access to more cores, thus increasing the performance and capacity and providing more value for large designs.

Fast growing markets like 5G, automotive, and IoT are driving the development of advanced semiconductor technologies and silicon-integrated circuits. In particular, the high cutoff frequency of advanced CMOS and Silicon-Germanium (SiGe) bipolar devices allow the integration of millimeter-wave circuits with good high-frequency performance and high integration level at moderate mask costs.

The Allegro Package Designer product line offers everything needed to take an IC package from idea to manufactured part, and this is where the journey takes us today. It is available from your Virtuoso environment as Virtuoso MultiTech Framework.

If you have been following the Conserve Power blog series, you will probably have an idea of what next I am going to talk about. Yes, we have now reached the finale, the last and the most intriguing piece in the entire story. It is the formal verification and sign-off of the IP to make it ready to be integrated into an SoC.

A blog that tells you about why splitting up blocks has now become a useful feature in more complex designs and advanced technology.

Read our story about how teams across Cadence, diligently work towards enhancing your experience by continuously improving the quality of user interfaces from a usability aspect.

We live in a complex world where it is essential to use and combine tools and platforms as efficiently as possible with all available features. In this blog, we are happy to show you how easy it can be to get best results using the Spectre Simulation Platform and its corresponding options.

The IC6.1.8 ISR15 and ICADVM20.1 ISR15 production releases are now available for download.

Welcome to a post on how to create component and padstack libraries for use in the Virtuoso platform-driven multiple technology flows. This post describes the tasks of a librarian, who must assemble component IP from various sources and create the views and documentation that can be used by designers.

In this blog, I will focus on the key enablers, which are required before the power-aware designs undergo the verification cycle. This is the ultimate test that confirms the robustness and efficiency of a design.

What if you could foresee potential changes in your design and analyze their impact in advance? I’m sure, your life would have been easier, isn’t it? Read on to know more about the what-if or ECO analysis feature in Voltus-Fi-XL.

Today’s blog focuses on in-design checks that offer an easy and convenient way to identify common design issues encountered by the design community while implementing low power schemes. It also helps designers to uncover issues early in the design cycle, avoiding an ECO.

Do you want accurate extraction data for your design, regardless of foundry process and node? Do you want to complete your EMIR setup entirely within the Virtuoso framework? Then explore the new Virtuoso EMIR DSPF flow…

This time I am back with a blog that briefly explains how to set up Virtuoso Power Manager before proceeding with low power verification. To run in-design checks, extract the power intent from a design, or run Conformal Low Power checks, you must first provide inputs that are required by the tool for correct identification of design topology and define the set of rules that apply to those design structures. For example...

Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.

Power consumption has always been an overriding concern in electronic design. Consumption relates not only to the power used in the circuitry but also involves monitoring the circuit to prevent overheating. The battery life of any electronic product can be a deciding factor in its success. Designers are continually devising innovative methods to ensure minimal power consumption without impacting the performance of their...

EMIR analysis is one of the more challenging fields of circuit simulation. It requires the power and/or signal net parasitics to be preserved for the later IR drop and EM current analysis. At the same time the EMIR analysis requires SPICE accuracy for properly checking the EM currents against the current limits defined by the foundry. The Cadence transistor level EMIR analysis tool is Voltus-Fi XL which uses the Spectre...

Read through this blog to know more about the usability enhancements made to digital signals in Virtuoso Visualization and Analysis XL.

When you are running the EM analysis for an RF module with a wirebonded IC, an important task is to capture the full coupling between the package and the bond wires. Read this blog to know about a quick and effortless way to do this in Virtuoso RF Solution.