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Virtuoso Meets Maxwell: How to Route a Package in Virtuoso?

By Alex Soyer | 25 May 2020

Let’s explore how a package design looks like in Virtuoso, how it can handle planes as well, and how to route the package quickly and cleanly.

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shove | ICADVM18.1 | route a package | push | Virtuoso Layout EXL | Virtuoso Meets Maxwell | route | Virtuoso RF Solution | Virtuoso RF | Layout EXL | Package Design in Virtuoso | system design | RF design | push and shove | Custom IC Design | Custom IC
Virtuosity: Rewind and Replay the Top 10 Cadence Virtuosity and Virtuoso Video Diary Blogs

By Rishu Misri Jaggi | 18 May 2020

With new content being posted nearly every week under Custom IC Design Blogs, there's a lot this space can tell you about Virtuoso. Let me help you find some of our most viewed posts...

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Analog Design Environment | Cadence blogs | ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | MODGEN | Auto Place and Route | System Design Platform | APR | Layout | Virtuoso | Virtuosity | Virtuoso Layout Suite | Custom IC | simulation | IC6.1.8 | ADE Assembler | MTS
Virtuoso IC6.1.8 ISR11 and ICADVM18.1 ISR11 Now Available

By Virtuoso Release Team | 13 May 2020

The IC6.1.8 ISR11 and ICADVM18.1 ISR11 production releases are now available for download.

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Cadence blogs | ICADVM18.1 | ADE Explorer | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso Visualization and Analysis XL | Virtuoso Analog Design Environment | Virtuoso | IC Release Blog | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part VI

By Kabir | 11 May 2020

This is the last blog in the miniseries that aims at providing in-depth details of electromagnetic analysis in Virtuoso RF Solution. To learn about a few tips and tricks on the simulation setup, read more...

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EM Analysis | AXIEM | ICADVM18.1 | awr | Virtuoso RF | Electromagnetic analysis | 3D EM simulation | AWR AXIEM | Custom IC Design | Virtuoso Layout Suite
Virtuosity: Can You Build Lego Masterpieces with All Blocks of One Size?

By KomalJohar | 30 Apr 2020

The way you need blocks of different sizes and styles to build great Lego masterpieces, a complex WSP-based design requires stitching together routing regions with multiple patterns that follow different WSSPDef periods. Let's see how you can achieve this.

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ICADVM18.1 | cadence | WSP | Advanced Node | Local regions | Layout Suite | width spacing patterns | Layout | Virtuoso | Virtuosity | usability | Custom IC | ux | WSSPDef
Virtuoso Meets Maxwell: Die Export Gets a Facelift

By Kabir | 27 Apr 2020

Hello everyone, today I’d like to talk to you about the recent enhancements to Die export in the Virtuoso RF Solution, most of which were released in ICADVM 18.1 ISR10. What’s the background for these enhancements? Exporting an abstract of a Die, which basically represents the outer boundary of the Die with I/O locations, as an intermediate file to exchange information between various Cadence tools (i.e., the Innovus...

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ICADVM18.1 | die export | Virtuoso Meets Maxwell | Advanced Node | Virtuoso RF | Wirebond | Virtuoso | System Design Environment | shape-based die | RF design | Custom IC Design | SKILL
Virtuosity: Concurrently Editing a Hierarchical Cellview

By Sucharita | 15 Apr 2020

This blog discusses key features of concurrently editing a hierarchical cellview.

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concurrent edit hierarchical subcell | concurrent layout editing | ICADVM18.1 | concurrent editing | CLE | concurrent hierarchical editing | Custom IC Design | Virtuoso Layout Suite | Custom IC | Layout Editing
Virtuoso Meets Maxwell: Keeping Things Simple in the Virtuoso RF Solution

By kfullerton | 13 Apr 2020

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic simulation is an activity where following that advice has enormous payoffs. In this blog I’ll talk about some of my experiences with how Virtuoso RF Solution’s shape simplification feature has helped my customers get significant performance improvements with minimal impacts on accuracy.

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EM Analysis | ICADVM18.1 | Virtuoso New Design Platform | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso RF | Electromagnetic analysis | RF design | Custom IC Design | Virtuoso Layout Suite
Virtuoso Meets Maxwell: What About My Die That Has No Bumps, Only Pad Shapes? How Do I Export That?

By Kabir | 6 Apr 2020

If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad shapes and labels to identify I/O locations, then you might be feeling a bit left out of all of this jazz and tango. Hence, today, I am writing to tell you that, fear not, we have a solution for your Die as well.

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ICADVM18.1 | die export | VRF | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF Solution | Virtuoso RF | Package Design in Virtuoso | die | System Design Environment | shape-based die | RF design | shape | Custom IC | VMM
Virtuosity: Are Your Layout Design Mansions Correct-by-Construction?

By KomalJohar | 26 Mar 2020

Do you want to create designs that are correct by construction? Read along this blog to understand how you can achieve this by using Width Spacing Patterns (WSPs) in your designs. WSPs, are track lines that provide guidance for quickly creating wires. Defining WSPs that capture the width-dependent spacing rules, and snapping the pathSegs of a wire to them, ensures that the wires meet width-dependent spacing rules.

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ICADVM18.1 | Advanced Node | Layout Suite | width spacing patterns | Layout | Virtuoso | Virtuosity | usability | Custom IC Design | ux
Virtuoso IC6.1.8 ISR10 and ICADVM18.1 ISR10 Now Available

By Virtuoso Release Team | 25 Mar 2020

The IC6.1.8 ISR10 and ICADVM18.1 ISR10 production releases are now available for download.

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Cadence blogs | ICADVM18.1 | ADE Explorer | IC Release Announcement blog | Virtuoso Visualization and Analysis XL | Virtuoso RF | Virtuoso Analog Design Environment | Virtuoso | IC Release Blog | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part V

By Kabir | 23 Mar 2020

Here is another blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. Read to learn about the nuances of port setup for electromagnetic analysis.

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EM Analysis | ICADVM18.1 | VRF | Virtuoso Layout EXL | ports | Virtuoso RF | Electromagnetic analysis | Virtuoso | Virtuoso Layout Suite | Custom IC
Virtuosity: Device Arrays in the Automated Device Placement and Routing Flow

By Sravasti | 17 Mar 2020

Since the release of the Automated Device Placement and Routing solution last year, we have continued to improve and build upon it. In this blog, I’ll talk about the latest addition—the Auto Device Array form—how this is an integral piece of the new Automated Device Placement and Routing solution.

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Modgen On Canvas | ICADVM18.1 | MODGEN | Automated Device-Level Placement and Routing | APR Modgen | Advanced Node | auto device array | APR | Auto P&R | advanced nodes | ada | Custom IC Design | Custom IC
Virtuoso Meets Maxwell: Bumps, Bumps.... Where Are My Bumps?

By Brian LaBorde | 16 Mar 2020

Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection between stacked ICs, interposers, packages, and boards. Bump locations, connectivity, and other attributes are the basis for creating TILPs, which we combine to create system-level layouts.

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ICADVM18.1 | Edit-in-Concert | Co-Design | Virtuoso Meets Maxwell | Virtuoso RF | Layout EXL | stacked solution | Custom IC Design | bumps
Virtuoso Meets Maxwell: Common Goal for One Flow, Acquisitions Strengthen RF Flow

By michaelthompson | 9 Mar 2020

Seven months ago, I pointed out the ongoing need for change, or revolution, in high-frequency design flows. Spreading design IP across multiple, unconnected tools, is leading to manufacturing and design errors. It also slows the design flow and forces designers to focus on keeping track of edits and updates and not on innovating. Keeping track of the right s-parameter file may be a necessary evil in your current design...

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integrand | ICADVM18.1 | Virtuoso New Design Platform | awr | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Advanced Node | Virtuoso RF | Electromagnetic analysis | EMX | RF design | microwave office | Custom IC Design | Virtuoso Layout Suite | acquisitions
Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 2

By Dishika Majumdar | 5 Mar 2020

Learn more about Cadence Education Services with this blog, which includes a list of training programs for various Virtuoso products and guidance on how to become Cadence certified in a certain technology or skill.

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digital badges | training bytes | Virtuoso | Virtuoso Video Diary | Virtuoso Layout
Virtuosity: Auto Device Array - A One-Stop-Shop for Modgens

By Aneesh Shastry | 27 Feb 2020

Hello everybody! I'm back with a new blog on Modgens. In this blog, I'm going to talk about an important new feature—the Auto Device Array form. Read the blog to know more about how this new feature has simplified the tasks of creating and customizing Modgens.

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Modgen On Canvas | MODGEN | APR Modgen | Advanced Node | auto device array | Layout EXL | Analog Layout Automation | ada | Analog Layout | Custom IC Design | modgens | Virtuoso Layout Suite | Custom IC
Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 1

By Dishika Majumdar | 20 Feb 2020

This blog will take you on a short tour to the Cadence Education Services site, which has several online training courses and bytes based on specific features of Virtuoso products.

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training bytes | Virtuoso | Virtuoso Video Diary | Virtuoso Layout
Virtuosity: Updated Virtuoso ADE Explorer and ADE Assembler RAKs in IC6.1.8/ICADVM18.1 ISR9

By Arja H | 13 Feb 2020

To show the latest features in IC6.1.8/ICADVM18.1 ISR9, we've updated the Rapid Adoption Kits for Virtuoso ADE Assembler and Virtuoso ADE Explorer. In addition, we have updated the RAK that explains the Stimuli Assignment form.

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ICADVM18.1 | ADE Explorer | Rapid Adoption Kit | RAK | stimuli | Virtuoso Analog Design Environment | Virtuosity | Custom IC Design | ADE Assembler | Stimuli Assignment form
Virtuosity: Blogging Journey of Virtuoso Place and Route in 2019

By Parula | 7 Feb 2020

To support various new features and enhancements in Virtuoso Placement and Routing, our tech gurus and the writers collaborated to publish some informative blogs in 2019. This blog is a sneak peek into the blogging journey of Virtuoso Placement and Routing and provides you a handy summary to make it easy for you to read these blogs at your leisure.

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tree routing | Modgen On Canvas | structured routing | ICADVM18.1 | Virtuoso Space-based Router | EXL | mesh routing | MODGEN | Automated Device-Level Placement and Routing | Virtuoso Placer | Layout EXL | trunk-to-trunk mesh | Auto P&R | Mixed-Signal | Tree Route | Layout Suite | trunk creation | Generate Trunk | Finish Trunk | EM Trunk Optimization | Custom IC Design | Virtuoso Layout Suite | Custom IC
Virtuosity: Reminiscing About The Last 'Teen' Year of Custom IC Design Blogs

By Dishika Majumdar | 24 Jan 2020

If you have missed reading any of our Virtuosity, Virtuoso Meets Maxwell, Virtuoso Video Diary blogs that were published in 2019, or you would like to go back to an ISR release announcement to see what were the featured enhancements, here's your chance to bookmark this blog for all that interesting information and for some of our most-viewed posts from the last year. Also, stay tuned to our new content arriving soon.

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ICADVM18.1 | Automated Device-Level Placement and Routing | Virtuoso RF | Layout EXL | Electromagnetic analysis | Virtuoso | Virtuosity | Custom IC Design | Virtuoso Layout Suite | Custom IC
Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis in 2019

By shubhangi upadhyay | 19 Dec 2019

2019 was quite an eventful year for Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis XL. We not only added new features such as Multi-Test Editor, but also redesigned existing forms to give you the best possible experience with the existing features.

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ADE waveform window | Cadence blogs | ICADVM18.1 | ADE Explorer | virtuoso visualization and analysis | Virtuosity | Virtuoso Video Diary | Custom IC Design | ADE Verifier | IC6.1.8 | ADE Assembler
Virtuoso IC6.1.8 ISR8 and ICADVM18.1 ISR8 Now Available

By Virtuoso Release Team | 11 Dec 2019

The IC6.1.8 ISR8 and ICADVM18.1 ISR8 production releases are now available for download.

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Cadence blogs | ICADVM18.1 | ADE Explorer | IC Release Announcement blog | Virtuoso RF | Virtuoso Custom Placer | Electromagnetic analysis | Virtuoso | CLE | IC Release Blog | Custom IC Design | Virtuoso Layout Suite | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL | clarity
Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part IV

By Kabir | 9 Dec 2019

This is the fourth blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. This part highlights how EM analysis in Virtuoso is compared with other third-party tools in terms of accuracy, performance, capacity, memory consumption, and usability.

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AXIEM | SiP | ICADVM18.1 | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF | Package Design in Virtuoso | Electromagnetic analysis | RF design | method of moments | Finite Element Method | Layout Editing | Allegro | clarity
Virtuosity: Sharing Expressions between Pre- and Post-Layout Simulations

By Arja H | 26 Nov 2019

This has been an age old problem, you extract your design and get a DSPF file, then you want to run simulation in Virtuoso ADE Assembler, or Virtuoso ADE Explorer, using that DSPF file, but you find that none of your expressions evaluate. That's because the design is flat in the DSPF file, plus the extractor probably added prefixes to devices, changed the finger delimiters and changed the case of nets etc. You probably...

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ADE Explorer | Rapid Adoption Kit | DSPF | ADE | postlayout | Custom IC Design | ADE Assembler

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