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  • Parula
    Virtuoso Video Diary: Knowledge Booster - 5G mmWave Handset System Design
    By Parula | 8 Apr 2021
    In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz.
    0 Comments
    Tags:
    training | Cadence training | digital badges | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Custom IC Design | online training | Custom IC
  • Amit Sanadhya
    Virtuoso Video Diary: Incremental Simulations with Enhanced Reference Histories and New Merge Histories Feature
    By Amit Sanadhya | 5 Apr 2021
    Gone are the days of exporting results from multiple interactive runs and combining them into Excel spreadsheets for analysis. The new Reference Histories and Merge Histories flows address all these concerns. Click here to know more.
    0 Comments
    Tags:
    Analog Design Environment | ICADVM18.1 | Analog Design Environment | Virtuosity | Virtuoso Video Diary | Custom IC | IC6.1.8 | Assembler | ADE Assembler
  • Stefan Wuensche
    Spectre Tech Tips: Detecting Leakage Path Current Hotspots
    By Stefan Wuensche | 28 Mar 2021
    In circuit design, wrong connectivity may cause undesired leakage paths that may result in current hotspots. These current hotspots can be quickly identified with Spectre’s dynamic design checks. This blog describes how to use the Spectre design checks to identify the root cause of leakage path current hotspots.
    0 Comments
    Tags:
    Dynamic design checks | Spectre design checks | leakage path detection | Spectre | dyn_dcpath | dyn_subcktpwr
  • YaswanthSai D
    Virtuoso Video Diary: Tabular Graph in Virtuoso Visualization and Analysis XL
    By YaswanthSai D | 25 Mar 2021
    Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis XL to analyze waveform data. Click here to know more.
    0 Comments
    Tags:
    Analog Design Environment | ViVa-XL | custom/analog | ADE Explorer | Analog Simulation | ADE | Virtuoso | ViVA | Virtuosity | Custom IC Design | ADE Assembler
  • Virtuoso Release Team
    Virtuoso ICADVM20.1 ISR17 and IC6.1.8 ISR17 Now Available
    By Virtuoso Release Team | 23 Mar 2021
    The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for download.
    0 Comments
    Tags:
    Cadence blogs | ADE Explorer | cadence | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso Analog Design Environment | ICADVM20.1 | IC Release Blog | Clarity 3D Solver | Custom IC Design | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | Custom IC | ADE Verifier | IC6.1.8 | ADE Assembler
  • jgrad
    Virtuoso Meets Maxwell: How to Simulate an RF Block with Passive and Active Devices in EMX Planar 3D Solver?
    By jgrad | 16 Mar 2021
    Do you work with RF designs that contain both active and passive devices? Have you been running electromagnetic simulations for those designs by making a copy of the design and removing active devices? So you have not explored the advanced full-cellview extraction feature yet. Read this blog to know more..
    0 Comments
    Tags:
    AXIEM | VLS EXL | EM Solver | Virtuoso Meets Maxwell | Electromagnetic analysis | black boxing | Virtuoso | EMX | ICADVM20.1 | Clarity 3D Solver | Virtuoso Layout Suite EXL
  • Parula
    Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 6
    By Parula | 10 Mar 2021
    In this blog. we would like to let you know the information on how to achieve complete full-chip DRC signoff on advanced-node designs and efficiently run multiple DRC signoff iterations.
    0 Comments
    Tags:
    blended | Pegasus Verification System | ERC | pegasus | DRC | LVS | training | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Cadence Education Services | PVS | Custom IC Design | online training | Custom IC
  • scottd
    Virtuoso Meets Maxwell: EMX—Industry-Leading EM Solver for RFICs
    By scottd | 8 Mar 2021
    Hi all, this is my first blog for the Virtuoso Meets Maxwell series. It builds on the Virtuoso Meets Maxwell 2021 introduction blog. Today I get to discuss one of my favorite topics, electromagnetic (EM) analysis of RFICs using Cadence EMX Planar 3D Solver.
    0 Comments
    Tags:
    RFIC | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF Solution | Electromagnetic analysis | EMX | ICADVM20.1 | Custom IC Design
  • Huiling Xiao
    Spectre Tech Tips: Introducing Spectre XDP-HB (Distributed HB)
    By Huiling Xiao | 26 Feb 2021
    Spectre XDP-HB was released in the SPECTRE 20.1 base release as part of the new Spectre X-RF simulation technology. Spectre XDP-HB uses a highly distributed multi-machine multi-core simulation technology to perform HB and HB small-signal analyses. In this blog, we introduce the Spectre XDP-HB technology.
    0 Comments
    Tags:
    Spectre RF | Spectre XDP-HB | Spectre X-RF | Spectre X distributed simulation
  • colint
    Virtuosity: Design, Plan, and Analysis - The 3 Sides Of A Coin, Episode 2
    By colint | 26 Feb 2021
    Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.
    0 Comments
    Tags:
    Congestion Analysis | Cadence blogs | Virtuoso Layout EXL | Floorplanning | Virtuosity | ICADVM20.1 | dpa | Pin Optimization | pin planning | Custom IC Design | Virtuoso Layout Suite | Design Planning and Analysis
  • Claudia Roesch
    Virtuoso Meets Maxwell: Virtuoso RF Solution—The Flow Revolution Enters the Next Level
    By Claudia Roesch | 24 Feb 2021
    In many ways 2020 was an exceptional year with extraordinary challenges for all of us. Despite the unusual circumstances of a global pandemic, it was an exciting year with lot of product innovation that lies behind. To start with the Virtuoso Meets Maxwell series in 2021, let’s take a moment to look back at what we have achieved since the inception of the Virtuoso RF Solution.
    0 Comments
    Tags:
    5G | IMS | integrand | SiP | pegusas | Virtuoso Overture | VRF | Celcius | awr | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF | Allegro Package Designer Plus | EMX | AWR AXIEM | RF design | SiP Layout Option | ICADVM20.1 | Sigrity | Quantus | Clarity 3D Solver | Custom IC Design | Allegro | VMM
  • Sucharita
    Virtuoso Video Diary: Performance Diagnostic Tool – An MRI Scanner for Virtuoso
    By Sucharita | 11 Feb 2021
    You can now use the Performance Diagnostic tool in the Virtuoso custom IC design platform to diagnose issues that might be causing your system to slowdown or freeze. Click here to know more.
    0 Comments
    Tags:
    performance diagnosis | Virtuoso | performance diagnostic | ICADVM20.1 | Custom IC Design | Custom IC | Virtuoso scanner
  • Parula
    Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 5
    By Parula | 4 Feb 2021
    Continuing our momentum with the Knowledge Booster blogs in the year 2021 , this blog informs you how to overcome DC Convergence issues and errors for a Spectre Simulation by modifying associated parameters.
    0 Comments
    Tags:
    blended | Spectre DC | Spectre Pro | training | digital badges | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Cadence Education Services | Custom IC Design | online training
  • Virtuoso Release Team
    Virtuoso ICADVM20.1 ISR16 and IC6.1.8 ISR16 Now Available
    By Virtuoso Release Team | 3 Feb 2021
    The ICADVM20.1 ISR16 and IC6.1.8 ISR16 production releases are now available for download.
    0 Comments
    Tags:
    Cadence blogs | ADE Explorer | cadence | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso Visualization and Analysis XL | Virtuoso Analog Design Environment | ICADVM20.1 | IC Release Blog | Clarity 3D Solver | Custom IC Design | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | Custom IC | ADE Verifier | IC6.1.8 | ADE Assembler
  • Stefan Wuensche
    Spectre Tech Tips: Using Spectre X for RF Analyses
    By Stefan Wuensche | 29 Jan 2021
    In the Spectre 20.1 base release at the end of September 2020, we released Spectre X-RF. The Spectre X-RF technology integrates the Spectre X engine into Spectre’s RF analyses. In this blog, we introduce the Spectre X-RF technology.
    0 Comments
    Tags:
    +xdp | +preset | Spectre X-RF | spectre x | Spectre X distributed simulation | Spectre X Simulator
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire – Looking Back and beyond!
    By Team ADE Verifier | 28 Jan 2021
    Have you missed out on any of the In the Line of Veri-Fire blogs? Here's your chance to fix it...
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | custom/analog | Analog Simulation | verification plan | analog | ADE | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | cadenceblogs | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | ADE Assembler | verification
  • Pallabi R
    Virtuosity: Moving Along the Least-Resistive Path in Voltus-Fi
    By Pallabi R | 16 Dec 2020
    Do you want to know how discovering the path of least resistance for the devices of your design much ahead of your power planning can make your life easier? Then go ahead and read the blog.
    0 Comments
    Tags:
    Voltus-Fi | electromigration | EMIR Analysis | power grid | Voltus-Fi-XL | Virtuoso | voltage drop | ICADVM20.1 | LRP | Custom IC Design | Custom IC | IC6.1.8
  • FredIvar
    Spectre Tech Tips: Increasing Performance and Capacity Using Spectre X Distributed Simulation
    By FredIvar | 15 Dec 2020
    The Spectre X distributed simulation is an extension to the multithreaded simulation where cores from different machines are used. The Spectre X distributed simulation provides access to more cores, thus increasing the performance and capacity and providing more value for large designs.
    0 Comments
    Tags:
    multithreaded simulation | ppn | Multi-Core | XDP | spectre x | Spectre X distributed simulation | multithreaded
  • Claudia Roesch
    Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy
    By Claudia Roesch | 15 Dec 2020
    Fast growing markets like 5G, automotive, and IoT are driving the development of advanced semiconductor technologies and silicon-integrated circuits. In particular, the high cutoff frequency of advanced CMOS and Silicon-Germanium (SiGe) bipolar devices allow the integration of millimeter-wave circuits with good high-frequency performance and high integration level at moderate mask costs.
    0 Comments
    Tags:
    Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF Solution | Electromagnetic analysis | EMX | Quantus Extraction Solution | RF design | ICADVM20.1 | Custom IC Design | VMM
  • Tyler
    Virtuoso Meets Maxwell: Defining Standard Library Components
    By Tyler | 7 Dec 2020
    The Allegro Package Designer product line offers everything needed to take an IC package from idea to manufactured part, and this is where the journey takes us today. It is available from your Virtuoso environment as Virtuoso MultiTech Framework.
    0 Comments
    Tags:
    Libimport | Unified Library | JEDEC | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso RF | Virtuoso MultiTech | Package Design in Virtuoso | Allegro Package Designer Plus | BGA | Allegro Package Designer | die | Virtuoso | ICADVM20.1 | Cadence SiP Layout | Custom IC Design | Custom IC | Allegro | VMM
  • bsachin
    Virtuosity: Conserve Power—Verifying a Design Using Conformal Low Power
    By bsachin | 3 Dec 2020
    If you have been following the Conserve Power blog series, you will probably have an idea of what next I am going to talk about. Yes, we have now reached the finale, the last and the most intriguing piece in the entire story. It is the formal verification and sign-off of the IP to make it ready to be integrated into an SoC.
    0 Comments
    Tags:
    Virtuoso Schematic Editor | virtuoso power manager | clp | Conformal Low Power | VPM | Supply States | 1801 | setup | Virtuoso | Virtuosity | ICADVM20.1 | UPF | IEEE | mixed-signal design | Liberty | Custom IC Design | power domains
  • Parula
    Virtuoso Video Diary: Why Split Symbols?
    By Parula | 3 Dec 2020
    A blog that tells you about why splitting up blocks has now become a useful feature in more complex designs and advanced technology.
    0 Comments
    Tags:
    split symbols | Virtuoso Schematic Editor | custom/analog | splits | Virtuoso | ICADVM20.1 | create split symbols | create splits | Custom IC
  • KomalJohar
    Virtuosity: Our Design Thinking Approach to Enhance User Interfaces across Cadence Products
    By KomalJohar | 2 Dec 2020
    Read our story about how teams across Cadence, diligently work towards enhancing your experience by continuously improving the quality of user interfaces from a usability aspect.
    0 Comments
    Tags:
    virtuoso power manager | EMIR Analysis | cadence | reliability options | usability | reliability analysis | Custom IC
  • Parula
    Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 4
    By Parula | 24 Nov 2020
    We live in a complex world where it is essential to use and combine tools and platforms as efficiently as possible with all available features. In this blog, we are happy to show you how easy it can be to get best results using the Spectre Simulation Platform and its corresponding options.
    0 Comments
    Tags:
    blended | Spectre RF | training | digital badges | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Cadence Education Services | Custom IC Design | online training
  • Virtuoso Release Team
    Virtuoso ICADVM20.1 ISR15 and IC6.1.8 ISR15 Now Available
    By Virtuoso Release Team | 23 Nov 2020
    The IC6.1.8 ISR15 and ICADVM20.1 ISR15 production releases are now available for download.
    0 Comments
    Tags:
    Analog Design Environment | Cadence blogs | ADE Explorer | cadence | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso Visualization and Analysis XL | Virtuoso | ICADVM20.1 | IC Release Blog | Custom IC Design | Virtuoso Layout Suite EXL | Custom IC | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
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