Analog/Custom Design (Analog/Custom design) - Cadence Blogs

Running Post-Layout Mixed-Signal Simulations with a More Complex Configuration

Cadence^®︎ Spectre^®︎ With the DSPF-in-the-middle feature, designers can easily set up complex configurations in the Hierarchy Editor (HED) and run a post-layout mixed-signal simulation with just a few clicks. View this blog to know more.

Qingyu Lin 19 Jan 2023 • 2 min read

AMS , AMS Designer , Start Your Engines , DSPF , Mixed-Signal , AMS simulation , Custom IC Design

Spectre Tech Tips: Dynamically Changing Spectre X Solver Settings

Spectre APS supports dynamically changing errpreset or reltol during a transient simulation. This feature is used by advanced Spectre users to optimize simulation performance when different time windows of the simulation have different accuracy requirements. The use model for this feature is the following:

tr1 tran stop=10u param=errpreset param_vec=[0 liberal 2u moderate]

The errpreset parameter is not available in…

Stefan Wuensche 18 Jan 2023 • 3 min read

Circuit simulation , spectre x , SPICE

Start Your Engines: Mixed-Signal Behavioral Modeling Review and Coaching

AHDL Linter utility checks analog behavioral code for modules and highlights the possible mistakes in your code that could slow down a Spectre AMS Designer simulation. It also suggests the code changes you can apply. View this blog to know more.

Andre Baguenie 10 Jan 2023 • 5 min read

AMS , ADE Explorer , AMS Designer , mixed signal solution , Mixed-Signal , Virtuoso Analog Design Environment , analog/mixed-signal , mixed-signal solution , AMS Verification , mixed-signal verification , ADE Assembler

Knowledge Booster Training Bytes – Place and Route Using Virtuoso Placer

Do you know you can do placement of the devices by using Virtuoso Placer, which helps in doing placement that is Correct by Construction? Check out this blog to know more.

Sandeep O 20 Dec 2022 • 6 min read

Advanced Node , Virtuoso Placer , analog/mixed-signal , Custom IC Design , Virtuoso Layout Suite EXL , Row-Based Placement

Virtuosity: Annotating Scalar Outputs for Single-Point Simulation in Virtuoso Visualization and Analysis XL

Can scalar outputs for single-point simulation be annotated in the graph window of Virtuoso Visualization and Analysis XL? Yes, now, you can! How? Read through this blog to know more.

Udit Rajput 15 Dec 2022 • 3 min read

annotation , Scalar Outputs Annotation , ADE Explorer , Summary Label , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , ViVA , Virtuosity , Single Point Simulation , ISR26 , Scalar Ouputs , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal Modeling?

Do you know you can speed up analog or mixed-signal simulations with digital mixed signal technology? View this blog to know more.

Jaseem TM 13 Dec 2022 • 9 min read

real number modeling , AMS , AMS Designer , training , DMS , training bytes , Spectre , RNM , AMS simulation , xcelium , Modeling , wreal , Custom IC Design , wreal Model , AMS Verification , vams

Virtuoso Meets Maxwell: Are You Telling Me I Can Auto-Generate a Package Schematic From a Package Layout?

Yes, you heard that right! You can now auto-generate a package schematic from a package layout with a snap of a finger! With Virtuoso RF Solution, there are all kinds of automations that allow you to have a connectivity-driven design. You can verify the connectivity by the top-level analog simulation and functional verification to make sure your netlist and results are within your expectation. In addition, verify your…

VRF Knight 12 Dec 2022 • 4 min read

IC Packaging , Footprint , VRF , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso MultiTech , Package Design in Virtuoso , Virtuoso , RF design

Knowledge Booster Training Bytes - Enhance Layout Productivity with Virtuoso CLE

Do you know you can work in parallel with Virtuoso Concurrent Layout? Click here to know more.

rbaby 7 Dec 2022 • 6 min read

concurrent layout editing , Knowledge Booster , Virtuoso , CLE , ICADVM20.1

Virtuoso ICADVM20.1 ISR29 and IC6.1.8 ISR29 Now Available

The ICADVM20.1 ISR29 and IC6.1.8 ISR29 production releases are now available for download.

Virtuoso Release Team 7 Dec 2022 • 2 min read

Cadence blogs , ADE Explorer , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Analog Design Environment , Virtuoso , ViVA , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , Cadence Community , ADE Assembler

Virtuoso Meets Maxwell: Top of the PoPs! By Exporting the Package Footprint in Virtuoso

I’m back again, it has been a while, but guess what… I have a lot of goodies to share with you. Since last time I posted a blog, our Virtuoso System Design solutions have gone through a lot of enhancements, and more automations have been accomplished. You may already have read our blog, Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution, which covers how you can bring your existing SiP design…

VRF Knight 29 Nov 2022 • 5 min read

IC Packaging , Footprint , VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Package Design in Virtuoso , Virtuoso , RF design

Virtuosity: Custom IC Design Flow/Methodology - Post-Layout Circuit Simulation and GDSII Generation

Read this blog for getting an overview of post-layout circuit simulation & GDSII generation.

Ashish Patni 23 Nov 2022 • 6 min read

post-layout simulation , Analog Design Environment , Cadence blogs , ADE Explorer , DSPF , Virtuoso Analog Design Environment , Spectre , ICADVM20.1 , Custom IC Design , IC6.1.8 , ADE Assembler

Spectre Tech Tips: How to Migrate to Spectre X?

Are you still using Spectre APS and you want to migrate to Spectre X? If yes, this post will guide you how to move to Spectre X and will also answer your questions about the preset modes mapping, postlayout circuits, and the impact of Spectre APS fine-tuned netlist options on Spectre X performance.

Moustafa Moham 31 Oct 2022 • 5 min read

spectre aps , Spectre , analog design , spectre x , Spectre X Simulator , verification

Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Design Capture and Packaging (DCP) utility lets you isolate, capture and package the source files easily from your Spectre AMS Designer testbench and immediately rerun it in the same or a different environment. Check out this blog to know more.

Andre Baguenie 20 Oct 2022 • 5 min read

mixed signal design , AMS Designer , AMSD , Start Your Engines , Mixed-Signal , Design Capture , Cadence Community

Virtuoso ICADVM20.1 ISR28 and IC6.1.8 ISR28 Now Available

The ICADVM20.1 ISR28 and IC6.1.8 ISR28 production releases are now available for download.

Virtuoso Release Team 12 Oct 2022 • 2 min read

Analog Design Environment , Cadence blogs , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Spectre Tech Tips: Dynamic Power Density Circuit Check

To ensure an improved reliability and lifetime of devices, the circuit designers need to optimize the power consumption of the devices. This blog introduces a new dynamic check that you can use to identify the devices with large power density values.

Amaninder 30 Sep 2022 • 3 min read

spectre aps , Spectre 21.1 , Dynamic Checks , Dynamic design checks , Spectre Circuit Simulator , Spectre , spectre x

Knowledge Booster Training Bytes - Virtuoso Pin-To-Trunk Routing

This blog helps in demonstrating the use of Pin to trunk routing style which helps in enhancing the layout experience.

Sandhya P S 28 Sep 2022 • 4 min read

Virtuosity: Driving Super-efficient Chip Design with Voltus-XFi Custom Power Integrity Solution

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.

Joy Han 30 Aug 2022 • 5 min read

Voltus-XFi , EMIR Analysis , featured , EMIR Simulation , EMIR Extraction , Virtuoso Analog Design Environment , Custom IC Design

Virtuosity: Synergize with CLE - Work Concurrently Across Geographies

Concurrent Layout Editing enables more than one designer to work in a hierarchy at the same time. Check out this blog to know more.

Sucharita 29 Aug 2022 • 7 min read

concurrent layout editing , Virtuoso , Virtuosity , CLE , ICADVM20.1 , Synergize with CLE

Virtuoso ICADVM20.1 ISR27 and IC6.1.8 ISR27 Now Available

The ICADVM20.1 ISR27 and IC6.1.8 ISR27 production releases are now available for download.

Virtuoso Release Team 24 Aug 2022 • 2 min read

Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , Virtuoso Analog Design Environment , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Virtuoso Meets Maxwell: Completing the Virtuoso RF Solution Assisted Flow

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this…

kgjudd 16 Aug 2022 • 6 min read

Layout SiP , Viltuoso MultiTech Framework , featured , Enablement GUI , VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , VMT , Allegro Package Designer Plus , Assisted Export , System Design Environment , fully assisted , SiP Layout Option , ICADVM20.1 , Assisted Flows , Assisted Import

Knowledge Booster Training Bytes - Virtuoso Visualization and Analysis XL

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.

Udit Rajput 10 Aug 2022 • 4 min read

blended , blended training , ADE Explorer , Virtuoso Visualization and Analysis XL , learning , training , knowledge resource kit , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Cadence Learning and Support portal , Custom IC Design , online training , Custom IC , ADE Assembler

Virtuosity: Custom IC Design Flow/Methodology - Circuit Physical Verification & Parasitic Extraction

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.

Ashish Patni 29 Jul 2022 • 6 min read

design rule violations , Extraction , Layout versus schematic , Physical Verification System (PVS) , Virtuoso , Quantus Extraction Solution , PVS , Custom IC Design , parasitics

Start Your Engines: An Innovative and Efficient Approach to Debug Interface Elements with SimVision MS

This blog introduces you to an efficient way to debug interface elements or connect modules in a mixed-signal simulation.

Andre Baguenie 28 Jul 2022 • 4 min read

connect modules , mixed signal design , featured , interface elements , AMS Designer , mixed-signal simulation , Virtuoso , SimVision-MS

Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides support to the Voltus-XFi Custom Power Integrity Solution.

Stefan Wuensche 22 Jul 2022 • 3 min read

Spectre X EMIR , Voltus-Fi-XL , Virtuoso Analog Design Environment , Spectre X distributed simulation , Spectre X Simulator

Virtuoso ICADVM20.1 ISR26 and IC6.1.8 ISR26 Now Available

The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for download.

Virtuoso Release Team 8 Jul 2022 • 2 min read

Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , Virtuoso Analog Design Environment , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

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