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Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

By Virtuoso Release Team | 17 Jun 2019

The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download.

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ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | Interactive and Assisted Routing | Virtuoso RF | ADE | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

By Parula | 10 Jun 2019

The first blog of the series talks about features that are not new but capabilities that are ground-breaking and can support your device-level routing requirements for advanced nodes with the use of the Finish Trunk command.

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Trunk Trimming | Pin to Trunk | Create Wire | space-based router | Virtuoso Space-based Router | layout XL | Layout Suite | Trunk Extending | Layout L | Finish Trunk | EM Trunk Optimization | Custom IC Design
Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations?

By NamrataM | 7 Jun 2019

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind of feature called point-to-point info balloons. These info balloons provide critical information that you would find handy while working with critical nets to resolve EM violations. Read more...

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ICADV12.3 | ICADVM18.1 | EM/IR | electrically-aware design flow | Layout EAD | Virtuoso Layout EXL | Virtuoso | IC6.1.7 | IC6.1.8 | Virtuoso Layout Suite XL
Spectre Tech Tips: Spectre APS Save Overview - Part 1

By Stefan Wuensche | 29 May 2019

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated...

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save statement | spectre aps | nestlvl | pwr=subckt | save=selected | save=lvlpub | save=allpub | currents=all | subcktprobelvl | Spectre | currents=selected | pwr=devices | Spectre Waveform Writing | pwr=total | pwr=all | save option
Virtuoso Video Diary: Comparing Multiple Tests and Sharing Settings

By Yuan Li | 21 May 2019

Have you been in the situation where you want to change a particular simulation setting in several of your tests in Virtuoso ADE Assembler? This can be a tedious process as you have to figure out which tests have that setting and what it is set to, then you have to go in to each test in turn to change it. From IC6.1.8 ISR3/ICADVM18.1 ISR3, we have added a tool to do just that. You can compare all the simulator settings...

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Analog Design Environment | ICADVM18.1 | ADE | simulator options | Virtuoso Video Diary | Custom IC Design | IC6.1.8 | Assembler | ADE Assembler
Virtuoso Video Diary: The Next Big Thing — ADE Verifier Teams Up with Cadence vManager

By Rashmi G | 16 May 2019

Need to perform functional verification of a mixed-signal design? Using the connection between Verifier and vManager, analog and digital engineers get to work together with two different tools using the same data. A single view allows a project manager to look up all the results together and the engineers to sign off the project. You have fulfilled traceability and tracking of results for internationally acknowledged...

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verifier | ICADVM18.1 | Functional Verification | Formalized Verification | vPlan | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso Video Diary | mixed-signal design | Custom IC Design | ADE Verifier | IC6.1.8 | vManager | verification
Virtuosity: Did My Checks Pass or Did They Not Run?

By AdityaMainkar | 14 May 2019

If you've ever tried to run the Checks/Asserts flow in Virtuoso ADE Assembler and Virtuoso ADE Explorer, you might have found it difficult to distinguish between “all checks passed” and “no checks were run”. In both the cases, the message “No violations” was displayed. Now, in IC6.1.8 ISR3 and ICADVM18.1 ISR3, you can differentiate when checks were not run or if they were ignored with syntax errors.

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ADE Explorer | Virtuosity | Custom IC Design | ADE Assembler
Virtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment

By Arja H | 9 May 2019

Have you ever wanted to sweep DSPF files across corners, plot terminal current and voltage and ensure that the simulator name maps correctly to the schematic name in Virtuoso ADE Assembler and Virtuoso ADE Explorer? If so, IC6.1.8 ISR3/ICADVM12.8 ISR3 will be the release for you.

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ADE Explorer | post-layout | DSPF | Virtuoso Analog Design Environment | postlayout | Virtuosity | ADE Assembler
Virtuoso Video Diary: What's New in Reliability Setup

By Udit Rajput | 7 May 2019

Read this blog to know about the enhancements made to the reliability options form and to the overall reliability setup

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stress analysis | Analog Design Environment | relxpert | ICADVM18.1 | ADE Explorer | MMSIM | ADE XL | ADE | ISR3 | reliability options | Virtuoso Analog Design Environment | Spectre | ADE-XL | Virtuosity | Virtuoso Video Diary | aging | reliability analysis | Custom IC Design | IC6.1.8 | reliability | ADE Assembler
Virtuosity: Filtering Plots!

By Arja H | 2 May 2019

If you're a regular reader of the Virtuosity series, you'll have seen a few blogs recently on filtering in Virtuoso ADE Assembler and Virtuoso ADE Explorer. Well, we've extended this capability and the same filters are now available for your plots in Virtuoso Visualization and Analysis.

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ADE Explorer | plotting | plot | Filtering | ViVA | Virtuosity | ADE Blog Series | Custom IC Design | ADE Assembler
Spectre Tech Tips: Measuring Noise in Digital Circuits

By RF Rich | 30 Apr 2019

As a designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Sometimes, you use Spectre to measure noise in digital circuits. Are you confused which method to use for noise measurement since Spectre provides different methods for measuring noise? This blog discusses the different noise measuring methods and explains why they may provide different results.

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edge delay | timeaverage | ADE Explorer | sampled jitter | sampled | pnoise | spectreRF | Virtuoso | direct plot form | full spectrum pnoise | edge phase noise | sampled phase | edge crossing
Virtuoso Video Diary: Creating and Previewing Stimuli

By Arja H | 30 Apr 2019

If you've ever tried to add stimuli to your design using the Stimuli form, you'll agree it needed a revamp. Most people tend to use a vsource or isource component or a file to set up stimuli. But wouldn't it be nice if you could create a library of stimuli to share between designs, and to preview your stimuli waveforms without having to simulate the entire circuit. Well in Virtuoso ADE Assembler and Virtuoso ADE Explorer...

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ADE Explorer | stimuli form | stimuli | Virtuoso Analog Design Environment | ViVA | Virtuosity | ADE Blog Series | Custom IC Design | ADE Assembler | Stimuli Assignment form
Virtuoso IC6.1.8 ISR3 and ICADVM18.1 ISR3 Now Available

By Virtuoso Release Team | 30 Apr 2019

The IC6.1.8 ISR3 and ICADVM18.1 ISR3 production releases are now available for download.

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TAGS:

ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | Interactive and Assisted Routing | Virtuoso RF | ADE | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Cdsenv Editor – Simplifying Virtuoso Customization

By Sucharita | 26 Apr 2019

Customization is the need of the day. From picking an ice cream flavor to outfitting a premium car, we all want a product customized according to our needs and expectations. Virtuoso users are no exception. Yes, you can customize many features in the Virtuoso environment by changing values of variables that control these features. These variables stored across various .cdsenv files are shipped with each Virtuoso...

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Cdsenv Editor | Virtuoso Environment Variables | ICADVM18.1 | cdsenv | cdsenv variables | Virtuosity | Virtuoso Design Environment | Custom IC Design | IC6.1.8
Virtuosity: Spring-Cleaned Virtuoso Doc Closet

By Rishu Misri Jaggi | 19 Apr 2019

Most of us know how a spring-cleaned house can look like. But, do you know how the spring-cleaned Virtuoso documentation closet could look like?

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legato | Virtuoso Schematic Editor | ICADVM18.1 | Routing | ADE L | Virtuoso RF | Layout EXL | layout XL | Virtuoso | Layout L | Cadence Help | Virtuoso Doc | Virtuoso Design Environment | Virtuoso Layout Suite | IC6.1.8
Virtuoso Video Diary: Tune In to the MPT Video Channel

By KomalJohar | 9 Apr 2019

Tune In to the MPT Video Channel to check out a wide range of features easily accessible through the MPT toolbar.

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ICADVM18.1 | video | Layout | Virtuoso | Virtuoso Video Diary | advanced nodes | multi-patterning technology | Custom IC
Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts

By NamrataM | 4 Apr 2019

How about checking your designs for electromigration (EM) compliance before creating layouts? Why not? Read further to know more ...

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EAD | electromigration | ICADVM18.1 | electrically-aware design flow | Virtuoso electrically-aware design flow | EM | Virtuoso Layout Suite | IC6.1.8
Spectre Tech Tips: Spectre Assert and Design Check Overview

By Stefan Wuensche | 28 Mar 2019

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Besides performing Spectre simulations to verify that the design works as expected, you may want to check your design for critical device conditions, or typical design problems, such as high impedance nodes, leakage paths, or power consumption problems. This blog provides an overview of the Spectre...

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spectre aps | Circuit simulation | asserts | Spectre | SOA Checks | Design Checks
Virtuoso Video Diary: What Makes EM/IR Analysis A Significant Sign-Off Step?

By Vani V | 20 Mar 2019

This blog describes the EM and IR analyses in Virtuoso ADE as a design sign-off step. It take you to the videos demonstarting the analyses and how to set them up.

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ADE Explorer | EM/IR | power integrity | IC layout | ADE | Virtuoso Analog Design Environment | Virtuoso Video Diary | sign-off | Custom IC Design | Custom IC | IC design | EMIR
Virtuoso IC6.1.8 ISR2 and ICADVM18.1 ISR2 Now Available

By Virtuoso Release Team | 19 Mar 2019

The IC6.1.8 ISR2 and ICADVM18.1 ISR2 production releases are now available for download.

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TAGS:

ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | ADE | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Maestro Plotting Templates

By Chandrika Durbha | 18 Mar 2019

Waveforms, plots, graphs, measurements, markers... are all a part and parcel of any circuit designer’s everyday life. For a regular user of Virtuoso ADE Explorer or Virtuoso ADE Assembler and the ADE waveform window, packaged with IC6.1.6/IC6.1.7 release, it was a common task to redo the measurements on plots every time the plot was refreshed or when a new simulation was set up. How about a feature that lets you save...

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ICADVM18.1 | ADE Explorer | ViVA | plotting templates | maestro plotting templates | Custom IC Design | IC6.1.8 | ADE Assembler
Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis

By Arja H | 8 Mar 2019

Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with the applied stimuli, it was necessary to run the simulations using both digital and analog solvers. This could be a time-consuming process. However, now you can read in the digital stimuli files directly into Cadence Virtuoso Visualization and Analysis, the ADE waveform window. In addition, you can plot the analog waveforms using the stimuli...

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VCD | Analog Design Environment | ICADVM18.1 | analog | ViVA | Virtuosity | analog stimuli | IC6.1.8 | vector
Virtuosity: Identifying Those Traces

By AdityaMainkar | 6 Mar 2019

With the ever-increasing number of simulations required to be run these days, the sheer number of plots can be overwhelming and it can be difficult to figure out which Cadence Virtuoso ADE XL, Virtuoso ADE Assembler or Virtuoso ADE Explorer history, test or corner each plot belongs to. To help with this, from IC.6.1.8/ICADVM18.1 Virtuoso Visualization and Analysis we have made identifying and comparing traces across...

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Explorer | plotting | ADE XL | Virtuoso | Analog Design Environment | ViVA | ADE-XL | Virtuosity | Assembler
Spectre Tech Tips: Device Aging? Yes, even Silicon wears out

By Moustafa Moham | 28 Feb 2019

While most of us would like our electronic gadgets to last forever, the reality is that these gadgets have a lifetime. Most of the time, the lifetime of devices is limited by either mechanical (switch, relay), or thermal (fuse, capacitor) failures. However, as microchips designed in advanced technologies become more pervasive, the lifetime of microchips has become an additional issue. Several effects contribute to...

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stress analysis | TDDB | PBTI | native reliability analysis | Spectre | reliability analysis | HCI | NBTI | reliability
Virtuosity: New Flexible Subwindows

By Arja H | 26 Feb 2019

Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or subwindow. Subwindows allow you to see plots from different analyses side by side. Until IC6.1.8/ICADVM18.1, the subwindows were not very flexible. Now, we've improved these so that you can choose any grid layout of subwindows up to a 6x8 grid. In addition, you can resize the subwindows easily and move them around. These subwindow configurations...

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ICADVM18.1 | subwindows | waveforms | Virtuoso Analog Design Environment | ViVA | Virtuosity | plotting templates | Custom IC Design | IC6.1.8

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