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Virtuosity: An Introduction to Modgen

By Aneesh Shastry | 22 Aug 2019

This blog provides an overview of Virtuoso Module Generator, also referred to as Modgen. Modgen allows you to create highly matched arrays of devices directly on the canvas. Virtuoso provides you with both GUI options and SKILL APIs to create and customize Modgens.

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Modgen On Canvas | module generation | Custom IC Design | modgens | Virtuoso Layout Suite | Virtuoso Layout Suite XL
SPECTRE 19.1 Release Now Available

By SpectreReleaseTeam | 21 Aug 2019

The SPECTRE 19.1 production release is now available for download.

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Dynamic Checks | Spectre Fault Analysis | SPECTRE 19.1 | Spectre X Simulator
Virtuoso Meets Maxwell: Here's All You Must Know to Create a TILP

By deeptig | 19 Aug 2019

Did you get a chance to look at the outstanding posts about Technology Independent Layout Pcell (TILP) in the Virtuoso Meets Maxwell series, TILP! What’s a TILP? and Export the Die? What Am I Exporting? To Where?? I am sure it would have been nearly impossible sometime ago to imagine a feature like this being offered in Virtuoso. Now, the Virtuoso RF Solution has brought the revolution by enabling you to create modules...

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ICADVM18.1 | Virtuoso New Design Platform | video | Virtuoso Meets Maxwell | Virtuoso RF | RF design | TILP | Custom IC Design | Virtuoso Layout Suite | technology
Virtuosity: Automated Device Placement and Routing - Grid Generation

By Sravasti | 15 Aug 2019

This blog, the third one in the Automated Device-Level Placement and Routing series, highlights the importance of following a gridded methodology for placement and routing. You'll see how the automated device-level layout flow lets you derive WSPs and row regions automatically, based on the device footprint, layers, and DRCs, with minimal user input.

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ICADVM18.1 | Automated Device-Level Placement and Routing | VPR | Automatic Placement | Advanced Node | Virtuoso Placer | Layout EXL | APR | Auto P&R | Virtuoso | Virtuosity | Virtuoso Placement | Custom IC
Virtuoso Video Diary: Stimuli with Variable Sweeps Videos and Rapid Adoption Kit

By Arja H | 9 Aug 2019

You're probably thinking, "wasn't there a recent blog on the new Stimuli Assignment form in ADE." Well yes, that's right, but we wanted to offer more functionality so from IC6.1.8 ISR4, we now have the ability to preview stimuli waveforms using swept variables. This will be really useful when defining your stimuli. There are a couple of other small usability changes too.

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ADE Explorer | stimuli form | stimuli | Virtuoso Analog Design Environment | ViVA | Virtuosity | Virtuoso Video Diary | ADE Blog Series | Custom IC Design | ADE Assembler | Stimuli Assignment form
Virtuosity: Automated Device Placement and Routing - Identifying Device Groups and Topologies

By Sravasti | 1 Aug 2019

This blog highlights the importance of identifying device groups and topologies in the fully automated device-level placement and routing flow in Virtuoso.

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ICADVM18.1 | Automated Device-Level Placement and Routing | VPR | Automatic Placement | Advanced Node | Virtuoso Placer | Layout EXL | APR | Auto P&R | Virtuoso | Virtuosity | Virtuoso Placement | Custom IC Design
Virtuoso Meets Maxwell: Edit-in-Concert – A New Duet

By Priya Sriram | 30 Jul 2019

This blog highlights a video that demonstrates how to use the Edit-in-Concert mode to edit die packages and layouts. Edit-in-Concert, also referred to as Co-design, is a design editing mode in the Cadence Virtuoso RF Solution. In this mode, the fabrics in a system are superimposed. The current fabric is displayed in the foreground and is available for edit. The fabrics in the background serve as a guide for the design...

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ICADVM18.1 | Edit-in-Concert | EXL | VRF | Virtuoso RF | Virtuoso | Custom IC | Cusstom IC Design
Virtuoso IC6.1.8 ISR5 and ICADVM18.1 ISR5 Now Available

By Virtuoso Release Team | 30 Jul 2019

The IC6.1.8 ISR5 and ICADVM18.1 ISR5 production releases are now available for download.

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ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | Automated Device-Level Placement and Routing | Automatic Placement | Interactive and Assisted Routing | Virtuoso RF | ADE | Mixed-Signal | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8 | ADE Assembler
Spectre Tech Tips: Spectre Local Options

By Stefan Wuensche | 30 Jul 2019

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Years back, we introduced the Multi-Technology Simulation (MTS) solution that allows you to simulate multiple chips in a single Spectre run, with each chip using its own device models, temperature definitions, and technology scaling setups. In the MMSIM 15. 1 (October 2015) release, MTS was made...

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highvoltage | spectre aps | scale | skip | Spectre | reltol | scoped options | vrefgnd
Virtuosity: bindStrict or Not in Virtuoso in the Times of Chandrayaan 2

By Rishu Misri Jaggi | 24 Jul 2019

Really, can Virtuoso bind strict? And what does that mean? Read along to find out...

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Update Binding | ICADVM18.1 | Layout XL Environment Variables | cdsenv | Virtuoso | Check Against Source | bindStrict | Custom IC Design | Update Components And Nets | Binder | IC6.1.8 | Virtuoso Layout Suite XL | binding
Tales from DAC: MediaTek's Experience with Spectre X Simulator

By XTeam | 22 Jul 2019

MediaTek recently gave the new Spectre X Simulator a try, and they talked about their experiences with it at DAC 2019 in a presentation given by YY Chen in the Cadence Theater. Spoiler alert: they loved it. MediaTek is the fourth largest fabless IC design company in the world, and they’re ranked #1 in the voice assistant device, android tablet, and network connectivity markets, among others. They, like so many others...

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Cadence Theater | DAC 2019 | mediatek | spectre x
Virtuoso Meets Maxwell: Export the Die? What Am I Exporting? To Where?

By kgjudd | 22 Jul 2019

Here I come back with another episode of TILP of the Virtuoso Meets Maxwell series! In my earlier post "TILP! What's A TILP?", I introduced the concept of Technology Independent Layout Pcell (TILP). Today we are going to create a TILP, which is used in the package design, from a die.

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ICADVM18.1 | die export | Virtuoso Meets Maxwell | Virtuoso RF | die | Layout | Multitech | TILP | Custom IC Design | Virtuoso Layout Suite
Virtuosity: Introducing Automated Device Placement and Routing in Virtuoso

By Sravasti | 18 Jul 2019

This blog provides an overview of the fully automated device-level placement and routing solution, which is available at advanced nodes.

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ICADVM18.1 | Automated Device-Level Placement and Routing | VPR | Automatic Placement | Advanced Node | Layout EXL | APR | Auto P&R | Virtuoso | Virtuosity | Virtuoso Placement | Custom IC Design
Tales from DAC: The New Spectre Simulator Is Here!

By XTeam | 17 Jul 2019

If you’re doing circuit simulation anywhere in the world, you’re probably already familiar with the Cadence Spectre® simulator. The Spectre simulator is an accurate and high-performance SPICE circuit simulator that has established itself as the golden reference analog simulation over many years of use by designers. Now, with smaller geometries and denser chip designs, requiring more performance and capacity, the Spectre...

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Functional Verification | DAC 2019 | Spectre | spectre x
Virtuoso Meets Maxwell: Learn Your Moves – We’re Doing an Edit-in-Concert

By Steve PDK Lee | 14 Jul 2019

This blog showcases the Edit-in-Concert technology available in the Cadence Virtuoso RF Solution, which lets designers view and edit die packages and their corresponding die layouts synchronously.

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Edit-in-Concert | Virtuoso Meets Maxwell | Advanced Node | Virtuoso RF | Virtuoso | Custom IC Design
Virtuosity: Device-Level Routing for Advanced Nodes – Using Generate Trunks

By Parula | 12 Jul 2019

The Trunk Generation feature is the founding piece that offers incremental productivity improvement with automation over Pin to Trunk, while still providing all the customizable options in the Pin to Trunk flow.

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Trunk generation | Interactive Routing | Pin to Trunk | ICADVM18.1 | Virtuoso Space-based Router | Layout EXL | Layout Suite | trunk creation | Virtuoso | Generate Trunk | EM Trunk Optimization | Custom IC Design | space based router | Virtuoso Layout Suite | Custom IC
Virtuoso Meets Maxwell: TILP! What’s a TILP?

By kgjudd | 1 Jul 2019

I have been breathing IC layout design for the last 38 years! Proliferating new Cadence products in the industry has been an enriching experience. Here I come to talk about yet another powerful invention, Virtuoso RF Solution and the underlying concepts. These concepts must be understood by designers who know package design but are new to the Virtuoso RF Solution. Or, the IC layout designers who are doing package design...

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PCells | Virtuoso Meets Maxwell | Virtuoso RF | Independent | Solution | Multitech | TILP | Custom IC Design | Virtuoso Layout Suite | technology
Spectre Tech Tips: Spectre APS Save Overview - Part 2

By Stefan Wuensche | 28 Jun 2019

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated...

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save statement | spectre aps | device terminal naming | subcktiprobes | device terminal calculation | ports | filter | time_window | exclude | depth | useprobes | subcktprobelvl | useterms | subckt | subcircuit terminal current calculation
Virtuoso Meets Maxwell: Virtuoso RF Solution - Revolution Begins with a Common Goal for One Flow

By michaelthompson | 25 Jun 2019

I am traveling home from the heart of the revolutionary Boston, Massachusetts, where I attended IMS 2019. It was indeed a fantastic show with a fitting location that has the history of inception of MIT Radiation Labs in early 1940s. These labs were renamed as Lincoln Labs in 1951. It was the birth of the modern microwave theory and design. Many of the 28-volume radiation lab series remain relevant even today with Samuel...

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SiP | VRF | Spectre RF | Virtuoso Meets Maxwell | Virtuoso RF | Virtuoso | System Design Environment | RF design | Custom IC Design | Custom IC | Allegro
Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

By Virtuoso Release Team | 17 Jun 2019

The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download.

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ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | Interactive and Assisted Routing | Virtuoso RF | ADE | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

By Parula | 10 Jun 2019

The first blog of the series talks about features that are not new but capabilities that are ground-breaking and can support your device-level routing requirements for advanced nodes with the use of the Finish Trunk command.

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Trunk Trimming | Pin to Trunk | Create Wire | space-based router | Virtuoso Space-based Router | layout XL | Layout Suite | Trunk Extending | Layout L | Finish Trunk | EM Trunk Optimization | Custom IC Design
Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations?

By NamrataM | 7 Jun 2019

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind of feature called point-to-point info balloons. These info balloons provide critical information that you would find handy while working with critical nets to resolve EM violations. Read more...

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ICADV12.3 | ICADVM18.1 | EM/IR | electrically-aware design flow | Layout EAD | Virtuoso Layout EXL | Virtuoso | IC6.1.7 | IC6.1.8 | Virtuoso Layout Suite XL
Spectre Tech Tips: Spectre APS Save Overview - Part 1

By Stefan Wuensche | 29 May 2019

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated...

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save statement | spectre aps | nestlvl | pwr=subckt | save=selected | save=lvlpub | save=allpub | currents=all | subcktprobelvl | Spectre | currents=selected | pwr=devices | Spectre Waveform Writing | pwr=total | pwr=all | save option
Virtuoso Video Diary: Comparing Multiple Tests and Sharing Settings

By Yuan Li | 21 May 2019

Have you been in the situation where you want to change a particular simulation setting in several of your tests in Virtuoso ADE Assembler? This can be a tedious process as you have to figure out which tests have that setting and what it is set to, then you have to go in to each test in turn to change it. From IC6.1.8 ISR3/ICADVM18.1 ISR3, we have added a tool to do just that. You can compare all the simulator settings...

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Analog Design Environment | ICADVM18.1 | ADE | simulator options | Virtuoso Video Diary | Custom IC Design | IC6.1.8 | Assembler | ADE Assembler
Virtuoso Video Diary: The Next Big Thing — ADE Verifier Teams Up with Cadence vManager

By Rashmi G | 16 May 2019

Need to perform functional verification of a mixed-signal design? Using the connection between Verifier and vManager, analog and digital engineers get to work together with two different tools using the same data. A single view allows a project manager to look up all the results together and the engineers to sign off the project. You have fulfilled traceability and tracking of results for internationally acknowledged...

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verifier | ICADVM18.1 | Functional Verification | Formalized Verification | vPlan | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso Video Diary | mixed-signal design | Custom IC Design | ADE Verifier | IC6.1.8 | vManager | verification

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