Custom IC Design Blogs

Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise and fall times. In this blog, we'll discuss the high impedance node checks available in Spectre and when to use each check.

We've been busy improving the usability of the Analog Design Environment products Virtuoso ADE Assembler and Virtuoso ADE Explorer over the recent releases. Click here to check out some of these usability updates that have been added between IC6.1.8/ICADVM20.1 ISR13 and ISR18 in this blog.

Details on a dedicated tab "Resources" in Job Policy form, which helps to do resource estimation while firing jobs in distributed farms like LSF, SGE, etc

The ICADVM20.1 ISR19 and IC6.1.8 ISR19 production releases are now available for download.

Virtuoso RF Solution is known for its extensive problem-solving capability that touches many product lines of the Virtuoso, AWR, and Allegro platforms. The Virtuoso RF Solution product page on the Cadence Learning and Support portal serves as a one-stop shop to showcase all the features on offer, the various flows in the overall solution, and related collateral for different modes of learning.

The new Large-Scale Cloud Simulation (LSCS) job control mode is highly scalable and can handle thousands of netlisting and simulation jobs in parallel. This job control mode supports all available job distribution methods in Virtuoso ADE Explorer and Virtuoso ADE Assembler. LSCS is an enabler for cloud-based simulation jobs. Read more...

This blog describes the behavioral modeling aspects of Verilog-AMS language that helps you to create and use modules for mixed-signal verification.

SPECTRE 19.1 ISR18, the last ISR of the SPECTRE 19.1 ISR release, was released on May 31st, 2021. This means that if you are still using the SPECTRE 19.1 release, you will not have access to any new features and enhancements made in Spectre. Read this blog to know more on how you can get the latest features and enhancements related to Spectre.

One of the strengths of the Virtuoso RF solution is the ability to handle connectivity across multiple fabrics. We have recently extended some the IC tools you already know and have used. They now comprehend connectivity across a multi-fabric system. You can trace a physical net from the package into the ICs that it hosts, and use connectivity checking to ensure your system layout’s nets match your schematic.

Read on to know the usefulness of the .simrc file and how and when it is picked by Virtuoso for netlist customization.

You can use Virtuoso keyboard shortcuts called bindkeys in Virtuoso Layout Suite to perform certain tasks. Check out this blog to see how you can download a printable document for bindkeys used in different Virtuoso Layout applications.

Fast and accurate electromagnetic simulation is becoming critical in a growing number of applications, and defining ports correctly is one of the most important things to get right to ensure accuracy. In this blog I will share some insights on defining ports for the EMX Solver.

In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz. We are also happy to announce and introduce our brand new corresponding training on June 14th 2021.

Chip tests have become more demanding as defects tend to occur more often in scaled down processes. In this blog, we'll discuss how you can use the Spectre Fault Analysis to improve test coverage by identifying critical test patterns.

This blog describes the features in Virtuoso Layout EXL and Clarity 3D Solver that are helpful in making the ports ready for an electromagnetic simulation.

The ICADVM20.1 ISR18 and IC6.1.8 ISR18 production releases are now available for download.

This blog shows how to efficiently use the Virtuoso ADE Assembler and Virtuoso ADE Explorer by using the available assistants in the Assembler and setting up a Monte Carlo run in the ADE Explorer.

Understanding the thermal performance of integrated circuits has been essential to avoid the overheating that can cause circuit malfunctions.  With greater integration, the power dissipation in integrated circuits is becoming increasingly impor...

Before the creation of die and package layout can begin, logical connectivity between these two fabrics need to be established. Based on the number of input or output and power or ground connections needed, the physical size and pin arrangement of the IC and package can start.

Cadence Learning and Support portal has introduced a new one-stop learning resource to guide you about different features of the Virtuoso Layout Suite products. Click here to know more.

In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz using the Cadence Virtuoso multi-technology framework.

Gone are the days of exporting results from multiple interactive runs and combining them into Excel spreadsheets for analysis. The new Reference Histories and Merge Histories flows address all these concerns. Click here to know more.

In circuit design, wrong connectivity may cause undesired leakage paths that may result in current hotspots. These current hotspots can be quickly identified with Spectre’s dynamic design checks. This blog describes how to use the Spectre design checks to identify the root cause of leakage path current hotspots.

Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis XL to analyze waveform data. Click here to know more.

The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for download.