Custom IC Design Blogs

Check out this blog to see how you can debug shorts using Interactive Shorts Locator (ISL)

Read this blog for an overview to the Circuit Layout design stage in Custom IC Design methodology and the key design steps which can help you achieve this.

The ICADVM20.1 ISR25 and IC6.1.8 ISR25 production releases are now available for download.

This blog is to announce the official release of the Fillet capability. The Fillet capability is another remarkable addition to our existing Virtuoso RF features portfolio. For analog and high-speed circuits, or areas of a design where shock and vibration to the design might disrupt connections, adding fillets to your design is probably the solution to improve yield and manufacturability.

From time to time, we observe Spectre customers using the maxstep feature for applications that can be better addressed with the Spectre strobe feature. Therefore, in this blog, we focus on explaining the usage of the Spectre strobe feature.

We are going to host a webinar on Virtuoso Layout Pro Training in the upcoming month. Check out this blog to know all the details.

Read this blog for an introduction to the Custom IC Design methodology and the key design challenges that the methodology can help you address.

DSPF files are an integral part of post-layout simulations. This blog introduces you to the commands and utilities provided by the Spectre circuit simulator to help you run simulations with DSPF netlists.

The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for download.

Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow the P&R routing style and are readable in Innovus.

Virtuoso Electromagnetic Solver integration allows layered parasitic extraction and electromagnetic simulation with Cadence Quantus Extraction Solution and Cadence EMX Planar 3D Solver. The seamless integration automatically ensures that parasitic effects are neither missed nor double-counted during post-layout circuit simulation. But what am I doing with custom passive devices? How can I include the parasitics of the...

We deliver one major Spectre ® circuit simulator release per calendar year. The base version of Spectre 20.1 was released in September 2020 and that of Spectre 21.1 in August 2021. For these two major releases, hotfix ISR releases are delivered in every 6 weeks. The latest hotfix releases in the two release streams are Spectre 20.1 ISR14 and Spectre 21.1 ISR4, both published in January 2022. The life of one Spectre...

The audit functionality is a checker utility that reports all errors or warnings for an export die function on an IC layout before actually exporting a die.

The ICADVM20.1 ISR23 and IC6.1.8 ISR23 production releases are now available for download.

This blog introduces you to the static voltage domain check in the Spectre circuit simulator.

Read through this blog to know more about the enhancements made to the eyeHeightAtXY and eyeWidthAtXY calculator functions.

A significant number of accuracy issues in Spectre simulations are caused by the designs that have multiple DC solutions. This blog illustrates how to identify and resolve such problems.

While Allegro Package Designer Plus together with SiP Layout Option is and continues to be one of the most complete solutions for package design, Virtuoso RF Solution allows module layout authoring capabilities inside the Virtuoso System Design Platform. The Virtuoso RF Solution offers a powerful suite of IC and package co-design capabilities, such as Edit-In-Concert, cross-fabric net probing, and bump optimization. Virtuoso...

Read this blog for an introduction to the Custom IC Design methodology and the key design challenges that the methodology can help you address.

The ICADVM20.1 ISR22 and IC6.1.8 ISR22 production releases are now available for download.

You can now assign tags to variables and corners in Virtuoso ADE Assembler. Check out this blog to find out.

This blog shows how Quantus Geometry Viewer (Quview) can be used to view various geometries like 3d views of an area generated by Quantus for debugging purposes. In addition, it shows the Connectivity checker which is is a netlist comparison utility to check the connectivity of the Quantus output netlist against the incoming LVS netlist data.

Read through this blog to know more about the usability enhancements made to the graph summary label in Virtuoso Visualization and Analysis XL.

Starting with ICADVM20.1 ISR20, you can write Design Intent notes in languages that use non-Latin character sets, for example, Mandarin Chinese, Japanese, and Hindi.

The ICADVM20.1 ISR21 and IC6.1.8 ISR21 production releases are now available for download.