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  • Sucharita
    Virtuoso Video Diary: Performance Diagnostic Tool – An MRI Scanner for Virtuoso
    By Sucharita | 11 Feb 2021
    You can now use the Performance Diagnostic tool in the Virtuoso custom IC design platform to diagnose issues that might be causing your system to slowdown or freeze. Click here to know more.
    0 Comments
    Tags:
    performance diagnosis | Virtuoso | performance diagnostic | ICADVM20.1 | Custom IC Design | Custom IC | Virtuoso scanner
  • Parula
    Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 5
    By Parula | 4 Feb 2021
    Continuing our momentum with the Knowledge Booster blogs in the year 2021 , this blog informs you how to overcome DC Convergence issues and errors for a Spectre Simulation by modifying associated parameters.
    0 Comments
    Tags:
    blended | Spectre DC | Spectre Pro | training | digital badges | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Cadence Education Services | Custom IC Design | online training
  • Virtuoso Release Team
    Virtuoso ICADVM20.1 ISR16 and IC6.1.8 ISR16 Now Available
    By Virtuoso Release Team | 3 Feb 2021
    The ICADVM20.1 ISR16 and IC6.1.8 ISR16 production releases are now available for download.
    0 Comments
    Tags:
    Cadence blogs | ADE Explorer | cadence | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso Visualization and Analysis XL | Virtuoso Analog Design Environment | ICADVM20.1 | IC Release Blog | Clarity 3D Solver | Custom IC Design | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | Custom IC | ADE Verifier | IC6.1.8 | ADE Assembler
  • Stefan Wuensche
    Spectre Tech Tips: Using Spectre X for RF Analyses
    By Stefan Wuensche | 29 Jan 2021
    In the Spectre 20.1 base release at the end of September 2020, we released Spectre X-RF. The Spectre X-RF technology integrates the Spectre X engine into Spectre’s RF analyses. In this blog, we introduce the Spectre X-RF technology.
    0 Comments
    Tags:
    +xdp | +preset | Spectre X-RF | spectre x | Spectre X distributed simulation | Spectre X Simulator
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire – Looking Back and beyond!
    By Team ADE Verifier | 28 Jan 2021
    Have you missed out on any of the In the Line of Veri-Fire blogs? Here's your chance to fix it...
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | custom/analog | Analog Simulation | verification plan | analog | ADE | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | cadenceblogs | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | ADE Assembler | verification
  • Pallabi R
    Virtuosity: Moving Along the Least-Resistive Path in Voltus-Fi
    By Pallabi R | 16 Dec 2020
    Do you want to know how discovering the path of least resistance for the devices of your design much ahead of your power planning can make your life easier? Then go ahead and read the blog.
    0 Comments
    Tags:
    Voltus-Fi | electromigration | EMIR Analysis | power grid | Voltus-Fi-XL | Virtuoso | voltage drop | ICADVM20.1 | LRP | Custom IC Design | Custom IC | IC6.1.8
  • FredIvar
    Spectre Tech Tips: Increasing Performance and Capacity Using Spectre X Distributed Simulation
    By FredIvar | 15 Dec 2020
    The Spectre X distributed simulation is an extension to the multithreaded simulation where cores from different machines are used. The Spectre X distributed simulation provides access to more cores, thus increasing the performance and capacity and providing more value for large designs.
    0 Comments
    Tags:
    multithreaded simulation | ppn | Multi-Core | XDP | spectre x | Spectre X distributed simulation | multithreaded
  • Claudia Roesch
    Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy
    By Claudia Roesch | 15 Dec 2020
    Fast growing markets like 5G, automotive, and IoT are driving the development of advanced semiconductor technologies and silicon-integrated circuits. In particular, the high cutoff frequency of advanced CMOS and Silicon-Germanium (SiGe) bipolar devices allow the integration of millimeter-wave circuits with good high-frequency performance and high integration level at moderate mask costs.
    0 Comments
    Tags:
    Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF Solution | Electromagnetic analysis | EMX | Quantus Extraction Solution | RF design | ICADVM20.1 | Custom IC Design | VMM
  • Tyler
    Virtuoso Meets Maxwell: Defining Standard Library Components
    By Tyler | 7 Dec 2020
    The Allegro Package Designer product line offers everything needed to take an IC package from idea to manufactured part, and this is where the journey takes us today. It is available from your Virtuoso environment as Virtuoso MultiTech Framework.
    0 Comments
    Tags:
    Libimport | Unified Library | JEDEC | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso RF | Virtuoso MultiTech | Package Design in Virtuoso | Allegro Package Designer Plus | BGA | Allegro Package Designer | die | Virtuoso | ICADVM20.1 | Cadence SiP Layout | Custom IC Design | Custom IC | Allegro | VMM
  • bsachin
    Virtuosity: Conserve Power—Verifying a Design Using Conformal Low Power
    By bsachin | 3 Dec 2020
    If you have been following the Conserve Power blog series, you will probably have an idea of what next I am going to talk about. Yes, we have now reached the finale, the last and the most intriguing piece in the entire story. It is the formal verification and sign-off of the IP to make it ready to be integrated into an SoC.
    0 Comments
    Tags:
    Virtuoso Schematic Editor | virtuoso power manager | clp | Conformal Low Power | VPM | Supply States | 1801 | setup | Virtuoso | Virtuosity | ICADVM20.1 | UPF | IEEE | mixed-signal design | Liberty | Custom IC Design | power domains
  • Parula
    Virtuoso Video Diary: Why Split Symbols?
    By Parula | 3 Dec 2020
    A blog that tells you about why splitting up blocks has now become a useful feature in more complex designs and advanced technology.
    0 Comments
    Tags:
    split symbols | Virtuoso Schematic Editor | custom/analog | splits | Virtuoso | ICADVM20.1 | create split symbols | create splits | Custom IC
  • KomalJohar
    Virtuosity: Our Design Thinking Approach to Enhance User Interfaces across Cadence Products
    By KomalJohar | 2 Dec 2020
    Read our story about how teams across Cadence, diligently work towards enhancing your experience by continuously improving the quality of user interfaces from a usability aspect.
    0 Comments
    Tags:
    virtuoso power manager | EMIR Analysis | cadence | reliability options | usability | reliability analysis | Custom IC
  • Parula
    Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 4
    By Parula | 24 Nov 2020
    We live in a complex world where it is essential to use and combine tools and platforms as efficiently as possible with all available features. In this blog, we are happy to show you how easy it can be to get best results using the Spectre Simulation Platform and its corresponding options.
    0 Comments
    Tags:
    blended | Spectre RF | training | digital badges | training bytes | Virtuoso | Cadence certified | Virtuoso Video Diary | Cadence Education Services | Custom IC Design | online training
  • Virtuoso Release Team
    Virtuoso ICADVM20.1 ISR15 and IC6.1.8 ISR15 Now Available
    By Virtuoso Release Team | 23 Nov 2020
    The IC6.1.8 ISR15 and ICADVM20.1 ISR15 production releases are now available for download.
    0 Comments
    Tags:
    Analog Design Environment | Cadence blogs | ADE Explorer | cadence | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso Visualization and Analysis XL | Virtuoso | ICADVM20.1 | IC Release Blog | Custom IC Design | Virtuoso Layout Suite EXL | Custom IC | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
  • Guru Rao
    Virtuoso Meets Maxwell: Enabling System Analysis And Implementation Through Libraries
    By Guru Rao | 23 Nov 2020
    Welcome to a post on how to create component and padstack libraries for use in the Virtuoso platform-driven multiple technology flows. This post describes the tasks of a librarian, who must assemble component IP from various sources and create the views and documentation that can be used by designers.
    0 Comments
    Tags:
    Technology Independent Layout Pcell | Unified Library | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF Solution | Virtuoso RF | Virtuoso MultiTech | Electromagnetic analysis | librarian | SiP Layout Option | ICADVM20.1 | Cadence SiP Layout | TILP | Custom IC Design | VMM
  • bsachin
    Virtuosity: Conserve Power—Importing and Exporting Power Intent
    By bsachin | 20 Nov 2020
    In this blog, I will focus on the key enablers, which are required before the power-aware designs undergo the verification cycle. This is the ultimate test that confirms the robustness and efficiency of a design.
    0 Comments
    Tags:
    Virtuoso Schematic Editor | virtuoso power manager | Conformal Low Power | VPM | Supply States | 1801 | setup | Virtuoso | Virtuosity | ICADVM20.1 | UPF | IEEE | mixed-signal design | Liberty | Custom IC Design | power domains
  • Pallabi R
    Virtuosity: Decoding the Mechanics of What If in Voltus-Fi-XL
    By Pallabi R | 17 Nov 2020
    What if you could foresee potential changes in your design and analyze their impact in advance? I’m sure, your life would have been easier, isn’t it? Read on to know more about the what-if or ECO analysis feature in Voltus-Fi-XL.
    0 Comments
    Tags:
    EMIR Analysis | debug | Voltus-Fi-XL | what-if analysis | Virtuoso | Virtuosity | ICADVM20.1 | Custom IC Design | IC6.1.8 | EMIR
  • Manishj
    Virtuosity: Conserve Power— Running In-Design Checks
    By Manishj | 12 Nov 2020
    Today’s blog focuses on in-design checks that offer an easy and convenient way to identify common design issues encountered by the design community while implementing low power schemes. It also helps designers to uncover issues early in the design cycle, avoiding an ECO.
    0 Comments
    Tags:
    In-Design Checks | Low Power | virtuoso power manager | Schematic XL | in-design | VPM | Schematic Editor | ICADVM20.1 | UPF | Power Manager | mixed signal | Liberty | Custom IC Design
  • Pallabi R
    Virtuosity: The Debut of the Virtuoso EMIR Analysis Flow for DSPF
    By Pallabi R | 10 Nov 2020
    Do you want accurate extraction data for your design, regardless of foundry process and node? Do you want to complete your EMIR setup entirely within the Virtuoso framework? Then explore the new Virtuoso EMIR DSPF flow…
    0 Comments
    Tags:
    Voltus-Fi | EMIR Analysis | ADE Explorer | Voltus-Fi-XL | MMSIM | DSPF | EMIR Extraction | Spectre | Quantus Extraction Solution | Virtuosity | ICADVM20.1 | analog design | signoff | Custom IC Design | Virtuoso Layout Suite | simulation | IC6.1.8 | ADE Assembler
  • deeptig
    Virtuosity: Conserve Power— Setting up Virtuoso Power Manager
    By deeptig | 4 Nov 2020
    This time I am back with a blog that briefly explains how to set up Virtuoso Power Manager before proceeding with low power verification. To run in-design checks, extract the power intent from a design, or run Conformal Low Power checks, you must first provide inputs that are required by the tool for correct identification of design topology and define the set of rules that apply to those design structures. For example...
    0 Comments
    Tags:
    Virtuoso Schematic Editor | virtuoso power manager | Conformal Low Power | VPM | Supply States | setup | Virtuoso | Virtuosity | ICADVM20.1 | mixed-signal design | Custom IC Design | power domains
  • colint
    Virtuosity: Design, Plan, and Analysis - The 3 Sides Of A Coin, Episode 1
    By colint | 3 Nov 2020
    Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.
    0 Comments
    Tags:
    Congestion Analysis | Layout Generation | Analog Design Environment | Cadence blogs | global route | Virtuoso Layout EXL | Advanced Node | Floorplanning | pin placement | Virtuosity | ICADVM20.1 | dpa | pin planning | Custom IC Design | Virtuoso Layout Suite | Design Planning and Analysis
  • deeptig
    Virtuosity: Conserve Power—A Preamble to Virtuoso Power Manager
    By deeptig | 29 Oct 2020
    Power consumption has always been an overriding concern in electronic design. Consumption relates not only to the power used in the circuitry but also involves monitoring the circuit to prevent overheating. The battery life of any electronic product can be a deciding factor in its success. Designers are continually devising innovative methods to ensure minimal power consumption without impacting the performance of their...
    0 Comments
    Tags:
    Virtuoso Schematic Editor | virtuoso power manager | clp | Virtuoso Schematic XL | Conformal Low Power | Mixed-Signal | VPM | Virtuoso | Virtuosity | ICADVM20.1 | Custom IC
  • Stefan Wuensche
    Spectre Tech Tips: The Value of Spectre X in EMIR Analysis
    By Stefan Wuensche | 28 Oct 2020
    EMIR analysis is one of the more challenging fields of circuit simulation. It requires the power and/or signal net parasitics to be preserved for the later IR drop and EM current analysis. At the same time the EMIR analysis requires SPICE accuracy for properly checking the EM currents against the current limits defined by the foundry. The Cadence transistor level EMIR analysis tool is Voltus-Fi XL which uses the Spectre...
    0 Comments
    Tags:
    Spectre X EMIR | EMIR Analysis | MX mode | Direct Method | Spectre | Iterated Method | spectre x
  • Udit Rajput
    Virtuoso Video Diary: Usability Enhancements in Digital Signals
    By Udit Rajput | 27 Oct 2020
    Read through this blog to know more about the usability enhancements made to digital signals in Virtuoso Visualization and Analysis XL.
    0 Comments
    Tags:
    Mnemonic Map | Cadence blogs | ICADVM18.1 | simvision | analog | Virtuoso Visualization and Analysis XL | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuoso Video Diary | ICADVM20.1 | Configure Mnemonics | usability | Custom IC | IC6.1.8
  • jgrad
    Virtuoso Meets Maxwell: Full 3D Analysis of Traces and Bond Wires in an RF Module
    By jgrad | 26 Oct 2020
    When you are running the EM analysis for an RF module with a wirebonded IC, an important task is to capture the full coupling between the package and the bond wires. Read this blog to know about a quick and effortless way to do this in Virtuoso RF Solution.
    0 Comments
    Tags:
    EM Analysis | ICADVM18.1 | Virtuoso RF Solution | Electromagnetic analysis | ICADVM20.1 | Clarity 3D Solver | Custom IC Design | Virtuoso Layout Suite EXL | Custom IC | clarity
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