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IC Packagers: An Introduction to Via Arrays

By Tyler | 18 Feb 2020

Vias are present in every design (except maybe some lead frames and the very rare single-layer substrate). Where they are placed, and how many there are, will depend on a slew of factors, though, as we know. There are different situations and reasons...

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Allegro Package Designer
BoardSurfers: Training Insights - Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

By mrigashira | 18 Feb 2020

In the days of yore when life was simple, there was a world full of DRAMs (Dynamic Random Access Memory). We have come a long way from there. First came Synchronous DRAMs (SDRAMS). Isn't it neater anyway, SDRAM? More systematic and organized, in tune...

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Allegro Package Designer | Sigrity | Allegro PCB Editor
Playing for Good

By Madhavi Rao | 18 Feb 2020

Last Saturday, Cadence and Concern India Foundation hosted a very special event - a charity sports tournament for corporates called “5Cs” – the Corporate Citizenship Challenge for the Cause of Children. It is one of the most fun eve...

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5Cs | NXP Semiconductor | amadeus | Qualcomm
DVCon 2020 Preview

By Paul McLellan | 18 Feb 2020

Coming up to the big conferences like DAC, I like to do one or more preview posts, both as a service for people who are already going to help them decide what to attend, and also to encourage people in the industry to attend. DVCon is another confere...

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DVcon | Accellera | pss
Sunday Brunch Video for 16th February 2020

By Paul McLellan | 16 Feb 2020

https://youtu.be/uc_vrZsq-2I Made in Cadence parking lot (camera Steve Brown) Monday: Benedict Evans 2020: Standing on the Shoulders of Giants Tuesday: Benedict Evans 2020: Regulating the Giants Wednesday: System Analysis: Computational Software...

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sunday brunch