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Life at Cadence

Cadence Women Conference in the Asia-Pacific and Japan Region – A Recap

Written by the APJ CWC Core Team. After several successful Cadence Women Conferences…

Mary Kasik 13 May 2025 • 2 min read

CWC , WomenAtCadence , LifeAtCadence

System, PCB, & Package Design

UCIe Full SI Analysis Flow with Compliance Check for Heterogeneous Integration

3D heterogeneous integration (3DHI) technology creates high-performance systems by…

MSATeam 13 May 2025 • 2 min read

Analog/Custom Design

Did You Miss the Quantus Insight Webinar? No Worries, the Recording Is Available…

If you missed joining or registering for the Quantus Insight webinar, the complete…

Justas Lukosiunas 9 May 2025 • 1 min read

Analog/Custom Design

Unlocking the Power of Analog Design Verification with Virtuoso ADE Verifier

In the fast-paced world of analog and mixed-signal design, ensuring that your circuits…

Niyati Singh 9 May 2025 • 3 min read

Analog Design Environment , Cadence blogs , custom/analog , analog , ADE , Virtuoso Analog Design Environment , Cadence training , training bytes , Virtuoso , Spectre , cadenceblogs , Cadence Education Services , Custom IC Design , Custom IC , ADE Verifier

SoC and IP

Boosting AI Performance with CXL

As AI applications rapidly advance, AI models are being tasked with processing massive…

Vanessa Do 8 May 2025 • 3 min read

CXL , IP , controller , PCIe

Life at Cadence

UK Interns Community Giving Day

UK Interns Lady Payan Cepeda, Seiba Abdul Rahman, and Hudson Ashmoore, hailing from…

Madhuparna Datta 8 May 2025 • 2 min read

CadenceCares , Culture , giving back , great place to work , life at cadence , cadence emea

Corporate News

Cadence and AVCC to Advance Physical AI Innovations for Autonomous Vehicles

Cadence has joined the Autonomous Vehicle Computing Consortium (AVCC) , marking a…

Corporate 8 May 2025 • 2 min read

Automotive , IP , featured , physical ai , chiplet , Safety , system on chip , HPC , high-performance computing , ADAS

Corporate News

Chip Design Industry Reaches an AI Inflection Point

The chip design landscape has hit a transformative milestone, one that signals a…

Corporate 8 May 2025 • 5 min read

inflection point , featured , agentic ai , agentic

Corporate News

Cadence Agentic AI Reduces SoC/System Engineering Time by Months

The modern design landscape is evolving rapidly, driven by shrinking design cycles…

Corporate 7 May 2025 • 5 min read

featured , agentic ai , AI

Corporate News

Transforming Chip Design with Agentic AI: Introducing Cadence Cerebrus AI Studio

The industry's first agentic AI, multi-block, multi-user SoC design platform To…

Corporate 7 May 2025 • 4 min read

featured , Cadence Cerebrus , Digital Implementation , AI

Analog/Custom Design

Virtuoso Studio IC23.1 ISR14 Now Available

Virtuoso Studio IC23.1 ISR14 production release is now available for download.

Virtuoso Release Team 7 May 2025 • 2 min read

featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso , Custom IC Design , Custom IC , IC design , IC23.1

Verification

UALink: Powering the Future of AI Compute

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification…

Sangeeta Soni 5 May 2025 • 2 min read

SoC and IP

Linux-Based Audio Platform with Cadence Tensilica HiFi 5

A Linux-based audio platform with Cadence Tensilica HiFi 5 enables rapid algorithm…

Vinod Khera 5 May 2025 • 3 min read

hifi 5 , IP , Tensilica , HiFi 5s , HiFi Audio

System, PCB, & Package Design

BoardSurfers: Training Insights: Advanced Design Verification with RAVEL

RAVEL, which stands for Relational Algebra Verification Expression Language, is designed…

ACat299612 5 May 2025 • 5 min read

PCB , Allegro X PCB Editor , DRC , ravel , Allegro X Advanced Package Designer , APD , PCB Editor , Allegro Package Designer , PCB design , Constraints , allegro x

Computational Fluid Dynamics

Exploring Turbulence: An Introductory Approach

Key Points Turbulence is a widespread phenomenon that occurs across many scales…

Gaurav 5 May 2025 • 5 min read

CFD , turbulence , LES

Digital Design

Semiconductors: Pioneering Extraordinary Growth in the 20th Century

Semiconductors have revolutionized the world, powering everything from smartphones…

Udaya Shankar 5 May 2025 • 3 min read

Static timing analysis , online courses , Cadence Online Support , RTL-to-GDSII , Joules , training bytes , Digital Implementation , Innovus , Synthesis , online training , physical implementation , cadence learning and support

SoC and IP

CadenceLIVE 2025: The Field Guide for Defense Digital Engineering

Modern microelectronics is a new operating theater for many in the Defense Industrial…

Adam Sherer 1 May 2025 • 2 min read

cadencelive , defense

Digital Design

Microlearning: The Snackable Knowledge Training Videos

Are you looking to level up your digital design skills—one byte at a time? Ohoo!…

P Saisrinivas 30 Apr 2025 • 5 min read

DFT , RTL2GDSII Flow , online courses , Functional Verification , Gate level simualtion , LEC , STA , Cadence training , training bytes , Digital Implementation , implementation , physical design , Synthesis , RTL design , RTL2GDSII Webinar

System, PCB, & Package Design

System Analysis Knowledge Bytes - Optimizing LPDDR5X Performance with Sigrity X

This blog post explores the capabilities of Cadence Sigrity X Advanced SI in designing…

ShivaShankarM 30 Apr 2025 • 5 min read

Sigrity and Systems Analysis , TopXp , PBA , DDR interface , Sigrity X , system analysis , measurement , license , SPB , ddrx , lpddr5x , Sigrity , High Speed design , simulation , Advanced SI

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