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Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Corporate
Corporate 7 Aug 2026 • 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

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Blog - Post List
Latest blogs

PCB、IC封装:设计与仿真分析

AI/ML 如何优化 IBIS-AMI 模型参数?

摘要 随着高速串行链路速率持续提升,IBIS-AMI 模型的参数空间变得更加复杂。传统手动寻优需要大量仿真,成本高且效率低。本文结合 Cadence Sigrity…

SDA China 13 Aug 2026 • less than a min read
Chinese blog , ml , 中文 , Sigrity , 信号完整性

Analog/Custom Design

Virtuoso Studio: Turning S-Parameter Data into Actionable Insights

Read this blog to learn how the S-Parameter Assistant simplifies RF and microwave…

Udit Rajput 12 Aug 2026 • 2 min read
S-parameter Analysis , S-parameter , ViVa-XL , Virtuoso Studio , ADE Explorer , Virtuoso Visualization and Analysis XL , virtuoso visualization and analysis , S-Parameter Quality Checking tool , Virtuoso Analog Design Environment , Spectre , ViVA , ADE Artist , Custom IC Design , ADE Assembler

Digital Design

The Odyssey of a Great Floorplan

With the recent release of The Odyssey , audiences are once again following an epic…

VNelson 12 Aug 2026 • 5 min read
Foorplanning , training bytes , digital implementation , Innovus

Physical Systems Simulation (CAE)

Adams 2026.1: Modernizing the Simulation Experience for Rapid Innovation

As Adams continues to evolve as a trusted solution for multibody dynamics, helping…

Pankaj Pawar 12 Aug 2026 • 2 min read
Multibody Dynamics , simulation software , Adams

RF Engineering

Accelerating ASTRO SDR Carrier Board Design with Cadence Visual System Simulator

The Slipstream Design ASTRO Ecosystem platform provides a software-defined radio…

StandingWaves 11 Aug 2026 • 4 min read
RF , RF Simulation , analog/RF , VSS , microwave office

System, PCB, & Package Design 

Register Now: Tackling the Complexity of Next-Generation IC Packaging

Today’s IC packaging solutions continue to grow in complexity, posing several challenges…

MSATeam 11 Aug 2026 • less than a min read
Sigrity Aurora , IC Packaging , Sigrity X , Allegro X Advanced Package Designer , Power Integrity , Allegro Package Designer , Signal Integrity , Thermal Analysis

Physical Systems Simulation (CAE)

What Is CAE Software? Computer-Aided Engineering from Simulation to Signoff

Discover what CAE software is, how computer-aided engineering integrates FEA, CFD…

Corporate 11 Aug 2026 • 10 min read
Beta CAE , CAE , CAE Software

Analog/Custom Design

Analog Design Migration Made Easy With Migration Cockpit

Analog IP remains one of the most valuable and difficult-to-scale assets in semiconductor…

Vinod Khera 10 Aug 2026 • 5 min read
analog IP , Automated test bench migration , parasitic aware optimization , Front to back Analog Migration , PPA , Analog Design Migration , schematic migration

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Corporate 7 Aug 2026 • 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design , design for AI , millennium

Digital Design

The 0.1 ns Mistake That Delayed an Entire Chip!

We’ve all been there. You wake up early, get ready on time, leave home exactly as…

P Saisrinivas 6 Aug 2026 • 3 min read
digital badge , digital design , Setup Time , Static timing analysis , Hold TIme , Low Power , Genus , Signoff Analysis , Timing Violations , RTL-to-GDSII , training , OCV , training bytes , Digital Implementation , Innovus , online training , tcl

Digital Design

Stop Coding RTL First - A Smarter Path to Hardware Design Using SystemC

Modern hardware design keeps demanding more -- more speed to market, more flexibility…

Prashanth Adek 6 Aug 2026 • 5 min read
digital badge , Training and Support , Stratus HLS , Cadence blogs , online courses , cadence , training , Stratus , SystemC , Cadence support , cadence learning and support

Physical Systems Simulation (CAE)

Speed Up External Superelement Reduction by 30x with AMSR in MSC Nastran

MSC Nastran pioneered superelements almost four decades ago and, still today, continues…

Cadence MSC Software 5 Aug 2026 • 3 min read
physical systems simulation , MSC Nastran , MSC Software , simulation software , CAE

Life at Cadence

The Power of Yet in the Age of AI

How one keynote on reinvention changed the way I think about careers, AI, and the…

Reela Samuel 3 Aug 2026 • 6 min read
Voices India 2026 , Power of Yet , Voices , AI

Physical Systems Simulation (CAE)

Breaking the Memory Bottleneck with scFAST Solver in Cradle CFD

In large-scale computational fluid dynamics (CFD) , speed is often framed around…

Veena Parthan 3 Aug 2026 • 5 min read
CFD , Aerospace , Cradle CFD , simulation software , scFLOW , scFast Solver

Digital Design

Beyond Moore's Law: Advances in Modern Semiconductor Design

The Shifting Landscape For decades, Moore's Law delivered a simple promise: more…

Udaya Shankar 31 Jul 2026 • 6 min read
digital badge , artificial intelligence , 3D-IC , Cadence Online Support , Logic Design , Cadence training , training bytes , implementation , online training , Full-Chip , DFM , verification

Academic Network

A Scholarship and a Summer at Cadence

The Cadence Future Innovators Scholarship was established to support students working…

Yesenia Carrillo 31 Jul 2026 • 4 min read
CadenceCares , Cadence interns , LifeAtCadence

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai , NVIDIA , advanced packaging , Samsung , AI for design , Ambarella , design for AI , advanced nodes , 3D-IC Technology , design stack , 2nm

Digital Design

Power Grid Verification Flow: A Methodology for High-Coverage Signoff

As semiconductor designs continue to scale in complexity, ensuring robust power integrity…

Vinod Khera 31 Jul 2026 • 3 min read
Power Integrity , voltus training kit , Power Grid Verification

Verification

When the Bug Is in the Waveform, the UALink Story Should Be There Too

Real design debug often ends in the same place: a waveform window full of DUT signals…

Sandeep Grover 31 Jul 2026 • 5 min read
bug , waveform , UALink , Verisium Debug , debugging , verification
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