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I have been criticized in the past for calling OrbitIO the "red-headed stepchild" of the Cadence product line. I think I shall have to improve my positioning and simply call it "ahead of its time". OrbitIO is the cockpit for all t...

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging...

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released and started to reshape the way design and verification engineers think about SoC level verification and testing. It took a noble idea of creating a single repr...

This is another of my occasional update posts, covering changes to recent posts that are not big enough to justify an entire post on their own. Today, Pointwise and PCIe. You will almost certainly have to read further to discover who Pointwise is. Yo...

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。 このシリーズの新しいブログに関する通知を受け取るために、Subscribe Nowをクリックし、Su...