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Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

From Layout to Silicon: Mastering Parasitic Extraction with the Quantus Training

From fundamentals to advanced nodes, discover how Quantus training helps VLSI engineers…

• 6 min read
parasitic-aware design , parasitic , Quantus Extraction Solution , qrc , Quantus , Parasitic extraction , parasitics

Digital Design

Your Phone Gets Updates, So Does Your Synthesis Expertise!

Most of us update our phones without ever knowing about the coolest new features…

• 2 min read
online courses , training , optimization , training bytes , Genus Synthesis Solution , online training

System, PCB, & Package Design 

Designing Integrated SOI X-Band Radar Switches with Cadence Workflow

RF systems operate under tight budgets for loss, coupling towards unwanted paths…

• 3 min read
Radar Switches , Power Integrity , IC package design , Signal Integrity , Sigrity , Clarity 3D Solver

SoC and IP

Why AI Factories Need Great Interconnect IP, Not Just More Compute

AI infrastructure is often evaluated based on compute: how many accelerators, how…

• 3 min read
ucie , IP , AI data center , AI Factories , HBM , memory IP , SerDes IP , interface design

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design , Process Design Kit , Intel Foundry

Learning and Support

Come Join Us and Learn from the Cadence Training Offerings

Are you wondering how to learn Cadence tools and technologies for free? Cadence offers…

• 5 min read
college grads , onboarding , videos , Customer Training , CadenceASK , Self Learning , Cadence Online Support , becomeproductivefast , training , Cadence training , training bytes , Cadence certified , bridgingthelearninggap , cadencetraining , Cadence ASK , Cadence Education Services , learning and support , ask , Cadence Learning and Support portal , TrainingBlogs , support resources , online training , Cadence Support Portal , Cadence support , cadence learning and support

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA , ChipStack AI Super Agent , AI

Verification

AMBA AXI5 Memory Tagging Extension: Making Memory Safety Observable on the Bus

Memory safety remains one of the most persistent challenges in modern computing systems…

• 5 min read
Memory Security , MTE , Memory Tag , AXI5 , AMBA Verification IP

Digital Design

Still Using Synthesis Tricks from Your "Golden Script" Folder? Consider Upgrade!

Ever looked at an old synthesis script and thought, “Who wrote this masterpiece of…

• 4 min read
Genus , Cadence Online Support , training , training bytes , Synthesis , online training

System, PCB, & Package Design 

Ascent: Training Insights: Hierarchical Design in Allegro X PCB System Capture

As PCB designs become larger and more complex, flat schematics are harder to manage…

• 4 min read
System Capture , schematic design , System-Level Design , Design Reuse , PCB design , allegro x , hierarchical block , Allegro X System Capture

Verification

MIPI M‑PHY v6.0: Evolution of ADAPT for Ultra‑High‑Speed Interfaces

MIPI M-PHY has evolved to support higher data rates with the introduction of HS-G4…

• 3 min read
Verification IP , MIPI Alliance , VIP , MIPI , MPHY

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent , InnoStack AI Super Agent , ViraStack AI Super Agent

Digital Design

Might of Design Exploration: Deep Dive of Exploration Techniques in Stratus HLS

Stratus HLS's behavioral design methodology enables easy exploration of multiple…

• 10 min read
High-Level Synthesis , Stratus HLS , cerebrus , Stratus , SystemC , Synthesis

Analog/Custom Design

Using Reliability Degradation Parameters to Drive Better Design Choices

A circuit can look perfect on day one and still drift out of specification after…

• 6 min read
blended , blended training , Analog Design Environment , Cadence blogs , Virtuoso Studio , custom/analog , ADE Explorer , Analog Simulation , analog , training , Virtuoso Analog Design Environment , Cadence training , analog/mixed-signal , digital badges , training bytes , Virtuoso , Spectre , Analog Design Environment , Circuit Design , IC Release Blog , Custom IC Design , online training , Custom IC , Cadence Community , ADE Assembler

Corporate News

Jilin University Accelerates Student Racing Success Using Fidelity CFD Software

Founded in 1955, the College of Automotive Engineering at Jilin University has a…

• 2 min read
CFD , designed with cadence , Fidelity CFD

Physical Systems Simulation (CAE)

The Sound of Silence as AI Rewrites EV NVH Engineering

Step into a modern electric vehicle, and one thing becomes immediately clear: the…

• 6 min read
MSC Nastran , electric vehicles , Actran , NVH simulation , simulation software , ODYSSEE

Digital Design

Accelerate Design Signoff with the Updated Cadence Voltus Training Kit

By Ronen Stilkol, Senior AE Architect As advanced-node and 3D-IC designs push higher…

• 8 min read
package , Voltus , die , VTK

Learning and Support

Cadence Welcomes Xinqiao Electronics to the Certified Training Partner Program

The semiconductor industry requires a highly skilled workforce and demands that recent…

• 1 min read
PCB , Cadence training , bridgingthelearninggap , PCB design , Cadence Education Services , learning and support , Training Partners

Verification

PSS 3.1 Channels: The Game Changer for Target-Time Communication

Portable Stimulus models already feature powerful language constructs to describe…

• 7 min read
PSS 3.1 , Perspec , System Design and Verification , channels , perspec system verifier , target time communication
CDNS - Fix Layout Hompage