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DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Corporate
• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

RF Engineering

Accelerating ASTRO SDR Carrier Board Design with Cadence Visual System Simulator

The Slipstream Design ASTRO Ecosystem platform provides a software-defined radio…

• 4 min read
RF , RF Simulation , analog/RF , VSS , microwave office

System, PCB, & Package Design 

Register Now: Tackling the Complexity of Next-Generation IC Packaging

Today’s IC packaging solutions continue to grow in complexity, posing several challenges…

• less than a min read
Sigrity Aurora , IC Packaging , Sigrity X , Allegro X Advanced Package Designer , Power Integrity , Allegro Package Designer , Signal Integrity , Thermal Analysis

Physical Systems Simulation (CAE)

What Is CAE Software? Computer-Aided Engineering from Simulation to Signoff

Discover what CAE software is, how computer-aided engineering integrates FEA, CFD…

• 10 min read
Beta CAE , CAE , CAE Software

Analog/Custom Design

Analog Design Migration Made Easy With Migration Cockpit

Analog IP remains one of the most valuable and difficult-to-scale assets in semiconductor…

• 5 min read
analog IP , Automated test bench migration , parasitic aware optimization , Front to back Analog Migration , PPA , Analog Design Migration , schematic migration

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design , design for AI , millennium

Digital Design

The 0.1 ns Mistake That Delayed an Entire Chip!

We’ve all been there. You wake up early, get ready on time, leave home exactly as…

• 3 min read
digital badge , digital design , Setup Time , Static timing analysis , Hold TIme , Low Power , Genus , Signoff Analysis , Timing Violations , RTL-to-GDSII , training , OCV , training bytes , Digital Implementation , Innovus , online training , tcl

Digital Design

Stop Coding RTL First - A Smarter Path to Hardware Design Using SystemC

Modern hardware design keeps demanding more -- more speed to market, more flexibility…

• 5 min read
digital badge , Training and Support , Stratus HLS , Cadence blogs , online courses , cadence , training , Stratus , SystemC , Cadence support , cadence learning and support

Physical Systems Simulation (CAE)

Speed Up External Superelement Reduction by 30x with AMSR in MSC Nastran

MSC Nastran pioneered superelements almost four decades ago and, still today, continues…

• 3 min read
physical systems simulation , MSC Nastran , MSC Software , simulation software , CAE

Life at Cadence

The Power of Yet in the Age of AI

How one keynote on reinvention changed the way I think about careers, AI, and the…

• 6 min read
Voices India 2026 , Power of Yet , Voices , AI

Physical Systems Simulation (CAE)

Breaking the Memory Bottleneck with scFAST Solver in Cradle CFD

In large-scale computational fluid dynamics (CFD) , speed is often framed around…

• 5 min read
CFD , Aerospace , Cradle CFD , simulation software , scFLOW , scFast Solver

Digital Design

Beyond Moore's Law: Advances in Modern Semiconductor Design

The Shifting Landscape For decades, Moore's Law delivered a simple promise: more…

• 6 min read
digital badge , artificial intelligence , 3D-IC , Cadence Online Support , Logic Design , Cadence training , training bytes , implementation , online training , Full-Chip , DFM , verification

Academic Network

A Scholarship and a Summer at Cadence

The Cadence Future Innovators Scholarship was established to support students working…

• 4 min read
CadenceCares , Cadence interns , LifeAtCadence

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai , NVIDIA , advanced packaging , Samsung , AI for design , Ambarella , design for AI , advanced nodes , 3D-IC Technology , design stack , 2nm

Digital Design

Power Grid Verification Flow: A Methodology for High-Coverage Signoff

As semiconductor designs continue to scale in complexity, ensuring robust power integrity…

• 3 min read
Power Integrity , voltus training kit , Power Grid Verification

Verification

When the Bug Is in the Waveform, the UALink Story Should Be There Too

Real design debug often ends in the same place: a waveform window full of DUT signals…

• 5 min read
bug , waveform , UALink , Verisium Debug , debugging , verification

SoC and IP

Scale-Up Ethernet Ecosystem Ramps Up: Cadence ESUN Controller IP Available

AI Infrastructure Networking Demands The AI Infrastructure industry is investing…

• 3 min read
controller IP , Design IP , IP , controller , Ethernet standards , Ethernet

Corporate News

AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP

As AI workloads scale in size, complexity, and performance requirements, delivering…

• 4 min read
advanced nodes , 3dfabric , AI silicon , TSMC-COUPE , system integration

Corporate News

HPE: Designing Data Centers for AI at Scale

One of the biggest inefficiencies in modern data centers is the disconnect between…

• 2 min read
digital twin , designed with cadence , Cadence Reality Digital Twin Platform

Digital Design

The PPA Grand Prix: Fine-Tuning Designs with Advanced Synthesis

Ever watched a Formula One race and wondered what makes the winning car just a little…

• 3 min read
online courses , advanced synthesis , optimization , training bytes , Genus Synthesis Solution , online training
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