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EDPS: Design Process in Milpitas

By Paul McLellan | 24 Sep 2018

For the second year, the Electronic Design Process Symposium (EDPS) took place in Milpitas, having been at Monterey for many years. This was apparently the 25th year EDPS has run. I find EDPS to be a fascinating conference, and I think it is a shame ...

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eda education | deep learning | EDPS
升级到Allegro17.2-2016的10大理由之5：如何层叠

By TeamAllegro | 21 Sep 2018

在这我们谈论的不是您的叠层设计跟其他人比怎么样，而是您设计的PCB层叠结构，是刚性板、柔性板、刚柔板，或者使用了镶嵌技术。层叠的定义，更具体而准确的层叠的定义，是至关重要的。各种材料的安排会影响需要的阻抗控制和减少关键信号串扰的计算和分析，从而影响了最终产品性能。表达真实基材厚度（包括掩模层）的ECAD / MCAD协作对于系统物理建模至关重要，特别是对需要最有效利用空间的最小或最薄的设备。最重要的是，精确的层叠定义将被发送给电路板制造设备，来制造符合设计数据的最终产品。材料镶嵌（点击查看大...

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PCB | Chinese blog | 布线 | PCB设计 | 中文 | MCAD-ECAD | Allegro PCB Editor | Allegro PCB编辑器 | 刚柔结合设计 | Allegro升级17.2 | 刚柔结合 | Allegro
Jaswinder's Only Job Interview

By Paul McLellan | 21 Sep 2018

On Labor day, I didn't get the day off since I was in Delhi. I had to labor, not celebrate it by eating barbecue. Instead, I ate chicken curry, naan, and fried okra at the lunch I had with Jaswinder Ahuja in a conference room. I knew he had ...

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bengaluru | Cadence India | Noida
What's For Breakfast? Video Preview September 24th to 28th 2018

By Paul McLellan | 20 Sep 2018

https://youtu.be/NYsYkQzZADo Coming from SAP Center, San Jose (camera Sean) Monday: EDPS: Design Process in Milpitas Tuesday: CDNLive India: Invecas and FD-SOI Wednesday: RF Design with Cadence and National Instruments Thursday: G...

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National Instruments | GTC | Kaufman Award | EDPS | RF design | Invecas | GlobalFoundries | esd alliance
Samsung Galaxy S9's Application Processor

By Paul McLellan | 20 Sep 2018

At this year's HOT CHIPS, Jeff Rupley of Samsung presented the application processor that goes in their Galaxy S9 and S9+ smartphones. Apple only ever gives cursory information about their Ax chips, and I don't remember seeing a lot of detail...

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Samsung | m3 | 10nm | galaxy