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Data Center

Cadence at Yotta 2026: From Infrastructure Investment to AI Value

The AI industry has entered a new phase. The conversation is no longer all about…

Corporate
• 4 min read
featured , AI Factories , digital twin , Reality Digital Twin

RF /マイクロ波設計

RF 設計のためのエージェント型 AI: より迅速な実行を実現する実践的なアプローチ

Cadence AI によるエンジニアリングの生産性向上に向けたサポートとは RF 設計において最も有用な AI は、エンジニアリングの文脈から切り離された汎用的なアシスタントではありません…

RF Design Japan
• less than a min read
featured , agentic ai , Virtuoso RF , RF design

Cadence Japan

3D-ICおよびヘテロジニアスインテグレーションによる高度なAIスケーリング

AIおよびハイパフォーマンスコンピューティング（HPC）設計が最先端プロセスノードへと進化するにつれて、設計イノベーションは個々のダイの枠を超え、3D-IC技術によって実現されるマルチダイ…

Cadence Japan
• less than a min read
Hetrogenenous , ヘテロジニアスインテグレーション , TSMC Certified design flows HPC , featured , 3D-IC

Corporate News

Accelerate Chip Design with Arm Architecture: Cadence EDA Tools on AWS Graviton

Cadence has qualified its full EDA flow on Arm-based AWS Graviton CPUs, and Annapurna…

Corporate
• 4 min read
news story , Innovus+ Place and Route , Jasper Formal Verification Platform , Cadence Oncloud , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Secure Imaging Starts at the Sensor: Understanding SEP in MIPI CSE v2.0

Secure imaging starts at the sensor. How the SEP protocol in MIPI CSE v2.0 protects…

• 5 min read
MIPI CSE Verification , Verification IP , MIPI Alliance , MIPI CSE , VIP , Camera Security , SEP Protocol Verification , MIPI CSI-2

Data Center

Cadence at Yotta 2026: From Infrastructure Investment to AI Value

The AI industry has entered a new phase. The conversation is no longer all about…

• 4 min read
featured , AI Factories , digital twin , Reality Digital Twin

Verification

Verifying FSED in MIPI CSE v2.0 with Cadence VIP

Automotive camera systems face a threat model that goes beyond packet-level tampering…

• 6 min read
MIPI CSE Verification , Verification IP , FSED Protocol Verification

System, PCB, & Package Design 

Available on Demand: Tackling the Complexity of Next-Generation IC Packaging

Learn how Cadence is addressing the challenges of complex IC packaging design and…

• less than a min read
NEMC , PCB Layout and routing , IC package design

Computational Fluid Dynamics

Professionals in CFD with Iva Papeš from Vertiv

In this special edition of Professionals in CFD , we step outside Cadence to spotlight…

• 7 min read
CFD , data center , Professionals in CFD , Vertiv , WomenAtCadence , women in engineering , Cadence Reality DC Design Software , Women in CFD

Verification

DisplayPort Adaptive-Sync: When Fixed Refresh Rate Is Not Enough

Displays are central to nearly every modern computing experience. Whether we are…

• 4 min read
DisplayPort , EDP , AdaptiveSync

Artificial Intelligence (AI)

What Agentic AI Actually Does in EDA

Electronic design automation (EDA) has always been about turning engineering intent…

• 8 min read
artificial intelligence , agentic ai , LLM , AI in chip design , AI-Driven Design , EDA , AI for design , ai in eda , AI/ML

Digital Design

From Wafer Maps to Yield: Modus Uses Wafer Analytics to Unlock Yield Improvement

Modern semiconductor manufacturing generates enormous amounts of test data. When…

• 2 min read
VLSI , DFT , MBIST , modus , Cadence Online Support , EDA , Semiconductor , cadencetraining , LBIST , diagnostics , Modus ATPG

RF /マイクロ波設計

RF 設計のためのエージェント型 AI: より迅速な実行を実現する実践的なアプローチ

Cadence AI によるエンジニアリングの生産性向上に向けたサポートとは RF 設計において最も有用な AI は、エンジニアリングの文脈から切り離された汎用的なアシスタントではありません…

• less than a min read
featured , agentic ai , Virtuoso RF , RF design

Digital Design

Master ATPG with Modus 26.1: AI-Assisted DFT, Smarter Diagnostics

The world of Design-for-Test continues to evolve, and Modus v26.1 introduces powerful…

• 3 min read
Cadnce , VLSI , DFT , MBIST , EDA , cadencetraining , SiliconDebug , ATPG , diagnostics , Modus ATPG

Verification

AMBA AXI5 MPAM: Control and Visibility for Shared Memory Resources

As modern SoCs become increasingly heterogeneous, the shared memory system has become…

• 6 min read
PMG , PARTID , AXI5 , MPAM , verification

Verification

Why Faster Isn't Always Better: UALink Transmitter Pacing Explained

Imagine two accelerators connected through a UALink link operating at full bandwidth…

• 4 min read
Transmitter Pacing , UALink , verification

Cadence Japan

3D-ICおよびヘテロジニアスインテグレーションによる高度なAIスケーリング

AIおよびハイパフォーマンスコンピューティング（HPC）設計が最先端プロセスノードへと進化するにつれて、設計イノベーションは個々のダイの枠を超え、3D-IC技術によって実現されるマルチダイ…

• less than a min read
Hetrogenenous , ヘテロジニアスインテグレーション , TSMC Certified design flows HPC , featured , 3D-IC , TSMC , マルチフィジックス解析 , japanese blog , AI , TSMC-COUPE

Learning and Support

Unlocking AI-Powered Verification Analytics with Xcelium SimAI App

Unlocking AI-Powered Verification Analytics with Xcelium SimAI App For engineers…

• 1 min read
xcellium , webinar , Cadence training

System, PCB, & Package Design 

AMBA Over UCIe: Building Coherent Multi-Die Systems

While CHI C2C brings coherence and protocol intelligence to multi-die architectures…

• 2 min read
ucie , chiplet , chiplet-based systems , CHI , SoC , MULTI DIE , AMBA

Analog/Custom Design

Spectre MDL: Turn Simulation Results into Reusable Measurements

Running a simulation is only half the job. Engineers must also extract useful measurements…

• 3 min read
Spectre , Custom IC

Analog/Custom Design

From Simulation Data to a Clear Story: Meet the Datasheet Interface 2.0

You have completed several simulations. Now you need to answer a simple question…

• 4 min read
Virtuoso Studio , Virtuoso Analog Design Environment , training bytes , Virtuoso , Custom IC , ADE Assembler

Analog/Custom Design

Virtuoso Studio IC25.1 ISR8 Now Available

Virtuoso Studio IC25.1 ISR8 production release is now available for download.

• 5 min read
IC25.1 , Cadence blogs , Virtuoso Studio , IC Release Announcement blog , IC Release Blog , Custom IC Design

Corporate News

Accelerating AI Silicon Design with AI-Driven Flows

AI silicon complexity is rising faster than engineering teams can scale with traditional…

• 4 min read
CDNS - Fix Layout Hompage