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It's Friday meaning it's time for another roundup of CFD news and detritus from the internet. Three highlights to whet your appetite: An article about automobile design makes the point that they are now complex systems versus not t...

It's only September 24, but this is the last Friday of the month so it's time for my monthly update. This month: ransomware, Apple's new A15 chip, the US government and zero trust, plus more Designed with Cadence videos. Ransomware Ransom...

The Team RF "μWaveRiders" blog series is a showcase for Cadence AWR RF products. Monthly topics will vary between Cadence AWR Design Environment release highlights, feature videos, Cadence Academic Network news (now includes the former A...

CadenceLIVE Europe is on October 19 and will be a digital event. Let me give you a preview of what is coming up and some reasons to attend. As usual, there are keynotes, technical updates, presentations mainly by customers, an expo...and even giveawa...

AWR Design Environment V16 产品版本已上线并可从 Cadence Downloads 网页下载，其中包含以下和其它增强功能

This morning Cadence announced the release of the Helium Virtual and Hybrid Studio. This is a next-generation engine for hardware/software co-verification and debug. The full virtual model provides the highest performance for software development and...

The concept of Trusted Execution Environments (TEE) was developed in the early 2000s to standardize key encryptions, end-to-end security and authenticity, and confidentiality of devices in a system. With the increase in computing and connected devices due to IoT, there are large number of applications...

The Basics of CFD in 8 Weeks - Free Online Course Learn the basics of CFD in eight classes across eight weeks and gain hands-on experience using commercial, flow-simulation software! Lasting approx. 45 minutes per class, take part in each ...

Placing component leads accurately as per the datasheet is an important task while creating a package footprint symbol. As the pin pitch goes down, the size and location of the component lead play a crucial role in the assembly of the components. The...

As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality . Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose secure information like decryption keys were found only...

Politico is not usually a place I go for material for this blog, but recently it had a Politico Tech Summit called At a Digital Crossroads. One session was sponsored by Micron (I think that's how it works) and featured the chairwom...

As it seems to be becoming a (bad) habit, This Week in CFD is presented here as Last Week in CFD. But that doesn't make the news any less relevant. Great article on wind tunnels because they go hand-in-glove with CFD. Monica Schnitger (who you r...

When you achieve the credit for proficiency, do you want to show it to the world? We know it isn’t easy to carry the actual physical badge (certificate) everywhere today. Why? Expenses, pandemic, making a list where to travel, to whom to show etc. Don’t worry! We have an easy and cost-free solution...

In my post about the big trends from this year's HOT CHIPS, I mentioned a paper from ISCA written by a group of people from Google. The paper is not actually titled exactly as in the title to this blog post, it is actually Ten Lessons From Three ...

The Cadence Scholarship Program is the flagship CSR program of Cadence India, introduced five years ago. Many meritorious students from under-served sections of society drop out of the education system after school because of the lack of finances. Th...

https://youtu.be/LuFCfy3aNbI Made with Lumen5 by me Monday: On-Device Artificial Intelligence the Tensilica Way Tuesday: How to Build a Data Center: It's All About the SerDes...and Thermal Wednesday: Pegasus Flies into the GF Technology Summ...

A guest blog to take your focus away from normal news and feature information that you are accustomed to reading about in the world of PCB Design blogs to let you know about Cadence’s recent ventures into the world of Computational Fluid Dynamics.

Two big trends that are no surprise, they were big at HOT CHIPS last year and for other events like the Linley Processor Conferences, are every processor is an AI processor, and increasingly most processors are using some form of advanced packaging. ...

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CadenceLIVE, Cadence’s annual user conference, has been a great platform for Cadence technology users, developers, and industry experts to connect, share ideas and best practices solve design challenges, and inspire design creativity. This...

This Blog shows how the Virtuoso Module Generators provide a way to generate multiple Pcell instances into a complex, highly matched, structured array and how you can control the routing style and generate internal routing geometry. In addition, you get an insight into Floorplanner that consists of automatic...

Today, I'm covering two of the biggest chips presented at the recent HOT CHIPS. Ponte Vecchio, Intel's enormous graphics chip intended to be used in Argonne National Laboratories' supercomputer Aurora. And the latest developments from Cer...

Today is the GF Technology Summit, what used to be called GTC in previous years. GF is, of course, GlobalFoundries. We also announced this morning that the Pegasus Verification System has been certified by GF on its 12LP, 12LP+, and 22FDX processes. ...

本記事は 2021年8月のMicrowave Product Digestに投稿した記事 を翻訳したものです。 RF系および部品の設計からCadence VSSおよびRohde＆Schwarz VSESIM-VSSソフトウェアを使用した実装まで by Dr.Gent Paparisto and David Vye, Cadence and Markus Loerner, Rohde & Schwarz 　 　電子設計自動化（EDA）ソフトウェアを使用した解析は、...

I came across a question on a social media site about how to know when the absolute maximum ratings for a component have been exceeded? In other words, how do you identify components that are stressed due to power dissipation, increase in junction te...