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For the third time*, I find myself writing the obligatory, "Hello, World!" first blog post. So "Hello" to all you readers of Cadence's Computational Fluid Dynamics blog. (Or as someone else put it, Cadence Fluid Dynamics.) Who...

Timing closure is one of the most crucial steps of a digital design. Therefore, to meet timing at the later stages of design signoff, it is imperative to consider timing analysis within the synthesis stage. We know real designs are complex, and so is the timing analysis. Unfortunately, we cannot reduce...

https://youtu.be/1HEd6JCriCQ Made in Groveland CA (camera Carey Guo) Monday: Package Assembly Design Kits Tuesday: Rapid Adoption of the Arm Server-Class Processors Wednesday: Arm V9A Thursday: Offtopic: Miniatur Wunderland Friday: no post Featured P...

In today's ever-shrinking IC Package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle. Layout engineers want a quick and accurate way to ...

Tomorrow and Monday are Cadence Global Holidays. Of course, May 1 is a holiday anyway, in much of the world (China takes the whole week, and it is a holiday in India and Indonesia too—so that gets you a lot of the way there). I am actually taki...