Cadence Community

Whiteboard Wednesdays – The Storage Combo PHY IP – Nirvana!

By Corrie Callenbach | 23 Jul 2019

In this week’s Whiteboard Wednesdays video, Jacek Duda describes three storage protocols and announces that you only need one PHY IP to support xSPI, ONFI 4.x and SD standards! https://youtu.be/cVi4FEpfpY4

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Whiteboard Wednesdays | PHY IP | ONFI 4.x
Virtuoso Meets Maxwell

By Paul McLellan | 23 Jul 2019

When I was a postgraduate at Edinburgh University, my office was in the James Clerk Maxwell Building, the JCMB. Maxwell was most famous for Maxwell's Equations, which give the rules for how electrical and magnetic forces interact, and how electro...

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RF | maxwell | Virtuoso
IC Packagers: Correcting Die Orientations and Die Attachments

By Tyler | 23 Jul 2019

When you add a die component to your SiP Layout design, you must identify both its default attachment type – wire bond or flip-chip – and its orientation – chip up or down. But, what happens if you get this wrong? The most common re...

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APD | SiP Layout
Virtuosity: 我的 Checks 通过还是没有运行？

By AdityaMainkar | 22 Jul 2019

今天的博客重点介绍 Checks/Asserts 结果显示和 Summary 表。这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分，以涵盖 Virtuoso®ADE Assembler ， Virtuoso®ADE Explorer 和 Virtuoso® Visualization and Analysis 中刚刚发布的功能。请继续关注更多此类有趣的博客。如果您曾尝试在 Virtuoso® ADE Assembler 和&...

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Chinese blog | ADE Explorer | Virtuosity | Custom IC Design | ADE Assembler
Tales from DAC: MediaTek's Experience with Spectre X Simulator

By XTeam | 22 Jul 2019

MediaTek recently gave the new Spectre X Simulator a try, and they talked about their experiences with it at DAC 2019 in a presentation given by YY Chen in the Cadence Theater. Spoiler alert: they loved it. MediaTek is the fourth largest fabless IC design company in the world, and they’re ranked...

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Cadence Theater | DAC 2019 | mediatek | spectre x