Cadence Blogs

I recently talked to Ashish Darbari, the CEO of Axiomise. They are based in London, where Ashish ended up having bounced around the world. But more of that later. I also discovered that he would be presenting at CadenceLIVE In Munich the followi...

Modern electronic designs have many stakeholders involved in the process. It is not uncommon for schematic drawing and pre-design simulation to be done in-house while the layout is handled by a third-party design partner. Allegro® Pulse not only ...

System Analysis Knowledge Bytesブログシリーズでは、Cadence®が提供するシステム解析ツールの機能と可能性について説明しています。 このシリーズは、この分野での役立つ機能等に関する学識を提供することに加えて、システム解析に関連する知識と経験を共有するブロガーと専門家の意見を広くお伝えすることを目的としています。   正確なSI/PI解析は、重大な設計問題の特定と解決、コストのかかる再設計の防止、サイクル時間の短縮、および製品性能の向上に役立つ...

AIスタートアップ企業のEnflame Technology社のエンジニアリング・チームは、Cadence LIVE China 2022でHBMメモリ・スタックと自社AIベースのチップ設計との間で、1700を超える信号をシリコン基板上で接続するシリコン・インターポーザ設計の課題をどのように克服したかを明らかにしました。   この議論には、データ転送速度2.0 GHzから7.2 GHz までのHBMインターフェイス規格が含まれています。   ケイデンスのアプリケーション・エン...

It's a new week in CFD and time to refresh our memories about what's going on here at Cadence Fidelity CFD. From The Blogs Cadence and McLaren Accelerate Innovation During a recent visit to the Cadence office in Austin, Texas, McLaren CEO Za...

Electronic design automation (EDA) has been experiencing a renaissance of sorts, breaking new ground in broader markets that focus on the computational (mathematical/data-driven) aspects of intelligent system design. While the industry has long playe...

CadenceLIVE Europe took place on Monday and Tuesday at the start of Thanksgiving week in Munich, Germany. It was in-person for the first time in three years. There were about 550 people there, maximum capacity. As in the past, the first day starts at...

Cadence® Perspec  System Verifier is a portable stimulus, system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for defining complex SoC-level use cases and amplifying use case exploration of state space and timing on fast platforms. It also helps to create coverage-driven automation of system use-case generation, bridging UVM and…

An optimization-based smoothing technique in Fidelity Pointwise promises to accurately resolve the boundary layers in a viscous flow by extruding a mix of prisms and hexahedra.

A picture tells more than a thousand words, so here are some pictures of CadenceLIVE Europe 2023 Academic and Entrepreneur Tracks to tell a story. After two years of absence, finally the Academic Dinner could take place with professors from Lead Ins...

It's time for one of my occasional travel guides, this time to Munich. For previous guides, see: The Breakfast Bytes Guide to Flying Breakfast Bytes Guide to Armenia Breakfast Bytes Guide to Japan Travel My Visits I have been to Munich literally do...

Life is a journey that gives us a series of beautiful memories. The roads we travel determine our life’s path. A new chapter of my life began when I relocated to Cork with my family, leaving behind many things, including the Cadence Noida office, where I spent a good part of my professional life, but looking forward to embracing a wholly unique experience.

With the roads flooded with electric vehicles worldwide, it is on us to give EV batteries a second life, which would count as an effort to reduce e-waste and achieve the net zero emission targets set by policymakers.

Raspberry Pi are known for providing lost-cost computing around the world. Their computers have been used by schools, small businesses, and even government call centers. One of their missions is to educate children about computers and to help them re...

Today is a very significant anniversary for the whole of the human race. But if you are reading Breakfast Bytes, it is especially important for whatever you do. Today is the 75th anniversary of the invention of the transistor. There is actually no p...

Test points are placed on a PCB during the design process to ensure (some might say ‘test’) that the design performs as intended and provides the desired output. Test points also help ensure that the integrity of the component assembly pr...

人工智慧、HPC等應用如雨後春筍般出現，晶片尺寸與規模越來越大、設計規範亦越來越複雜，因應系統及全晶片層級的設計挑戰，Cadence解決方案也顯現高度整合與智慧化的發展趨勢，針對設計到簽核收斂的完整設計工具與整合流程，進一步推出業界首創的全晶片同步優化簽核 - Certus設計收斂方案。 擘劃並引領Cadence數位與簽核事業群的研發方向、目前擔任Cadence資深副總裁暨數位與簽核事業群總經理的滕晉慶(Chin-Chi Teng)博士，日前來台與台灣媒體共同探討Cadence最新數位設計趨勢、...

Cadence and our employees were proud to show appreciation for our Veteran employees, their families, and all who have served the United States this Veterans Day. Honoring our military's personnel, Cadence observed Veterans Day as a holiday in the U.S...

Hi, I’m Samuel Afari and I’m a CFD Applications Engineering Intern at Cadence. I am currently a PhD candidate at Embry-Riddle Aeronautical University in Daytona Beach, Florida. I also did my MSc in Aerospace Engineering at the same school...

One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated. Suddenly, both "Systems designers" and "Hardware de...

Today is the last day in November, amazingly, and since I was on vacation last Friday, today is my regular monthly update covering topics that don't justify a whole post on their own or that are updates to a previously published post. Kaufman Din...

聯電射頻晶圓設計套件(RF FDK)和Cadence RF方案協助其共同客戶 - 聚睿電子達成卓越 5G 射頻設計成果 Cadence與聯電宣布雙方合作經認證的毫米波參考流程，成功協助亞洲射頻IP設計的領導廠商聚睿電子(Gear Radio Electronics)，在聯電28HPC+ 製程技術以及Cadence® 射頻(RF)解決方案的架構下，達成低噪音放大器 (LNA) IC一次完成矽晶設計(first-pass silicon success) 的非凡成果。 經驗證的聯電28HP...

Smart manufacturing – the use of nascent technology within the industrial Internet of things (IIoT) to address traditional manufacturing challenges – is leading a supply chain revolution, resulting in smart, connected, and intelligent env...

Join Cadence Training and Principal Application Engineer Daniel Bayer for this free technical training webinar.

The Verisium Debug Platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must.

In this Training Webinar, you’ll learn how to automate your debug experience using the Verisium Debug…

I’m back again, it has been a while, but guess what… I have a lot of goodies to share with you. Since last time I posted a blog, our Virtuoso System Design solutions have gone through a lot of enhancements, and more automations have been accomplished. You may already have read our blog, Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution, which covers how you can bring your existing SiP design…