Cadence Community

Whiteboard Wednesdays – What is Happening at the USB IF Standards Meetings?

By Corrie Callenbach | 16 Jul 2019

In this week’s Whiteboard Wednesdays video, Jacek Duda talks about the next-generation standard, USB4. What are the benefits? Overlap with existing USB standards? How does it compare with USB 3.x? Watch the video. https://youtu.be/sKHF8xB-NBk

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Whiteboard Wednesdays | USB
IC Packagers: Bend in Both Directions with J-Loop Bond Wires

By Tyler | 16 Jul 2019

Let’s talk about wire bonding for a quick minute. Still a favorite for many of you, bonding is a cheap way to connect your die to the top layer of your package (or to a lead frame, if that’s what you’re using). A 3D wire is connecte...

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IC Packaging | APD | SiP Layout
GLOBALFOUNDRIES After the Pivot

By Paul McLellan | 16 Jul 2019

At SEMICON West I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to get an update on what is going on since the “pivot”. The Pivot The pivot was the decision last year to pull back from 7nm and EUV development and focus their process ...

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globalfound | semicon | 22fdx | 12fdx | FD-SOI
Cadence and the Expanding Presence of Women in Tech Conferences

By MeeraC | 15 Jul 2019

Cadence sponsors several different tech conferences throughout the year. We use these events as an opportunity to allow employees to take a day out of our normal work routine to network, learn, and develop as leaders—but more importantly, so we...

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Insights on Culture | Culture | STEM | IEEE WIE ILC | women | VerveCon | diversity
Is the Role of Test Chips Changing at Advanced Foundry Nodes?

By TomWong | 15 Jul 2019

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping...

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Design IP | IP | cadence | PCIe Gen4 | IP integration | ip cores | Ethernet | semiconductor IP | PCI Express