Community

More package designers these days, with the increasing component counts and more complicated electrical constraints, are shifting to using a front-end schematic capture tool. As with IC and PCB design, this allows for verification between the logical...

A lot of EDA and IP is increasingly based around standards. As a result, Cadence is actively participating in and contributing to standards bodies such as IEEE, JEDEC, Accellera, and Si2 to name a few. Here are the most recent standards that we have ...

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 ブログメータ...

Cadence Education Services have released our latest advanced UVM Training Byte (TB) video on support.cadence.com . This TB covers issues when migrating to UVM-IEEE. UVM is the dominant testbench methodology for ASIC and IC design. For many years UVM w...

At the recent Arm DevSummit, one of the presentations mentioned CHERI and the Arm Morello board in passing. This was in the context of using capabilities (perhaps) in some future Arm processors to increase the amount of memory safety, and to protect ...