Cadence Community

The Art of Analog Design Part 6: Response to Frank’s Question to Part 4

By Arthur Schaldenbrand | 23 Oct 2017

In the comments to blog #4, Frank Wiedmann asked about the correlation between the results of mismatch from Monte Carlo analysis and DC mismatch analysis. It is a fair question and here is a short blog to explore the topic. The example may not be realistic, but it is a useful for exploring the effects...

1 Comments

TAGS:

spectre aps | Virtuoso Variation Option | ADE Explorer | mismatch analysis | Analog Simulation | Monte Carlo analysis | DC Mismatch | Custom IC Design
Putting the Bad Guys in an Arm Lock

By Paul McLellan | 23 Oct 2017

This morning Arm announced their Platform Security Architecture (PSA), a new way of protecting our ever expanding connected world. This is intended for all Arm-based devices from the lowest cost microcontrollers on up. There is a particular focus on IoT devices, since they will be the most numerous and...

0 Comments

TAGS:

security | ARM Techcon | mirai | platform security architecture | psa | ARM | Breakfast Bytes | Techcon
Education, Occupation, and You: Vishal Kapoor at SJSU

By Paul McLellan | 20 Oct 2017

Earlier this week, Jim Hogan hosted the next evening at San Jose State University on Preparing for the Cognitive Era , with Vishal Kapoor. If you work at or deal with Cadence, and his name seems familiar, that's because he worked at Cadence from 2003 to 2012 in several senior positions. Most recently...

0 Comments

TAGS:

san jose state university | vishal kapoor | san jose state | cognitive science | cognitive era | sjsu | Breakfast Bytes
What's For Breakfast? Video Preview October 23rd to 27th 2017

By Paul McLellan | 19 Oct 2017

(Please visit the site to view this video) Coming from SJSU Theater (camera Sean) Monday: Arm Announcement (embargoed) Tuesday: Cadence Announcement (embargoed) Wednesday: Why Was Arm Successful in Mobile? Thursday: Oski Formal Verification Club (with Arm and Arteris) Friday: Post...

0 Comments

TAGS:

ARM Techcon | formal | Arteris | mobile | ARM | Formal verification
Mark Papermaster: Moore's Law Plus

By Paul McLellan | 19 Oct 2017

Recently, I wrote about Robert Lang's presentation on Computational Origami . He was a real paper master. The CTO of AMD is Mark Papermaster, although I think he is more of a silicon master than a paper master. At SEMI's strategic materials conference, he gave the opening keynote, The Future...

0 Comments

TAGS:

epyc | has | chiplets | rocm | AMD | 3DIC | 2.5D IC | Breakfast Bytes