Cadence Community

DATA Pulse: Simplify Your ECAD Data Release Process While Ensuring Process Control

By Auromala | 22 Jan 2020

Do you dread your ECAD to PLM publishing process? If yes, worry not. We have a solution.

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System Capture | allegro edm | PCB design | Pulse | PLM
IEDM: Automating DTCO for 3nm

By Paul McLellan | 22 Jan 2020

At IEDM in December, Lars Liebmann of TEL presented Design Technology Co-Optimization for 3nm and Beyond. The challenge in designing a modern process is that scaling is no longer based on incremental change purely at the process level. Design Te...

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3nm | IEDM | DTCO
Virtuosity：Modgen中的布局重用流程

By Aneesh Shastry | 21 Jan 2020

Modgen 现在支持布局重用流. 请继续阅读，了解如何使用此功能通过减少创建 Modgen 的时间和精力来提高版图效率.

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Chinese blog | Modgen On Canvas | ICADVM18.1 | MODGEN | Layout Suite | Layout | Virtuoso | Virtuosity | Layout design | Custom IC Design | modgens | Virtuoso Layout Suite | Custom IC
IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

By Tyler | 21 Jan 2020

When you need to make an edit to a component, whether that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability changes back to the IC design team, there ar...

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Allegro Package Designer
A Big Problem with Big Data

By Paul McLellan | 21 Jan 2020

I happened to read a blog post that referred to a 2018 paper in The Annals of Applied Statistics with the title Statistical Paradises and Paradoxes in Big Data: Law of Large Populations, Big Data Paradox, and the 2016 Presidential Election . The ...

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deep learning | big data