Verification(Verification of System and Software) Blogs

Cadence® Perspec  System Verifier is a portable stimulus, system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for defining complex SoC-level use cases and amplifying use case exploration of state space and timing on fast platforms. It also helps to create coverage-driven automation of system use-case generation, bridging UVM and…

One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated. Suddenly, both "Systems designers" and "Hardware de...

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The Verisium Debug Platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must.

In this Training Webinar, you’ll learn how to automate your debug experience using the Verisium Debug…

High-end SOC architectures today requiring more area and higher speed to transfer and process data. To fulfill this requirement, protocol such as PCIe, USB, DP, SATA and USB4 are regularly being updated. Most critical part of the high-speed interface is the Physical (PHY) layer of the protocol where the actual signaling happens. In addition to signaling, the PHY also takes care of some of the processing to reduce errors…

The automotive world is conquering new technological heights, piggybacking on advanced semiconductor components. A typical vehicle has around 1,400 semiconductor components, and the numbers are expected to go higher as vehicles become more intelligent and autonomous. The ecosystem change in the automotive world has mutated the demand patterns for automotive chips, resulting in the growing demand for purpose-driven applications…

With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to-zero) to PAM4 (4-Level Pulse Amplitude Modulation) is no surprise. To address the Nyquist frequency issues at 64GT/s, which doubles to 32GHz which further causes frequency dependent loss increased to 70dB, PAM4 was introduced. 

Use of PAM4 signaling address the issues related to integrity, channel loss and backward compatibility but increased…

PCIe designed system fabrics rely on software enumeration by Operating System (OS) for device discovery. CXL 2.0 device is exposed as PCIe native endpoint and CXL 1.1 is exposed as root complex integrated endpoints (RCiEP) during software enumeration process. Notably, there is a difference between the discovery of CXL 1.1 versus the CXL 2.0 device. Hence, the configuration space for CXL1.1 and CXL 2.0 varies. In this…

USB4 is an industry standard that tunnels three different protocol specifications (PCIe, USB3 and DisplayPort) serially to a destination. DisplayPort (DP) tunneling over USB4 means DP protocol packets are converted into USB4 protocol packets and transferred over its fabric to a destination. Before the USB4 router sends the packets to its destination, they are converted back to DP protocol packets. In sum and substance…

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology since then. With the doubling of the bandwidth from 8 GT/s to 16 GT/s per Lane in formulating the PCIe 4.0 specifications, there arises the need-to-know overall link health as channels are pushed near operating limits by frequency doubling. By link health I mean -how much signaling margin is available in the design to squeeze out full…

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This specification enables up to 80 Gbps link speed per direction in symmetric mode, and up to 120 Gbps link speed in asymmetric mode. It has new feature capabilities in almost all the layers of the USB4 Version 1.0 specification, focus being on how to tunnel and transmit the data faster.

Some important feature updates in it are listed below…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol that makes use of the PCIe PHY layer. It may be chosen to run the PCIe protocol in addition to one or multiple alternate protocols in the alternate protocol mode. This is negotiated by the link partners during Configuration LTSSM states while communicating their own capabilities with each other. For the CXL protocol, the same outline is utilized…

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen-Z transfer specification and assets to CXL Consortium. In August, the next full version of the CXL 3.0 standard was announced. With the continued proliferation of cloud computing, AI and analytics, increasing need for system-level optimization among high performance accelerators, system memory, smart NICs and leading edge networking. The…

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.  

Amongst many new features and changes in PCIe 6.0…

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.  

Amongst many new features and changes in PCIe 6.0, we will…

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.  

Amongst many new features and changes in PCIe 6.0…

Media Independent Interface Management (MIIM), or Management Data Input/Output (MDIO), is a serial bus protocol and is used for the IEEE 802.3 Ethernet standard and Media Independent Interface (MII). The MIIM/MDIO protocol is a simple two-wire serial interface with specific terminology to define the various devices on the bus. The device driving the MDIO bus is identified as the Station Management Entity (STA). The STA…

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification, which will enable up to 80 Gbps operation over the USB Type-C® cable and connector.

As per this announcement, the key characteristics of the updated USB4 solution include: 

• Up to 80 Gbps operation, based on a new physical layer architecture, using existing 40 Gbps USB Type-C passive cables and newly-defined 80 Gbps USB…

Functional verification consumes more than 70% of the labor invested in today’s SoC designs. Yet, even with such a large investment in verification, there’s more risk of functional failure at tape out than ever before. The primary reason is that the design team does not know where they are, in terms of functional correctness, relative to the tape-out goal. Coverage Closure in SoC verification is like chasing a mirage…

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt  products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3…

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and…

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication…

NAND Flash memory is now a widely accepted non-volatile memory in many application areas for data storage such as digital cameras, USB drive, SSD and smartphones. One form of NAND flash memory, Toggle NAND, was introduced to transmit high-speed data asynchronously thus consuming less power and increasing the density of the NAND flash device. 

The initial Toggle NAND versions had memory arranged in terms of SLC (Single Level…

It has become challenging to ensure that the designs are complete, correct, and adhere to necessary coding rules before handing them off for RTL verification and implementation. RTL Designer Signoff Solution from Cadence helps the user identify RTL bugs at a very early development stage, saving a lot of effort and cost for the design and verification team. Our reputed customers have confirmed that using RTL signoff for…

Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity. 

UFS is…

Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that ar...