Functional Verification Blogs

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the industry. TileLink is a free and open standard chip-scale interconnect protocol designed for RISC-V processors and beyond (could be used with other ISAs as well). It’s a fast scalable SoC communication protocol designed to connect...

All the workings of USB4 protocol are primarily about how to transfer the native protocol data through tunneling from their originating points to respective destinations. One may verify thoroughly the core layers, like logical layer and transport layer, of a USB4 design. But that is only half the job done. The next challenge comes up at verifying the tunneling of each native protocol, which are USB3, PCIe, and DisplayPort...

It won’t be incorrect to say that the transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services like paths and routing for tunneled traffic, various types of flow control, link management, which are some of the core features that make a USB4 router work the way it should. A path is like a virtual wire, which is a unidirectional...

Using Cadence ® Specman ® Elite macros lets you extend the e language ─ i.e. invent your own syntax. Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and some are very advanced utilities implementing sophisticated methodologies. With macros, you can replace long complex user code with much shorter and simpler code. And, as we know – the shorter the code is, the less...

To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies supported by its latest low power memory offering LPDDR5 to include the 937MHz and 1066MHz that translates to the max data rates of 7500MT/s and 8533 MT/s. Devices supporting these incredibly high data rates are being categorized...

Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer and non-transparent Link Training-Tunable PHY Repeater (LTTPR) device when connected. The diagram below shows the connection between the source, LTTPRs, and sink devices. The specification allows up to eight LTTPRs....

Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low form factor memory devices to process data temporarily to gain widespread adoption in the market place. HyperRam memory has all above characteristics to improve performance of end devices. The HyperRam device is the high...

RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as possible—to reduce the cost per bug—which puts additional pressure on designers. Conventional methods of design bring-up using unit-level testbenches are no longer the optimal way to address these challenges. Design teams...

Memory is an important part of every electronic system, still it is increasingly becoming a performance bottleneck. While NAND flash is primarily important in consumer and computing applications, there was no standard to help designers integrate NAND...

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to...

RTL designers are creating increasingly complex designs, and are under relentless pressure to provide assurance that the designs are complete and correct, before handing off the designs for RTL verification and implementation. This assurance needs to be provided at the block/IP level as those become mature enough for handoff, and again once the design is integrated to subsystem or chip level. Recently, the multitude...

As a verification engineer, you want your toolbox to be varied and rich. It looks trivial, but if we really ask ourselves why, there are several reasons. First , when you look for your next exciting verification position, the more HVL you know, the more options you have. In addition, you reflect yourself as a knowledgeable person for potential employers. Secondly , familiarity with several HVL, makes you a better verification...

We’re proud to see that many expert verification teams exploit the powers of UVM vr_ad, in implementing intricate verification environments in e . The vr_ad is an open source package, part of UVM- e . It provides means to access the DUT registers and memory, monitor the accesses and check the DUT registers behavior. It is indeed a flexible powerful utility. But with power comes responsibility. During the verification...

If you’re looking for an example of how well the Cadence flow fits together, look no further than Renesas and their experience using the Cadence System Testbench Generator and System Performance Analyzer alongside Perspec and Palladium. With development time requirements shrinking while designs grow, verification engineers and chip designers need access to every advantage they can get, and there’s few ways you can improve...

Asynchronous designs happen. They’re not particularly easy to verify, but sometimes they’re necessary. If you don’t have a system clock, or if you have controllers that operate at a high speed with low power dissipation, or even if you do have a system clock but it’s noisy, your design may be asynchronous, and that’s okay. It’s no secret that asynchronous designs are a challenge —so what can you do to make sure they...

If you’re not familiar with the Arm/Cadence collaboration , you’ve been missing out. Arm has been using Cadence’s virtual system platform—Palladium ® Z1 for emulation and Protium S1 for prototyping—for years, and with these, Arm powers their wide array of fast models for virtual prototyping to make the emulation process even faster than it already is. Interested? Well, it’s no secret that virtual prototyping is the...

Looking to learn more about the best practices for emulating today’s billion-gate-plus designs? Rest assured—we’ve got you covered. Cadence has been partnered with Nvidia Mellanox for years, helping them build complete end-to-end solutions for everything from networking to data centers. Mellanox provides and handles every aspect of the process , and they’ve got a long track record of delivering breakthrough technology...

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic Simulator has a new feature just for you. Harnessing the power of machine learning, which is one of the areas of computational software innovation, Xcelium ML is here to help you optimize your regressions. The inherently iterative, data-driven nature of simulation seems ripe for a machine-learning assisted tool, and Xcelium ML is here...

UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology in our current industry. With the growing use of UVM methodology, engineers need to have an in-depth knowledge. For someone getting started with UVM, it can be challenging and a steep learning curve. So, we offer a comprehensive and adaptable course SystemVerilog Accelerated Verification with UVM to sharpen your UVM skills . This...

I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor whom I could ask all my queries. But most of the time, I was on my own, as "learning by doing" was the motto of my mentor. Today, after completing 20 years at Cadence, I can tell you that it works great, especially in cases where the tool...

In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using-coverage-callback - we shared some ideas about how to employ the new Coverage Callback API for increasing the tests efficiency. This blog shows two more ideas for improving tests, using runtime coverage information. Stop the Run After the Goal Is Reached The basic concept of Coverage Driven Verification is running many random tests...

Most have heard the phrase "time is money". Thinking more about it, probably the right phrase would be "time is more valuable than money". People look at their bank accounts with great attention but don't tend to look at their time the same way, ending up wasting this greatly valuable and important resource. You can gain money using time, but you can’t use money to purchase more time. The “Shift Left” concept has been...

When you go to the store, you walk until you get there, stop, get your groceries, and go back home. You do not start circling around the block for few rounds. You do not say “if I walk around the block really fast, I can save time”. It is clear that if you avoid circling the block at first place – you will save even more time. Why don’t we adopt the same rationale in the verification process? Instead of thinking just...

As the de facto IO interconnect technology, PCIe has commendably addressed the performance bottleneck at the IO interface by doubling the bandwidth support every 3-4 years over the course of 5 generations of the specification and with Gen 6 at 64GT/s in the works. However, the datafication of everything requires that the raw data be processed and/or harvested for meaningful information. The high computational workloads...

Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE in Dec 2019. This draft provided the standardization of higher lane speed support for backplane systems, including 3 speed mode variations: 100G, 200G, and 400G. Backplane Ethernet speed is increasing, evolving from 10G, 25G, 50G, to current 100G on a single SerDes lane within less than 10 years, offering unprecedented capacity for the datacenter...