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Is it Time to Verify Your Chips in the Cloud? Part 3 of 3

By XTeam | 28 Jun 2018

Welcome back to our series on cloud verification solutions. This is the final part of a three-part blog—you can read part one here and part two here . Now, for the moment you’ve all been waiting for: what can Cadence do for you in the realm of cloud verification. Are you ready? In case you saw that list of qualities one should look for in a cloud partner in the last part of this blog, and wondered who ticks all those...

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security | Functional Verification | cadence cloud | xcelium | palladium cloud
UVM-ML- Managers’ Freedom of Choice

By teamspecman | 28 Jun 2018

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is defined in wikipedia as “an individual's opportunity and autonomy to perform an action selected from at least two available options…”. Is having many choices always a good thing? Well, usually it is- who would not want to live in a world where s/he has options and can make choices? However, there are also downsides to having multiple...

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Specman | Specman/e | UVM-ML | Specman e | UVM multi-language | UVM-e | UVM ML | multi-language | multi-language UVM | multi-language verification | verification
Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

By XTeam | 21 Jun 2018

Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here . The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020—that’s an annual growth rate of almost 20%. Cloud providers and other related companies are putting more and more resources into building solutions for this...

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uvm | Functional Verification | EDA | HPC | cadence cloud
App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog Data Structures

By XTeam | 21 Jun 2018

Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerilog. [link to app note here]. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t...

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SystemVerilog | Tip | Functional Verification | App Note Spotlight
Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

By XTeam | 15 Jun 2018

Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud. For a while now, there’s been a growing interest in cloud-based EDA solutions, but the time wasn’t ripe for production deployment. People had concerns about security and the sustainability of the data centers. But nowadays, public clouds are highly secure, typically more secure...

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cloud-based verification | Functional Verification | cadence cloud | cloud computing
DMS 2.0 - What's Cool and What's New

By XTeam | 11 Jun 2018

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and wonderful features to help you use Xcelium to verify your mixed-signal designs. The level of interaction between analog structures and digital logic is a lot more complex than it used to be. Divide-and-conquer verification isn...

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digital mixed signal | Functional Verification | DMS 2.0 | xcelium simulator
Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

By XTeam | 7 Jun 2018

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April 2018. One of the fields Microsemi operates in is the realm of optical networking. In optics, a given sensor’s input can vary wildly, but the way the input is processed is largely the same. Thus, a wide variety of tests are...

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SystemVerilog | uvm | Dynamic Test Load | Functional Verification | xcelium
RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs

By XTeam | 5 Jun 2018

The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to verify one of the most critical technology convergences in IoT devices. It’ll talk about the differences in verification of a processor-based design whether it’s powered internally or externally, how to verify SPICE, SystemVerilog...

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Low Power | Functional Verification | RAK | power intent | mixed signal
App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog Semantics

By XTeam | 4 Jun 2018

Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator...

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performance | SystemVerilog | Functional Verification | xcelium simulator
Empowering Generation - Range Generated Fields (RGF)

By teamspecman | 31 May 2018

Specman constraints solver process consists of a series of reductions and assignments . It reduces the range of the field value based on the constraints, and then assigns to it a random value from the reduced range. After assigning one field, the range of all connected fields is reduced accordingly, and the process continues until all fields are assigned. A new feature added in Specman 18.03 – Range Generated Fields...

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Specman | Specman/e | Generation | e language | Constraints
Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress, and HyperRAM

By XTeam | 3 May 2018

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM high-speed memory. We also unveiled a new JEDEC Universal Flash Storage 3.0 (UFS) VIP. Together, these three new VIPs allow early-adopters to leap off the starting line in the race to create new, incredible SoCs and IPs incorporating...

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hyperRAM | Functional Verification | coaxpress | UFS | press release
Xcelium's New Save and Restart Saves You Time

By XTeam | 5 Apr 2018

You may have heard about the overhaul to the old save/restart mechanism that was in Incisive—but are you aware of what the new Xcelium Simulator version can do? While the old version is still supported, there’s a lot of benefits to shifting to the new one. Now called “checkpointing,” this new system uses a process-based implementation and is overviewed in the app note, Using Save/Restart Checkpointing with Xcelium...

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save and restart | xcelium | save and restore | checkpointing
List of TLM Analysis Ports: Where Is This Packet Coming From?

By teamspecman | 1 Apr 2018

Let’s say that you got an invitation from the police station nearest your home to be there the next day at 14:00. Hmm…. What could it be about? You check the letter and envelope for more information, but it does not say which department sent it. Well, it makes a big difference if the invitation was from the “lost and found” department, which means you will probably get something back, or if it came from “investigations...

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Specman | Functional Verification | e | e language | team specman | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part I

By XTeam | 19 Mar 2018

Welcome to a special multi-part edition of the App Note Spotlight, where we’ll be highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerliog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator—in fact, they...

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SystemVerilog | Object Oriented Programming | Functional Verification | Optimize
Temporals, Reset, and Test Phases

By teamspecman | 11 Mar 2018

One of the biggest challenges in dynamic functional verification is testing Reset – resetting the DUT during simulation and check DUT operation afterwards. The main challenges are propagating the reset information in the testbench, and adjusting the components behavior. For performance and accuracy, it is best to have one agent controlling and monitoring the reset, rather than each and every agent monitoring the reset...

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Specman | UVM e | Specman e | e | e language
App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For You

By XTeam | 6 Mar 2018

Welcome to another App Note Spotlight! One of the biggest issues facing verification engineers is the question of reducing elaboration time. Using incremental elaboration (MSIE) can greatly reduce that time—but that raises a new question: between the two MSIE flows, which one is right for you? Those two MSIE flows are single-xrun MSIE, and multi-xrun/xmelab MSIE. Single-xrun (1-xrun) MSIE is the simplest; all you...

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incremental elaboration | Flows | Functional Verification | MSIE
Xcelium and Cavium: What’s the Deal?

By XTeam | 26 Feb 2018

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers now. While that’s all well and good, why is it such a big deal? Well, Cadence gathered up Ziv Binyamini, Gopal Hegde, and Ann Keffer to answer just that question in a video: https://youtu.be/QTN6goFWWBo What does it mean that Xcelium is now available on Cavium’s Thunder X2 servers? Well, the Thunder X2 brings a lot of advantages to...

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thunder x2 | video | Cavium | xcelium
Coming to DVCon? It's Not Too Late to Sign Up!

By XTeam | 20 Feb 2018

Are you coming to DVCon this year? It’s right around the corner, but it’s not too late to register! DVCon is the flagship conference for all things functional design and verification, showcasing the freshest technologies, techniques, tips, and tricks. Cadence will be in booth 702, bringing the newest tools and methodologies for working with complex silicon, SoCs, and systems. To check out the schedule, look at the...

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Functional Verification | DVcon 2018 | tutorials | event
Type MIN / MAX Values in Specman

By teamspecman | 25 Jan 2018

When defining coverage bins for coverage items, the number and size of bins depend on the item type. People seek ways to define the MIN and MAX value of the type automatically, rather than typing the numbers. For example, to ensure edge values are covered, we want to have a bin of the MIN value of the type, a bin of the MAX value of the type, and the rest of the values – to be grouped in 10 bins. If the field is of...

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Specman | Specman coverage engine | Specman e
App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)

By XTeam | 24 Jan 2018

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains to real number modeling (SVRNM), and it both enhances and simplifies the design of mixed-signal circuits. How? Well, for example, in the process of pixel design for image sensors, a designer may need to have several real nets share a value at the same time. This effectively makes those nets shorted together for the required duration...

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SystemVerilog | real number modeling | Functional Verification | App Note Spotlight
This Was 2017, Looking Forward 2018

By teamspecman | 16 Jan 2018

With 2017 just out of the door, this is a good time to stop for a few minutes, look back at 2017, and plan ahead for 2018 and the years to come. While thinking of the projects and challenges awaiting you, don’t miss this video - Specman news, Jan 2018 - an interview with Orit Kirshenberg, the manager of Specman R&D. In this interview, Kirshenberg shares her view of Specman evolution in 2017, and some of the trends...

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Specman | Functional Verification
CRAFTing Your Aero/Defense UVM Testbench the Easy Way

By XTeam | 11 Jan 2018

So you want to build an automated testbench for your aero/defense project, eh? Luckily, there’s a solution for you. A project called CRAFT (which stands for Circuit Realization At Faster Timescales) seeks to speed the development of SoCs by providing the tools necessary to make automated testbenches faster and more easily created than ever before. Funded by DARPA, CRAFT utilizes components from a number of different...

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Functional Verification | VWB | online tool | automated testbench | craft
User Extensions to DUT Error

By teamspecman | 10 Jan 2018

A question was raised to stackoverflow about how can one extend the dut _error() for printing more information. The capability to provide the test runners and debuggers more information upon an error can be a great enhancement to the quality and usability of the verification environment, so I decided to extend here a bit the answer given in the stackoverflow . The request was worded: Can we extend the dut _error()...

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Specman | e code | advanced verification | e language
App Note Spotlight - Introduction to Connect Modules

By XTeam | 10 Jan 2018

Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an app note that contains valuable information you may not be aware of. Today, we're going to look at connect modules—what they are, and why you should care about them. A Quick Run-Down on Connect Modules To understand connect modules, we'll need to step back a bit. First, understand that mixed-signal simulation has to happen in both...

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app note | Functional Verification | App Note Spotlight | Connect Module | mixed signal
Register for the UVM Register Layer Webinar on January 12!

By XTeam | 5 Jan 2018

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim of helping users model UVM in certain less-intuitive ways. This webinar will cover the usage of user-defined front and back doors to extend register-layer capabilities past simple call-and-response transactions, understanding the role the predictor plays in updating the register model, and how to use register callbacks to model strange...

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webinar | Doulos | xcelium | uvm register layer

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