Community Verification

Featured

Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

Anika Sunda
• 3 min read
featured , coverage , throughput , machine learning , Regression

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
• 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP

Moving Beyond EDA: The Intelligent System Design Strategy

The rising customer expectations, intermingling fields and high performance needs…

Vinod Khera
• 5 min read
optimality , artificial intelligence , featured , intelligent system design
Verification

Latest blogs

Verification of Integrity and Data Encryption (IDE) for CXL Devices

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

Sangeeta Soni
• 3 min read

The Crucial Need for Synchronization with Third-Party Systems

In today’s interconnected world, businesses and organizations rely heavily on various…

Anika Sunda
• 3 min read

Introducing PCIe's Integrity and Data Encryption Feature (IDE)

The Integrity and Data Encryption (IDE) was published in PCIe (Peripheral Component…

Felipe Goncalves
• 2 min read
Verification IP , encryption , PCIe , pcie gen6 , IDE

Unraveling the PCIe.6.0 Compliance Feature

In PCI Express (PCIe) devices, there is a need for testing near-worst-case inter…

sabnams
• 4 min read
Verification IP , VIP , PCIe , feature , PCIe 6.0

Power Up Your Low-Power Verification - A Quick Overview

Handheld devices have evolved immensely over the past decade. Today's smartphones…

Tyler Sherer
• 2 min read
Low Power , Verisium Debug , xcelium , verification

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

Our previous posts in this series covered measuring parameters, switches, and profiling…

Reela
• 4 min read
cadence , Xcelium Logic Simulator , xcelium simulator , verification

Best Practices to Achieve the Highest Performance Using Xcelium Logic Simulator …

Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters…

Reela
• 4 min read
Xcelium Logic Simulator , profile analysis , xcelium simulator , xcelium , best practices , verification

Understanding PCIe 6.0 Shared Flow Control

As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms…

mrana
• 3 min read
SystemVerilog , Verification IP , PCIe , pcie gen6 , PCIe 6.0 , System Design and Verification , verification

CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performanc…

Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The…

Tanushri Shah
• 1 min read
Mixed-Signal , xcelium simulator , xcelium

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

In a landscape characterized by increasingly intricate designs and rapidly diminishing…

Reela
• 5 min read
Xcelium Logic Simulator , Multi-Core , best practices , verification

Accelerate Design Debugging Using Verisium Debug

Verisium Debug is an advanced debugging tool that helps engineers explore, analyze…

ManishaP
• 1 min read
Verification IP , Verisium Debug , verification

Introduction of Precoding in PCIe 6.0

What Is Precoding in PCIe? With higher speed introduced from PCIe 5.0, high 32…

xinmu
• 4 min read
Functional Verification , VIP , pcie gen6

Training Insights: Bridging the Skill-Gap with the New Cadence Training Digital IC…

The world is reeling towards AI/ML newer planes, and our EDA world is adding these…

prabhab
• 2 min read
Functional Verification , System Design and Verification , Coverage-Driven Verification , place and route , digital flow , RTL2GDSII , Synthesis , digital_implementation

Coverage Closure – A Progression Instead of Just a Destination

The testing and verification of a complex hardware or software system, such as modern…

Anika Sunda
• 2 min read
ml , coverage , bugs , simulation

Exploring World of Flash Memory: Serial, Dual, Quad, and Octal Interface

Overview In the world of digital data storage, flash memory has become an indispensable…

Manoj Kachadiya
• 3 min read
Verification IP , DATA Storage , flash , serial flash , VIP , Memory Model Portfolio , nor flash , OSPI

Training Insights – A New Free Online Course on the Protium System for Beginner and…

The Cadence Protium System is used for prototyping. It is a hardware platform that…

SANDEEP NASA
• 2 min read
digital badge , online_training , protium x2 , Protium , blended_training , training bytes , live

Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus…

The initial focus of the Portable Test and Stimulus Standard (PSS) was pre-silicon…

Moshik Rubin
• 5 min read
Perspec , post-silicon , ATE , pss , portable stimulus , verification

Low-Power IC Design: What Is Required for Verification and Debug?

Low-Power Design Techniques Are Needed In today’s world, energy saving is a hot topic…

Rich Chang
• 6 min read
Low Power , debug , Functional Verification , UPF , VerisiumDebug

How to Maximize Productivity and Lower Cost for Enterprise Prototyping

Semiconductor chips are often produced as application-specific integrated circuits…

Reela
• 6 min read

Streamlining Your Verification Environment with Xcelium ML

When it comes to projects that involve cover groups and properties, and tests that…

Anika Sunda
• 1 min read
coverage , xcelium ml , xcelium apps

Lightelligence Accelerates DFT Simulation Using Cadence Xcelium Multi-Core

The growing design complexity of today’s system on chips can result in long hours…

Reela
• 3 min read
DFT , Lightelligence , Multi-Core , xcelium , verification

Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Python…

The Verisium Debug platform is optimized for scalability, supporting debugging of…

ManishaP
• 1 min read
Verification planning and management , training , webinar , Verisium Debug

Understanding UCIe Design Verification Topologies

UCIe or Universal Chiplet Interconnect Express is the fastest growing chiplet interconnect…

Anunay
• 3 min read
ucie , Verification IP , chiplet , VIP , die

Accelerating Your Overall HW/SW Verification and Validation Productivity Using Dynamic…

With the increasing complexity of system-on-chip (SoC), the associated software…

Reela
• 8 min read
Analog Devices. ADI , software verification , validation , protium x2 , palladium z2 , Accelerate , productivity , Hardware/software co-verification , verification

Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

Anika Sunda
• 3 min read
featured , coverage , throughput , machine learning , Regression , simulation , verification

Training Insights – Webinar –: Solve Tricky SVA Problems with Jasper Visualize and…

Are you experienced in using SVA? It’s been around for a long time, and it’s tempting…

Nizar Hanna
• 2 min read
digital badge , online , Visualize , Jasper , training , webinar , SVA , app , verification

Flex Ethernet (FlexE): Unlocking the Physical Bandwidth Constraints

Efficient and flexible use of bandwidth is the key to optimizing traffic flow…

Krunalkumar
• 3 min read
Verification IP , 5G Network , Ethernet VIP , Functional Verification , FlexE , VIP , Flex Ethernet , Ethernet , Hyperscalers , data centers , OIF , verification

What Makes a Next-Generation Debug Solution?

For the past few decades, design and verification technology have made great progress…

Rich Chang
• 5 min read
Functional Verification , debugging tips , debugging
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