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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
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UPLI Credit Flow: Why It Matters for UALink and What It Takes to Verify It Right

The Problem Nobody Talks About Picture a world where 1,024 AI accelerator chips work…

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Verification IP , VIP , UALink

UCIe 3.0: Faster Links Are Only Half the Story

The chiplet ecosystem continues to push performance boundaries, and the latest UCIe…

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ucie , Verification IP , chiplets , cadence , Cadence VIP portfolio , VIP , AIInfrastructure , UCIe 3.0 , HPC , SoCDesign , ASICDesign , SiliconEngineering

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The question posed was simple: how can we show that a virtual platform is actually…

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Automotive , Embedded Software Debugging , vlab , virtual platform , embedded software , Shift-Left

New Course Release: Python API and App Store Development with Verisium Debug

Automate debug workflows. Build reusable apps. Extend Verisium Debug with Python…

• 4 min read
Functional Verification , Verisium Debug , verification

AMBA CXS Interleaving: Shared Transport for Multi-Protocol, Multi-Node Systems

Modern SoCs bring together CPUs, GPUs, AI accelerators, coherent memory devices,…

• 9 min read
chiplet , cxs-streaming , Arm Neoverse CMN , ARM , CXS-D

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

• 7 min read
featured , chip design , AGI , LLMs

GDDR7: Highlights of Memory of Choice for Graphics and High Bandwidth Apps

Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM…

• 5 min read
Verification IP , gddr6 , VIP , JEDEC , DFI , GDDR , DRAM , Graphics memory , memory models , GDDR7

The Ethernet PHY We Knew, The UALink PHY We Needed

Same building blocks. Same lane rates. So why not just use Ethernet PHY unchanged…

• 10 min read
Verification IP , physical layer , Ethernet , UALink , protocol verification

Untangling PCIe L0p: How Four Bytes DLLP Reshape a Live Link

PCIe links in AI accelerators, storage subsystems, and data-centric platforms see…

• 5 min read
Verification IP , Low Power , Coverage-Driven Verification , PCIe

Not Every Byte in a UALink DL Flit Is a Payload

Imagine a cargo train carrying three kinds of shipments: the railway company's own…

• 8 min read
Verification IP , Flit Packing Rules , Data Link Layer , VIP , Flit Format , UALink

Secure Imaging Starts at the Sensor: Understanding SEP in MIPI CSE v2.0

Secure imaging starts at the sensor. How the SEP protocol in MIPI CSE v2.0 protects…

• 5 min read
MIPI CSE Verification , Verification IP , MIPI Alliance , MIPI CSE , VIP , Camera Security , SEP Protocol Verification , MIPI CSI-2

Verifying FSED in MIPI CSE v2.0 with Cadence VIP

Automotive camera systems face a threat model that goes beyond packet-level tampering…

• 6 min read
MIPI CSE Verification , Verification IP , FSED Protocol Verification , MIPI Alliance , Camera Security , CSE , FSED

DisplayPort Adaptive-Sync: When Fixed Refresh Rate Is Not Enough

Displays are central to nearly every modern computing experience. Whether we are…

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DisplayPort , EDP , AdaptiveSync

AMBA AXI5 MPAM: Control and Visibility for Shared Memory Resources

As modern SoCs become increasingly heterogeneous, the shared memory system has become…

• 6 min read
PMG , PARTID , AXI5 , MPAM , verification

Why Faster Isn't Always Better: UALink Transmitter Pacing Explained

Imagine two accelerators connected through a UALink link operating at full bandwidth…

• 4 min read
Transmitter Pacing , UALink , verification

Flexible UALink Verification for Any Layer, Interface, and Design Configuration

Modern AI training and inference clusters rely on hundreds or even thousands of GPUs…

• 3 min read
Verification IP , Functional Verification , VIP , UALink

Software-Defined Coffee Machine

When I go to a hotel, a key component of the experience is the morning coffee. I…

• 2 min read
Automotive , virtual platforms , vlab , System Design and Verification

When the Bug Is in the Waveform, the UALink Story Should Be There Too

Real design debug often ends in the same place: a waveform window full of DUT signals…

• 5 min read
bug , waveform , UALink , Verisium Debug , debugging , verification

AMBA AXI5 Memory Tagging Extension: Making Memory Safety Observable on the Bus

Memory safety remains one of the most persistent challenges in modern computing systems…

• 5 min read
Memory Security , MTE , Memory Tag , AXI5 , AMBA Verification IP

MIPI M‑PHY v6.0: Evolution of ADAPT for Ultra‑High‑Speed Interfaces

MIPI M-PHY has evolved to support higher data rates with the introduction of HS-G4…

• 3 min read
Verification IP , MIPI Alliance , VIP , MIPI , MPHY

PSS 3.1 Channels: The Game Changer for Target-Time Communication

Portable Stimulus models already feature powerful language constructs to describe…

• 7 min read
PSS 3.1 , Perspec , System Design and Verification , channels , perspec system verifier , target time communication

Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?

Cadence Multi-Platform Verification improves functional coverage and verification…

• 5 min read
Verification IP , Emulation , simulation

Understanding PCIe 6.0 Power States: L0p vs L0s vs L1

PCI Express has always focused on a single goal: maximizing performance while minimizing…

• 5 min read
Verification IP , PCIExpress , PCIe 6.0

From Pacemakers to ADAS: Verifying Systems Before Tapeout

Imagine discovering a critical bug in a heart pacemaker, not after deployment, not…

• 6 min read
Automotive , Protium , Palladium , medical , robotics , verification

DFI 6.0 Key Highlights of the Latest DFI Specification

The DDR PHY Interface (DFI) protocol specifies the signals, timing parameters, and…

• 4 min read
Verification IP , memory controller , PHY , VIP , hbm4 , DFI , DRAM , DFI 5.2 , DFI 6.0 , memory models , Lpddr6

UALink Under the Hood: Why Full-Stack Verification Wins

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Verification IP , UAL , verification strategy , System Design and Verification , VIP , UALink , verification

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Non-Volatile Memory Express (NVMe) has become the dominant protocol for high-performance…

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NVMe 2.0 , Verification IP , non-volatile memory , NVM Express , NVMe , Non-Volatile Memory Express , VIP , Zoned Namespaces , NVMe Verification IP , NVMe specification , ZNS

Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training

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USB4 VIP , usb4 , retimers
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