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Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus
Verification
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Inside Akeana and Cadence’s Secret Sauce for Faster RISC-V Chip Verification

The Nightmare of Chip Testing (And How to Fix It) Let's be real: designing ambitious…

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cadence , System Design and Verification , Emulation , verification

Cadence Announces PCIe 8.0 Verification IP Availability at PCI‑SIG US

At the recent  PCI ‑ SIG Developers Conference US held on May 6-7,2026 , Cadence…

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Verification IP , Functional Verification , pcie 8.0

VLAB at the MATLAB Expo Japan 2026

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Automotive , Simulink , vlab , MBSE , Testing , event , verification , Matlab

Unraveling Precision Time Measurement (PTM)

Introduction Precision Time Measurement (PTM) is an optional capability for communicating…

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Verification IP , PCIe 6.0

Unraveling Embedded Clock Mode in MIPI D-PHY: Simplifying High-Speed Serial Link

As flagship smartphones push camera sensors beyond 200 megapixels and display resolutions…

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Verification IP , Clock Data Recovery , Embedded clock mode , MIPI D-PHY , PHY Verification , verification

Struggling to Rewrite Functionality in PSS? Import Functions Streamlines

One of the most powerful features of the Portable Stimulus Standard (PSS) is the…

• 9 min read
Perspec , System Design and Verification , perspec system verifier , import function , pss

C-PHYv3.0 Verification, 35% Throughput Boost for Camera and Display Designs

With the evolution of advanced camera systems and higher-resolution displays for…

• 4 min read
Verification IP , PHY Layer , CPHYv3.0 , 18 Wire state Mode , Camera and Display Interface Design , MIPI-CPHY

EUSB2 V2 Explained: Multi Gigabit Symmetric and Asymmetric Operation

eUSB2‑V2 is stepping into the spotlight at a time when hardware designers are being…

• 4 min read
Verification IP , eUSB2v2 , eUSB , verification

Powering the Future of Memory-Centric Computing with CXL 4.0 VIP

CXL 4.0 Verification IP Now Available! Empowering Advanced AI, HPC, and Data-Centric…

• 2 min read
Verification IP , CXL3.0 , verification

Cadence VLAB at the Embedded World 2026

Just like every year, the Embedded World took place in Nürnberg in mid-March. It…

• 5 min read
Automotive , virtual platforms , vlab , Embedded World

UCIe Manageability: The Hidden Control Plane of Chiplet Systems

Chiplet-based architectures are quickly becoming the foundation of next-generation…

• 2 min read
ucie , Verification IP , multi-die , VIP

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI , verification

What Makes LPDDR6 a Key Technological Advancement for DRAM Memory Technologies

Low-power DDR SDRAM is one of the most widely used memory types in the semiconductor…

• 4 min read
Storage Technology , Verification IP , Memory , LPDDR , LOW POWER DRAM , JEDEC , DRAM , memory models , Lpddr6

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System

Modern embedded systems are becoming increasingly compact, power efficient, and feature…

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SerialWireDebug , SWD

Breaking Down UPLI: A Protocol-Level Perspective on UALink 200

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• 3 min read
UAL , protocol layer , AI Accelerator , UALink , UPLI , AI

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that…

• 5 min read
UAL , protocol layer , VIP , UALink , UPLI

Cadence VLAB at the Automotive Software Frontier

The VLAB team at Cadence is participating in the 11th Automotive Software Frontier…

• less than a min read
Automotive , vlab , virtual platform , embedded software , event

Palladium – Power Estimation Efficiency from Days to Minutes

In the competitive semiconductor industry, leading innovators consistently set the…

• 2 min read
System Design and Verification , Palladium , SVG , dpa , Power Analysis , hsv , verification

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digital badge , live training , blended training , System Design and Verification , Protium , SVG , accelerated learning , verisium , Jasper , webinar , training bytes , Stratus , ask , RAKs , verification , tcl

Virtual Platforms Keynote at RAPIDO 2026

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• less than a min read
Automotive , virtual platforms , vlab , verification

PSS Randomization Semantics and Numeric Expressions

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pss 3.0 , Perspec , perspec system verifier , pss

Don’t Let Bugs Slip Through Your RTL Design!

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FPV , Formal Analysis , formal , SoC , Jasper Apps , SVA , assertions , simulation , Formal verification

Virtualization, Collaboration, and Software at SDV Europe

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• 6 min read
Automotive , virtual platforms , software-defined vehi , software development

What's New in PSS 3.0? Key Additions to the Portable Stimulus Standard

The Portable Stimulus Standard (PSS) Language Reference Manual (LRM) has evolved…

• 6 min read
SoC verification , Perspec , SoC , pss

Smarter Chips, Faster Checks: GravityXR Leading the XR Verification Shift

As XR technology accelerates, complexity rises—but speed to market remains the ultimate…

• 2 min read
performance , AVIP , GravityXR , virtual platforms , cadence , debug , Palladium , hybrid , Emulation , XR , testbench , verification

VESA Adaptive-Sync V2 Operation in DisplayPort VIP

Need for Synchronization In a computer system, both the GPU as well as the monitor…

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Target Refresh Rate , Screen Tearing , VSync , GPU , Adaptive Sync , FAVT , Adaptive Sync SDP , display , VIP , DisplayPort , Gaming Content , GSync , Cadence VIP , FPS , Monitor , Video Content , Vertical Expansion/Reduction , VESA , AVT , Screen Stuttering , Frame Rate , VTotal , Video Frame , DisplayPort VIP , VRR , frame , Refresh Rate , FreeSync

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• 3 min read
Verification IP , non-volatile memory , flash , ONFT5.2 Vs ONFI5.1 , ONFI , VIP , memory models , ONFI5.2 , NAND , sca

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CXL , performance , Verification IP , Functional Verification , coherent , l0p
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