Cadence Community

Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress, and HyperRAM

By XTeam | 3 May 2018

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM high-speed memory. We also unveiled a new JEDEC Universal Flash Storage 3.0 (UFS) VIP. Together, these three new VIPs allow early-adopters to leap off the starting line in the race to create new, incredible SoCs and IPs incorporating...

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hyperRAM | Functional Verification | coaxpress | UFS | press release
Xcelium's New Save and Restart Saves You Time

By XTeam | 5 Apr 2018

You may have heard about the overhaul to the old save/restart mechanism that was in Incisive—but are you aware of what the new Xcelium Simulator version can do? While the old version is still supported, there’s a lot of benefits to shifting to the new one. Now called “checkpointing,” this new system uses a process-based implementation and is overviewed in the app note, Using Save/Restart Checkpointing with Xcelium...

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save and restart | xcelium | save and restore | checkpointing
List of TLM Analysis Ports: Where Is This Packet Coming From?

By teamspecman | 1 Apr 2018

Let’s say that you got an invitation from the police station nearest your home to be there the next day at 14:00. Hmm…. What could it be about? You check the letter and envelope for more information, but it does not say which department sent it. Well, it makes a big difference if the invitation was from the “lost and found” department, which means you will probably get something back, or if it came from “investigations...

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Specman | Functional Verification | e | e language | team specman | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part I

By XTeam | 19 Mar 2018

Welcome to a special multi-part edition of the App Note Spotlight, where we’ll be highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerliog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator—in fact, they...

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SystemVerilog | Object Oriented Programming | Functional Verification | Optimize
Temporals, Reset, and Test Phases

By teamspecman | 11 Mar 2018

One of the biggest challenges in dynamic functional verification is testing Reset – resetting the DUT during simulation and check DUT operation afterwards. The main challenges are propagating the reset information in the testbench, and adjusting the components behavior. For performance and accuracy, it is best to have one agent controlling and monitoring the reset, rather than each and every agent monitoring the reset...

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Specman | UVM e | Specman e | e | e language
App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For You

By XTeam | 6 Mar 2018

Welcome to another App Note Spotlight! One of the biggest issues facing verification engineers is the question of reducing elaboration time. Using incremental elaboration (MSIE) can greatly reduce that time—but that raises a new question: between the two MSIE flows, which one is right for you? Those two MSIE flows are single-xrun MSIE, and multi-xrun/xmelab MSIE. Single-xrun (1-xrun) MSIE is the simplest; all you...

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incremental elaboration | Flows | Functional Verification | MSIE
Xcelium and Cavium: What’s the Deal?

By XTeam | 26 Feb 2018

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers now. While that’s all well and good, why is it such a big deal? Well, Cadence gathered up Ziv Binyamini, Gopal Hegde, and Ann Keffer to answer just that question in a video: https://youtu.be/QTN6goFWWBo What does it mean that Xcelium is now available on Cavium’s Thunder X2 servers? Well, the Thunder X2 brings a lot of advantages to...

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thunder x2 | video | Cavium | xcelium
Coming to DVCon? It's Not Too Late to Sign Up!

By XTeam | 20 Feb 2018

Are you coming to DVCon this year? It’s right around the corner, but it’s not too late to register! DVCon is the flagship conference for all things functional design and verification, showcasing the freshest technologies, techniques, tips, and tricks. Cadence will be in booth 702, bringing the newest tools and methodologies for working with complex silicon, SoCs, and systems. To check out the schedule, look at the...

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Functional Verification | DVcon 2018 | tutorials | event
Type MIN / MAX Values in Specman

By teamspecman | 25 Jan 2018

When defining coverage bins for coverage items, the number and size of bins depend on the item type. People seek ways to define the MIN and MAX value of the type automatically, rather than typing the numbers. For example, to ensure edge values are covered, we want to have a bin of the MIN value of the type, a bin of the MAX value of the type, and the rest of the values – to be grouped in 10 bins. If the field is of...

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Specman | Specman coverage engine | Specman e
App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)

By XTeam | 24 Jan 2018

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains to real number modeling (SVRNM), and it both enhances and simplifies the design of mixed-signal circuits. How? Well, for example, in the process of pixel design for image sensors, a designer may need to have several real nets share a value at the same time. This effectively makes those nets shorted together for the required duration...

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SystemVerilog | real number modeling | Functional Verification | App Note Spotlight
This Was 2017, Looking Forward 2018

By teamspecman | 16 Jan 2018

With 2017 just out of the door, this is a good time to stop for a few minutes, look back at 2017, and plan ahead for 2018 and the years to come. While thinking of the projects and challenges awaiting you, don’t miss this video - Specman news, Jan 2018 - an interview with Orit Kirshenberg, the manager of Specman R&D. In this interview, Kirshenberg shares her view of Specman evolution in 2017, and some of the trends...

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Specman | Functional Verification
CRAFTing Your Aero/Defense UVM Testbench the Easy Way

By XTeam | 11 Jan 2018

So you want to build an automated testbench for your aero/defense project, eh? Luckily, there’s a solution for you. A project called CRAFT (which stands for Circuit Realization At Faster Timescales) seeks to speed the development of SoCs by providing the tools necessary to make automated testbenches faster and more easily created than ever before. Funded by DARPA, CRAFT utilizes components from a number of different...

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Functional Verification | VWB | online tool | automated testbench | craft
User Extensions to DUT Error

By teamspecman | 10 Jan 2018

A question was raised to stackoverflow about how can one extend the dut _error() for printing more information. The capability to provide the test runners and debuggers more information upon an error can be a great enhancement to the quality and usability of the verification environment, so I decided to extend here a bit the answer given in the stackoverflow . The request was worded: Can we extend the dut _error()...

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Specman | e code | advanced verification | e language
App Note Spotlight - Introduction to Connect Modules

By XTeam | 10 Jan 2018

Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an app note that contains valuable information you may not be aware of. Today, we're going to look at connect modules—what they are, and why you should care about them. A Quick Run-Down on Connect Modules To understand connect modules, we'll need to step back a bit. First, understand that mixed-signal simulation has to happen in both...

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app note | Functional Verification | App Note Spotlight | Connect Module | mixed signal
Register for the UVM Register Layer Webinar on January 12!

By XTeam | 5 Jan 2018

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim of helping users model UVM in certain less-intuitive ways. This webinar will cover the usage of user-defined front and back doors to extend register-layer capabilities past simple call-and-response transactions, understanding the role the predictor plays in updating the register model, and how to use register callbacks to model strange...

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webinar | Doulos | xcelium | uvm register layer
Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck!

By XTeam | 29 Nov 2017

On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional verification...

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Functional Verification | PCI-e | announcement | TripleCheck
26262 4U: Infineon and the Incisive Functional Safety Simulator

By XTeam | 22 Nov 2017

Infineon and Cadence have a bit of a history: they’ve been working together on functional safety mechanisms for around two and a half years now, and Infineon has been using the entire Cadence verification suite since the nineties. Functional safety is a serious hurdle for the automotive industry, and with the rise of ADAS systems, the issues that face Cadence and Infineon are about to get a lot more complicated. Right...

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Infineon | Functional Verification | fault | ifss
Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!

By XTeam | 15 Nov 2017

Even today, gate-level simulation is still a major signoff step for most semiconductor projects. However, those simulations can take days or weeks to run. A bug that causes a rerun of a gate regression can push a tapeout for weeks—but help is on the way! The app note for gate-level simulation (GLS) methodology was released on November 11, 2017. It aims to showcase new methods and simulator-use models that make GLS...

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app note | Functional Verification | GLS
Adding Annotations in Your e Code

By teamspecman | 8 Nov 2017

If you have had a chance to work with languages like Java or C#, you might have come across Annotations . Since the Specman 17.10 version, annotations have become part of the e language! (See Java annotation and Basic Introduction to Data Annotation in .Net Framework . ) What are annotations? Annotations are a form of metadata that provides information about an entity in your code. However, they have no direct effect...

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Specman | e | e language | specman elite | annotations
Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on Arm-Based Servers

By XTeam | 30 Oct 2017

On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic Simulation on Arm-based servers. It was demonstrated running on Cavium ThunderX2 and Qualcomm Centriq servers at the Arm Techcon event on October 25 and 26. This represents a new development in low power, yet high performance simulation solutions for the EDA industry. Ensuring that designs function correctly is a huge challenge for...

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Multi-Core | xcelium | ARM | simulation | announcement
Munich October 18—Come See SystemC Evolution Day!

By XTeam | 17 Oct 2017

Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to Munich in October for SystemC Evolution Day—a workshop on the evolution of SystemC standards held in Munich, Germany on October 18th. It’s a full day workshop, and the second iteration of a successful first run in May 2016. SystemC Evolution Day will feature several in-depth sessions about current and future standardization topics involving...

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Munich | Functional Verification | Accellera | SystemC | event
Teradyne Standardizes on Xcelium Simulator

By XTeam | 13 Oct 2017

Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator for use in ASIC development. They’ve reached a 2x speedup with Xcelium when compared to their old simulation solution. Xcelium has quickly become a key part of Teradyne’s verification environment, providing an easy-to-use, yet very powerful, tool that runs fast and ensures high-quality designs. Beyond Xcelium, Teradyne is also using...

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Teradyne | ASIC | press release | xcelium | JasperGold | vManager
Teradyne "Formally" Adopts JasperGold FPV

By XTeam | 13 Oct 2017

CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation, Success using Formal Verification --and now they join the ever-growing fold of JasperGold FPV (Formal Property Verifier) App users. Teradyne had used some of JasperGold's functionality before with the JasperGold Connectivity App, but this marked a noted change in their usage of it by embracing more of the features the JasperGold...

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Teradyne | FPV | CDNLive | customer success | JasperGold | Formal verification
Single Core vs. Multi Core: Simulation in Stereo

By XTeam | 26 Sep 2017

Latency simulations are the sworn enemy of the verification schedule. A handful of tests add days to weeks for each regression cycle; and when you add in the fact that they can’t be parallelized like the shorter bandwidth simulations, it gets hard to manage an engineer’s time efficiently. But… What if there was a better way? Since the olden days of simulation, all of that was true. Bandwidth sims were—and still...

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Single-Core | Functional Verification | Multi-Core | xcelium | simulation
Put On Your Perspectacles: How Perspec Can Speed Up Your Testbench

By XTeam | 23 Aug 2017

It’s no secret that the bulk of time running simulations is spent on the testbench side. You can throw as many cores as you want at the DUT when you’re running RTL tests, but let's face it, it’s the testbench itself that’s bottlenecking you. Let’s say it takes thirty minutes to run the testbench side, and thirty minutes to run the tests themselves. You can use multi-core parallelism to massively shrink the DUT time,...

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Functional Verification | Perspec | xcelium | testbench

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