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Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 2 of 2)

By XTeam | 25 Jun 2019

Welcome back to this account of the IP Security Panel at the Accellera Luncheon at DAC 2019. We’ve covered who’s seated on the panel and the moderator’s questions in the last installment (link to first blog)—now it’s time to talk about what the audience had to ask. The first question asked was related to that morning’s keynote speaker, and that speaker’s one criteria for IP developers with regards to security: do they...

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security | luncheon | DAC 2019 | Panel | Accellera
Tales from DAC: A Meeting of Security's Heroes at the Accellera Luncheon (Part 1 of 2)

By XTeam | 24 Jun 2019

Figure 1: The panel and crowd Citizens—the tech world is in trouble. With the ever-expanding size and complexity of chip designs, security hasn’t kept up. Old techniques for securing a design are no longer sufficient—and with IoT devices expanding into every facet of a person’s life, security is more important than ever. The often-joked-about case of someone hacking your refrigerator isn’t strictly a joke—without...

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security | luncheon | DAC 2019 | Panel | Accellera
Master of ‘e’? Now You Can Prove It!

By teamspecman | 19 Jun 2019

The knowledge and experience of using Specman/ e tells everyone that you have acquired profound verification methodology. But how do you showcase this knowledge to your company, colleagues, and perspective employers? To help you showcase your expertise, Cadence Training Services now offers Cadence Digital Badging . A certification test was created for some technologies (including Specman). When you pass the certification...

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Specman | Specman/e | Specman e | badge | e | e language | specman elite
Specman: Python Is here!

By teamspecman | 12 Jun 2019

Do you know from where Python technology gets its name? It is not from the snake, it is named after the Monty Python comedy group. And indeed, one of the main guidelines behind it is to be fun to use (check out the Zen of Python ). Therefore, Python is intuitive, readable, and easy to learn - all of these make it not only fun to use but also highly productive. Does this sound familiar? If you are an e user, it should...

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Specman/e | Python | Specman e | machine learning | specman elite
Got IP Security Questions? This Luncheon at DAC Has Answers

By XTeam | 30 May 2019

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you’re planning to attend DAC, be sure to stop by the Accellera-sponsored Luncheon Focusing on IP Security Assurance Issues Led by Panel of Industry Experts. There, you’ll hear a short update on what Accellera’s been up to by Accellera Chair Lu Dai, and then the experts will jump right into a panel discussion covering all sorts of IP security...

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security | DAC | luncheon | DAC 2019 | Accellera
Thinci Finds Success with the Cadence Verification Suite

By XTeam | 28 May 2019

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete Cadence Verification Suite to speed up the verification of their machine-learning and AI designs. Now, Thinci can access the new technologies available through the Cadence Verification Suite to shorten their product development time by months while improving verification coverage. “We selected the Cadence Verification Suite because it...

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ThinCi | Functional Verification | cadence verification suite | success story | verification
Concurrent Actions in Specman: Part 2

By teamspecman | 8 May 2019

In the previous blog: Concurrent Actions in Specman , we discussed the existing options: all of ( which awaits completion of all branches) and first of (which terminates at the first completion of any branch). In 19.03 we added enhancement on top of these existing options, we made them more dynamic. In all the examples in the previous blog, the number of branches was constant (all the examples used 2 branches). What...

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Specman | Specman/e | Specman e | concurrency | specman elite
Cadence at the Red Hat Summit--Come See Xcelium in Action!

By XTeam | 1 May 2019

The Red Hat Summit is coming around to Boston this year, and it’s only a few short days away. Cadence has a demo at the Marvell booth (that’s #418-1), and we’ll be there from 3-7 PM on Wednesday, May 8 th . There, we’ll be showing off our Arm-server technology by demoing Xcelium. Be sure to stop by! Cadence and Arm have worked together to create solutions that optimize power, performance, and area while speeding up...

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Functional Verification | red hat summit | xcelium | event
Cadence at the HOST Symposium: Come See What We're Doing!

By XTeam | 1 May 2019

The HOST Symposium is returning for its 12 th year, and general registration is open now. The IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) aims to accelerate and assist the development of hardware-based security technologies. With the advent of Internet-of-Things (IoT) devices, new avenues of attack have opened up for nefarious hackers—what was previously focused on computers, defense...

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host | Functional Verification | symposium | event
Specman Linting and the all_unique Method

By teamspecman | 29 Apr 2019

Sorting according to pointers- why? One of the best practices that you need to follow when using Specman or any other tool is to use a linting tool on a regular basis to catch bugs early. In Specman, we frequently add additional e checks to HAL (Cadence linting tool) based on the customer issues that can be avoided or caught during linting. For instance, in 19.03, among few other linting checks, we planned to add...

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Cadence Announces Continued Partnership With Northrop Grumman

By XTeam | 1 Apr 2019

On March 28th, 2019, Cadence Design Systems announced an expanded collaboration with Northrop Grumman centering on advanced-node SoC projects. Cadence’s cutting-edge verification tools are combining with Northrup Grumman’s expertise to deliver high performance ASICs more efficiently. Northrop Grumman will be using the full flow of Cadence ASIC development tools including verification, digital synthesis and implementation...

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chip design | Functional Verification | press release | Northrop Grumman
Cadence Leads the Pack: The First VIP for USB4 is Here!

By XTeam | 1 Apr 2019

On March 14th, Cadence announced the release of the industry’s first USB4-supporting Verification IP! The Cadence VIP for USB4 allows engineers to design and create cutting-edge SoC designs compliant with the current standards that are completely functionally verified and require less time. “Support from [USB Implementers Forum] members like Cadence helps reduce the barriers to adoption of new USB protocols and enables...

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Functional Verification | VIP | usb4 | press release
Concurrent Actions in Specman

By teamspecman | 25 Mar 2019

Lately we have been asked by several customers about the concurrency options in Specman (some refer to it as “What are the Specman options similar to fork…join?”). Apparently, things that are in Specman for ages are likely to be missed. Therefore, this blog describes Specman concurrent actions (existing for years). Specman has two actions controlling concurrent execution: all of and first of. Both actions create parallel...

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first of | Specman | Specman/e | Specman e | e | specman elite
And the Winner of the 2019 DVCon U.S. Best Paper Award Is...

By XTeam | 11 Mar 2019

Another successful DVCon U.S. 2019 has come and gone, but this year had a particularly interesting highlight. With nearly 900 attendees, a bigger program of tutorials, panels, papers, and posters, and a sold-out expo, the Best Paper award was even more prestigious than ever before. This year, the award was renamed to the Stuart Sutherland Best Paper Presentation. Stu was a leading Verliog and SystemVerilog expert, and...

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DVCon 2019 | paper | Functional Verification | award
Specman is Sweet – Bosch Sensortec's Story

By XTeam | 29 Jan 2019

Recently, Bosch Sensortec has been using Specman for their functional verification needs in their Inertial Measurement Unit, and they’re loving it. Why is Specman so cool? Well, it’s implementing the familiar UVM in e, which provides the tools and infrastructure to easily build extendable, maintainable, and reusable verification components. If you use Specman, you’ll see big productivity increases. For a lot of common...

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Specman | Bosch | e | success
New Training Bytes Available Now: All About SystemVerilog Classes

By XTeam | 28 Jan 2019

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking, don’t worry—there’s a new series of Cadence Training Bytes to help you hit the ground running in 2019. Here you’ll find eight new YouTube videos all about SystemVerilog classes. You can find the first video here . Here’s a quick table of contents: SystemVerilog Classes 1: Basics This video goes over the basics of what a SystemVerilog...

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SystemVerilog | Functional Verification | classes | training | training bytes
Verification of ML IP and Specman—Our Hackathon Project

By teamspecman | 15 Jan 2019

If you are lucky enough and your company spends a few working days each year on a Hackathon, you must know that it is usually a lot of fun. The latest 2018 Hackathon in Cadence was all about Machine Learning. We, in Specman R&D, debated a bit around how to approach the topic since Machine Learning means a lot of different things in our industry. Take a look at the following interesting article: Where ML works best in...

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ml | Specman | Specman/e | Specman e | machine learning | specman elite | verification coverage | verification
Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification Suite

By XTeam | 24 Dec 2018

Recently, Renesas Electronics Corporation faced a challenge. They were developing a new data conversion block, one that included an AHB bus bridge, which would be attached to a pre-existing DMA IP core. There was also a complicated finite state machine involved in this new block. Renesas didn’t have a whole lot of time on their hands—they needed a quick turnaround time, but only had a limited amount of engineers to accomplish...

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Specman | Functional Verification | Renesas | e | success
Veriest to Host Verification Meetup in Serbia Featuring Specman Macros

By Steve Brown | 30 Nov 2018

Veriest , a member of the Cadence Verification Alliance , is holding a series of Meetups in Serbia to serve the growing technology community. The December 12th event will feature a session on Specman Elite macros and how they help with reusability and maintainability. Veriest is a long time Verification Alliance member, and recently co-authored a paper with Valens on DVCon on the same topic: " Learn How Valens uses...

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Specman | veriest | specman elite | verification
Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High Performance Computing Servers

By XTeam | 25 Oct 2018

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching system design enablement collaboration, the Cadence Verification Suite is ready for use on Arm®-based high-performance computing (HPC) server environments. Now, all of the Cadence verification software tools you know and love—including Xcelium Simulator—can be run on the Hewlett Packard Enterprise (HPE) Apollo 70 system, which uses...

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press release | HPC | ARM | announcement
Learn How Valens uses Specman Macros Automate Configuration of Verification Environments at DVCon EMEA Next Week

By Steve Brown | 16 Oct 2018

Valens has achieved success through applying Specman to their verification projects. At DVCon EMEA (Oct 24-25) you can learn how their use of Specman Macros to automate configuration of the verification environment to their design. This saves them effort and lowers the learning curve for engineers who jump from project to project. In collaboration with Veriest Verification Ltd , a Cadence Connections Verification partner...

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verification
Improving Your Testbench Flexibility with Enhanced Specman Templates

By Steve Brown | 8 Oct 2018

Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible with the Open Verification Methodology (OVM), the Universal Verification Methodology (UVM), and the eReuse Methodology (eRM), so you can quickly and easily integrate it with established verification flows. Attend our...

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Specman 18.09: Avoiding the Small Annoying Mistakes

By teamspecman | 8 Oct 2018

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article takes the small mistakes to the extreme and mentions a few cases of small mistakes that had a huge effect: Messing up big time: 10 tiny mistakes that have caused HUGE problems . How is it relevant to Specman? As a verification...

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enumerator | Specman | Functional Verification | e | e language | specman elite | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Objects

By XTeam | 8 Oct 2018

Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the...

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performance | SystemVerilog | Functional Verification | xcelium simulator
Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

By XTeam | 12 Sep 2018

Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling in ways you may not be aware of. We’ll be covering the following topics: How to use user-defined front doors and back doors to expand what the register layer can do Understanding the role played by the predictor...

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uvm | Functional Verification | webinar | Duolos | uvm register layer

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