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Single Core vs. Multi Core: Simulation in Stereo

By XTeam | 27 Jun 2017

Latency simulations are the sworn enemy of the verification schedule. A handful of tests add days to weeks for each regression cycle; and when you add in the fact that they can’t be parallelized like the shorter bandwidth simulations, it gets hard to manage an engineer’s time efficiently. But… What if there was a better way? Since the olden days of simulation, all of that was true. Bandwidth sims...

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Single-Core | Functional Verification | Multi-Core | xcelium | simulation
Cadence @ DAC: What to Expect and What to See

By XTeam | 19 Jun 2017

Cadence returns to DAC 2017 this year, showcasing our full verification suite. Here are some of the things you can look forward to from us in the upcoming week. Once again, Cadence has the Expert Bar on Monday, Tuesday, and Wednesday. The Expert Bar is where engineers can visit our booth and have conversations with our technical experts. Cadence will be running many sessions, and those topics are listed below. ...

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TAGS:

DAC | methodology | EDA | Formal verification | verification
X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset

By XTeam | 13 Jun 2017

All chips need to cold reset on every power-up. Warm resets, however, are a bit more complicated. Take a smartphone screen, for example. The screen may power down while the phone is idle. However, the user will want it to return to their pre-set brightness level on power-up. Chips have to be tested for multiple warm-reset scenarios, and each of these tests take a very long time. Enter Xcelium Simulator, and X-propagation...

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SystemVerilog | Functional Verification | xcelium | Reset | simulation
A Brief Introduction to Xcelium

By XTeam | 9 Jun 2017

Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the newest in parallel simulation technology with the Xcelium Parallel Simulator. In this blog, we will bring you informational and technical articles regarding Xcelium’s features, such as X-propagation technology, save and restore, and incremental elaboration, in addition to information about innovations and general improvements over existing...

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Low Power | digital mixed signal | Functional Verification | Multi-Core | xcelium | parallel simulation
Static Members in e

By teamspecman | 12 Mar 2017

How do you define elegant or clean code? Usually, you know it when you see it; defining it is harder. It is usually a simple, clear and well-structured code. OO programming languages (like Java, C++, System Verilog, and also e ) provide you with aids to write elegant code. This blog is about static members in e . Can you live without them? Usually, you can. What can they do for you? Help you write elegant and clean code...

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Specman | Incisive | e language | static | xcelium | verification
Specman in Xcelium

By teamspecman | 6 Mar 2017

Just recently Cadence announced the new superb simulator, Xcelium . Just as Specman was part of the previous simulator, IES, it is now part of Xcelium. As always, we keep enhancing and developing Specman, and the new Specman release, now part of Xcelium, contains great new capabilities. The focus in the last year was on tools that will enable you, the verification experts, to create easy to use powerful verification...

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TAGS:

IEEE 1647 | funtional verification | Specman | Functional Verification | e | e language | Funcional Verification | specman elite | Incisive Enterprise Simulator (IES) | IES | verification | IES-XL
IEEE Std 1647™ 2016 - e Language - New Standard Publication

By teamspecman | 2 Feb 2017

Congratulations to the IEEE-1647 e Functional Verification Language Working Group ( e WG) In the beginning of 2017, the IEEE-1647 e WG issued for publication IEEE Std 1647™ 2016, IEEE Standard for the Functional Verification Language e . This version of the standard, issued under the chairmanship of Darren Galpin from Infineon, with input from other members from the EDA industry, contains enhancements of the...

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IEEE 1647 | Specman | e | e language | specman elite
Creating Code from Tables

By teamspecman | 30 Nov 2016

Some things are best described with tables—each column shows the values for one category, and each row encapsulates one given set of values for all categories. e verification language code is a perfect fit. This blog describes how to use tables in your verification environment code to make the code more readable and more easily maintained. The tables can be written in the code or they can be pulled in from an...

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TAGS:

Specman | Tables | e | verification
What is ISO 26262 and Why Should I Care?

By Randal Childers | 29 Sep 2016

ISO 26262 is a functional safety standard applied to the development of electrical and/or electronic (E/E) systems in automobiles . It is aimed at reducing risks of physical injury or of damage to the health of people in the event of an unplanned or unexpected hazard. The standard requires that every tool used within the design and verification flow, that can either insert errors into the final product or prevent errors...

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automotive | functional safety | cadence | ISO 26262
Coverage Maximization

By teamspecman | 24 Aug 2016

Searching for “automatic coverage maximization” results with ~16 million hits. Alas, this does not reflect 16 million solutions, rather it is an indication of the big interest in this topic, and the many attempts to automate the process of “getting full coverage, faster”. There are several tools available, performing smart coverage analysis and directing the tests to the less covered areas. ...

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Specman | coverage | Functional Verification | Testbench simulation | Coverage-Driven Verification | CDV | e | e language | Funcional Verification | team specman | specman elite | verification
Fine Tuning of Coverage Model Definition

By teamspecman | 14 Jul 2016

Functional Coverage is one of the main means to measure the quality and progress of the verification project. We define coverage models, run semi-random tests, and every once in a while analyze the coverage report to decide “are we there yet?”. When talking about “coverage closure”, people tend to talk about generation, how we create the data that will fill the coverage. In this blog, we discuss...

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funtional verification | Specman | coverage | Functional Verification | Coverage-Driven Verification | CDV | e | e language | Funcional Verification | team specman | Verification IP modeling | metric-driven verification | MDV
Why Do We Need a Verification Language?

By teamspecman | 21 Jun 2016

This month, we celebrate the 20 th anniversary of Specman’s introduction to the public—at DAC 1996 in Las Vegas. This introduction was not simply of a new tool—it was the introduction of a new concept. Specman included e , and thus, with that introduction, the first Hardware Verification Language was born. Many of you, I suspect, were still in high school in the 1990s. You would be amazed if you saw...

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TAGS:

Specman | e | Aspect Oriented Programming | yoav hollander | verification
How to Find Where Declared e Entities Are Used

By teamspecman | 5 Jun 2016

The e Reflection API allows you to perform various queries on entities in your own code, and to figure out which types, fields, methods, and so on have been declared in the code, the relations between them, and their source information. However, what the Reflection API does not provide is an ability to figure out if those entities are actually used, and if so, where they are used. For example, you have declared a method...

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TAGS:

IEEE 1647 | funtional verification | Specman | Functional Verification | e | e language | Funcional Verification | specman elite | IES
Simulation Acceleration—Maximizing Simulator Performance

By teamspecman | 25 May 2016

"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to describe a verification environment in which the Device Under Test is synthesized and runs on the emulator, while the testbench runs on the simulator. This blog describes a technique for maximizing the performance of the simulator and thus increasing the overall performance of the Simulation Acceleration. In Simulation...

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TAGS:

Specman | Functional Verification | e | specman elite | verification
Building Efficient Scoreboards

By teamspecman | 18 Apr 2016

A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple: Items sent to the DUT are added to the scoreboard and stored in its data base. Items returned from the DUT (and collected by the monitors) are added to the scoreboard to be matched against the items sent. Basically, the matching...

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RTL Signoff vs. Functional Signoff

By John Brennan | 14 Apr 2016

The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification, like how much functional coverage you should use on a particular design. I promised to next talk about signoff, so here it is. There are two fundamental steps most users apply to sign-off a new design, a functional milestone...

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TAGS:

funtional verification | IMC | metric driven verification (MDV) | functional coverage | MDV | vManager
Modelling a Value Holder Template with the Value “new-ed” by Default

By teamspecman | 11 Apr 2016

In many companies, there is a well-defined flow for handling monitored data items: match the input data to output data (or, match a response to a request), update data, for example latency or the time from request to response, print formatted messages, and so on. One of the tools used by verification leaders to implement such company methodology and, at the same time, “pave the way” for variations in the...

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IEEE 1647 | Specman | tech tips | e | e language | specman elite | Aspect Oriented Programming | AOP | verification
How to Handle a Binding Catastrophe

By teamspecman | 28 Mar 2016

Are you busy debugging your environment topology and coming up against components getting unexpected data? Have you found yourself asking “who is passing data to this monitor, and why?”? Components in the environment interact using ports (TLM ports, method ports, simple ports, and so on). This blog tackles the challenge of debugging a “bad connection”—an in port bound to the wrong out...

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Specman | TLM | binding
e Templates – Cool Tool, Now Even Cooler

By teamspecman | 23 Mar 2016

One of the reasons why verification engineers love e is the power it gives them as no other language can. The combination of macros, reflection and extension allows you to create high quality utilities that can be shared by verification teams all over your company. Such utilities are an effective way to enhance the quality of the verification environment; the base type or template are created once by experts, and used...

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UVM-ML OA: Now Within Incisive Platform As Well!

By teamspecman | 22 Feb 2016

Open-source software has many advantages. In short: you can see it (the code), you can inspect it ( check out what Coverity revealed in the Android kernel ), and you can change it. But the fact that open-source software is not commercial also raises concerns: Is it “polished” enough? Is it thoroughly tested? How hard should I work to make it part of my product? What is the level of support? Etc. Yes, life...

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TAGS:

Specman | UVM-ML OA | Incisive | multi-language
Functional Verification Closure—Are We Done Yet?

By John Brennan | 12 Feb 2016

In my job as product marketing director for vManager and MDV, I get to hear this discussed all the time— when will verification be done? If not asked overtly, at a minimum it’s that rattling and clanging that you just know is going on in people’s heads as they try to formulate the questions and the concerns. So I thought I would write about it, if nothing else to stir the conversation about what is known...

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methodology | verification strategy | Functional Verification | Metric Driven Verification | vPlan | Incisive | Plan and metrics management | vManager
Using Tables to Handle Configurability in Incisive Enterprise Specman

By teamspecman | 20 Jan 2016

Most, if not all, designs which are being verified today are configurable. This is just a fact of life, with companies trying to reuse as much IP as possible in multiple different projects, or iterations of the same project. The requirements change as well (sometimes too often) and the interface protocols are getting more elaborate and layered. Just have a look at the table below: (Ref: http://www.3gpp.org The Mobile...

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TAGS:

IntelliGen | configurable designs | Specman | tech tips | Funcional Verification | Incisive Enterprise Specman
A Coverage Time-Saving Tip

By John Brennan | 20 Nov 2015

How often has this happened to you? You are re-using a part of a previous design in your new design, you are in the depths of coverage closure, both functional and design code coverage. You discover that many parts of the re-used design are actually not applicable in the new design, and you manually exclude those RTL lines of code. But wait – there is another design change, and your RTL now has been shifted around...

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TAGS:

IMC | coverage | Incisive Enterprise Simulator | Incisive | metric-driven verification | MDV | Incisive Enterprise Simulator (IES)
Incisive vManager Free Video Training

By John Brennan | 15 Sep 2015

The Incisive vManager tool for professional verification planning and management has now been officially released for almost two years. As demand for the Incisive vManager solution increases, so does our broad-scale support. Many of our users, however, are unaware of how much free training is actually available through Cadence as video content, available directly via Cadence Online Support (COS). This video content is...

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TAGS:

Functional Verification | Cadence Online Support | Incisive | training | vManager
Make Your Debugging Faster by Recording Your Simulator

By teamspecman | 21 Jul 2015

One of the famous quotes of Brian Kernighan is: "Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it". Well, I am not really sure he meant that no one is smart enough to debug one’s own code; however, he did mean that debugging is hard, if not even harder than coding. Hence, you...

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TAGS:

Specman | debug | e | specman elite | simulation | verification

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