Functional Verification Blogs

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you might have heard Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Of course, CXL buzz is for real and is well resonating with big industry players in processing and storage landscape. We are already seeing pre-production CXL design...

We covered CHI specification revisions A to D in my previous article , what about Issue E? Issue E was by far the biggest update yet with a slew of new transactions, optimization features to interface behavior and architecture, and spec clarifications and corrections. It spanned two years and two sub releases (E.a and E.b). 2020 (CHI-E.a) Issue E.a – update Issue E.a added new transaction types such as Write...

As discussed in the last installment of the blog, a robust system level scoreboard is essential for functional verification and performance validation of modern SoCs. A properly architected system scoreboard should work in conjunction with interface Verification IPs (VIPs) and share verification responsibilities. It should monitor all ports on an SoC’s interconnect, deploying clever algorithms to track transactions...

In ARM MMU-based systems, DTI protocol defines a standard way to communicate with Translation Control Unit (TCU). DTI protocol is a point-to-point protocol with each channel defining a link. The communication with TCU will be from two different components, and DTI protocol defines both. Communication between Translation Buffer Unit (TBU) and TCU (DTI-TBU Protocol) Communication between PCIe Root Complex and TCU...

As the device frequencies and the data rates go up with every new generation of Interface and memory devices, sampling of the signals and the transferring of the data b/w Initiator and target is being increasingly difficult with ever shrinking data eyes.   To assist with handshaking for the high speed I/O, most of the newer generation of the interfaces and memories support an ever-increasing number of Training Modes...

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system’s performance. These performance expectations make the whole system verification extremely challenging and become more complex as the project evolves from IP Level verification to Memory sub-system and System-level as you start integrating the memory pieces in the whole SoC. In this blog, I will be discussing how Cadence helps to overcome...

DDR Memory is an important part of a wide array of electronic system designs in various verticals like Data centers, Cloud computing, Aero-Defense, Mobile, or any other consumer devices. These industries continue to demand higher throughput, energy e...

Cloud computing, IoT (Internet of Things), machine learning, big data, and data centers are a few of those buzzwords levitating around digital transformation in recent years and we are quite familiar with these terms. These technologies have much of a demand for things like excessive speed, higher bandwidth, scalability, and accelerated processing power. Hyperscale computing provides an intelligible method of processing...

Current verification techniques cannot keep pace with the growing arithmetic nature of today´s designs. With the advent of AI, cryptography, and other emerging domains, the amount of datapath in designs today is growing exponentially. These datapath designs typically involve arithmetic units doing integer, fixed-point, and floating-point operations for matrix multiplications, polynomial computations, FFTs, and many...

MIPI specifications are widely used across the Mobile and IoT industries, mainly for applications like cameras, sensors, modems, storage, audio, displays and other peripherals. In the last few years, the Automotive industry has also started to adopt ...

Presenting Specman syntax error messages enhancement - provide suggestions to fix typos. Starting Specman 21.09, the next time you get a compilation error of the kind “no such variable xxx”, or “yyy does not have such a field”, Specman will try to include a suggestion to an existing name.

Knowingly or unknowingly, we are consuming huge volumes of data from getting up early with Google/Siri, doing day-to-day work, using maps while driving till the time we call it a day and retiring in bed while watching Netflix. We expect all these to...

The objective of USB4 protocol to achieve high speed signal transmission and thereby providing high data bandwidths for protocol tunneling would not have been possible without USB4 re-timer. Like several other serial protocols where the generation-by-generation higher link speeds are being targeted, USB4 system too needs re-timers, whether On-board or in Active cables, to support 40Gbps link speed. Re-timers are protocol...

In my previous article ( From AMBA ACE to CHI, Why Move for Coherency? ) I talked about how coherency needs have evolved from AMBA ACE to the highly successful and widely adopted CHI architecture. Since the introduction of CHI, Arm has continually refined the specifications with clarifications, improvements, and new features. Let’s take a quick look at each update and understand why they are important. 2017 (CHI...

The emerging 5G network is the 5th generation of the cellular network. A 5G network allows handling a thousand times more traffic than today's networks. Not only is it faster than the 4G network , but it also has lower latency, faster connectivity, and greater bandwidth. 5G network revolutionizes autonomous driving, the internet of things (IoT), virtual reality (VR), and user experience in the entertainment industry...

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from existing AXI protocol, to satisfy the cache coherency maintenance demands of SOCs with multi core processors and shared caches in smart phones, mobile computers, and servers. It added new channels for cache communication, extra signals to allow new transaction for coherency support, and five state model for caches. AXI + ACE Signals : ACE was designed...

At a particular point in time, the automotive industry continued to add more and more sensors and electronic control units to vehicles. All these sensors and actuators used to connect through CAN and LIN buses. However, since the introduction of IVN (In-Vehicle Network), the industry has started replacing these buses with automotive ethernet. According to NXP , “Ethernet enables broadband connectivity with the necessary...

Even with the DRAM capacity going up with each generation of DRAM, the demand for memory densities by variety of applications, is growing at even faster rate. To support these high memory densities and bus width requirements (that are typically more than what a single DRAM can support) almost all the new generation of memory sub systems and SOCs have multiple DRAM Dies combined to effectively create higher density...

The concept of Trusted Execution Environments (TEE) was developed in the early 2000s to standardize key encryptions, end-to-end security and authenticity, and confidentiality of devices in a system. With the increase in computing and connected devices due to IoT, there are large number of applications which are installed or accessed by users in a server or mobile resulting in an increased probability of data being compromised...

As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality . Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose secure information like decryption keys were found only in post silicon after tape out. This shows that conventional simulation-based verification is insufficient to address...

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnects are enabling new generations of data servers and high-performance mobile devices. Being at the heart of SoCs, they introduce significant challenges to verification engineers both from functional verification and...

The new cloud, AI, Analytics, and Edge usage models with exponential data growth and connection drive the evolution of high-bandwidth PCIe (Peripheral Component Interconnect Express) version 5.0 and 6.0, CXL (Computer Express Link) version 2.0 and 3.0. Every component can be envisioned as an attack vector in modern computational systems, especially PCIe and CXL components, which are part of the system HW root-of-trust...

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification has been ubiquitous PHY interface for accelerating the design and verification of higher layer protocol stacks for more than 15 years. Since then, there have ...

I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during the previous CDC webinar "Still Relying on Static-Only CDC Signoff? Introducing the JasperGold CDC App". If you didn't have the chance to attend it, we are recommending you to visit the Training Byte webinar recording here before joining this webinar. Clock domain crossing (CDC) issues remain a major problem for designers - contributing...

Join Cadence Training and Software Architect Efrat Shneydor for this free technical Training Webinar. Reflection is a unique capability in the e language, providing a deep inspection of the program, going into the verification environment code and structure, and letting you examine defined types, query current values of instances, and more. Reflections are commonly used with macros, and by using them, you’ll increase...