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Coverage Maximization

By teamspecman | 24 Aug 2016

Searching for “automatic coverage maximization” results with ~16 million hits. Alas, this does not reflect 16 million solutions, rather it is an indication of the big interest in this topic, and the many attempts to automate the process of “getting full coverage, faster”. There are several tools available, performing smart coverage analysis and directing the tests to the less covered areas. ...

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Specman | coverage | Functional Verification | Testbench simulation | Coverage-Driven Verification | CDV | e | e language | Funcional Verification | team specman | specman elite | verification
Fine Tuning of Coverage Model Definition

By teamspecman | 14 Jul 2016

Functional Coverage is one of the main means to measure the quality and progress of the verification project. We define coverage models, run semi-random tests, and every once in a while analyze the coverage report to decide “are we there yet?”. When talking about “coverage closure”, people tend to talk about generation, how we create the data that will fill the coverage. In this blog, we discuss...

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funtional verification | Specman | coverage | Functional Verification | Coverage-Driven Verification | CDV | e | e language | Funcional Verification | team specman | Verification IP modeling | metric-driven verification | MDV
Why Do We Need a Verification Language?

By teamspecman | 21 Jun 2016

This month, we celebrate the 20 th anniversary of Specman’s introduction to the public—at DAC 1996 in Las Vegas. This introduction was not simply of a new tool—it was the introduction of a new concept. Specman included e , and thus, with that introduction, the first Hardware Verification Language was born. Many of you, I suspect, were still in high school in the 1990s. You would be amazed if you saw...

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Specman | e | Aspect Oriented Programming | yoav hollander | verification
How to Find Where Declared e Entities Are Used

By teamspecman | 5 Jun 2016

The e Reflection API allows you to perform various queries on entities in your own code, and to figure out which types, fields, methods, and so on have been declared in the code, the relations between them, and their source information. However, what the Reflection API does not provide is an ability to figure out if those entities are actually used, and if so, where they are used. For example, you have declared a method...

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IEEE 1647 | funtional verification | Specman | Functional Verification | e | e language | Funcional Verification | specman elite | IES
Simulation Acceleration—Maximizing Simulator Performance

By teamspecman | 25 May 2016

"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to describe a verification environment in which the Device Under Test is synthesized and runs on the emulator, while the testbench runs on the simulator. This blog describes a technique for maximizing the performance of the simulator and thus increasing the overall performance of the Simulation Acceleration. In Simulation...

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Specman | Functional Verification | e | specman elite | verification
Building Efficient Scoreboards

By teamspecman | 18 Apr 2016

A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple: Items sent to the DUT are added to the scoreboard and stored in its data base. Items returned from the DUT (and collected by the monitors) are added to the scoreboard to be matched against the items sent. Basically, the matching...

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RTL Signoff vs. Functional Signoff

By John Brennan | 14 Apr 2016

The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification, like how much functional coverage you should use on a particular design. I promised to next talk about signoff, so here it is. There are two fundamental steps most users apply to sign-off a new design, a functional milestone...

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funtional verification | IMC | metric driven verification (MDV) | functional coverage | MDV | vManager
Modelling a Value Holder Template with the Value “new-ed” by Default

By teamspecman | 11 Apr 2016

In many companies, there is a well-defined flow for handling monitored data items: match the input data to output data (or, match a response to a request), update data, for example latency or the time from request to response, print formatted messages, and so on. One of the tools used by verification leaders to implement such company methodology and, at the same time, “pave the way” for variations in the...

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IEEE 1647 | Specman | tech tips | e | e language | specman elite | Aspect Oriented Programming | AOP | verification
How to Handle a Binding Catastrophe

By teamspecman | 28 Mar 2016

Are you busy debugging your environment topology and coming up against components getting unexpected data? Have you found yourself asking “who is passing data to this monitor, and why?”? Components in the environment interact using ports (TLM ports, method ports, simple ports, and so on). This blog tackles the challenge of debugging a “bad connection”—an in port bound to the wrong out...

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Specman | TLM | binding
e Templates – Cool Tool, Now Even Cooler

By teamspecman | 23 Mar 2016

One of the reasons why verification engineers love e is the power it gives them as no other language can. The combination of macros, reflection and extension allows you to create high quality utilities that can be shared by verification teams all over your company. Such utilities are an effective way to enhance the quality of the verification environment; the base type or template are created once by experts, and used...

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UVM-ML OA: Now Within Incisive Platform As Well!

By teamspecman | 22 Feb 2016

Open-source software has many advantages. In short: you can see it (the code), you can inspect it ( check out what Coverity revealed in the Android kernel ), and you can change it. But the fact that open-source software is not commercial also raises concerns: Is it “polished” enough? Is it thoroughly tested? How hard should I work to make it part of my product? What is the level of support? Etc. Yes, life...

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Specman | UVM-ML OA | Incisive | multi-language
Functional Verification Closure—Are We Done Yet?

By John Brennan | 12 Feb 2016

In my job as product marketing director for vManager and MDV, I get to hear this discussed all the time— when will verification be done? If not asked overtly, at a minimum it’s that rattling and clanging that you just know is going on in people’s heads as they try to formulate the questions and the concerns. So I thought I would write about it, if nothing else to stir the conversation about what is known...

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methodology | verification strategy | Functional Verification | Metric Driven Verification | vPlan | Incisive | Plan and metrics management | vManager
Using Tables to Handle Configurability in Incisive Enterprise Specman

By teamspecman | 20 Jan 2016

Most, if not all, designs which are being verified today are configurable. This is just a fact of life, with companies trying to reuse as much IP as possible in multiple different projects, or iterations of the same project. The requirements change as well (sometimes too often) and the interface protocols are getting more elaborate and layered. Just have a look at the table below: (Ref: http://www.3gpp.org The Mobile...

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IntelliGen | configurable designs | Specman | tech tips | Funcional Verification | Incisive Enterprise Specman
A Coverage Time-Saving Tip

By John Brennan | 20 Nov 2015

How often has this happened to you? You are re-using a part of a previous design in your new design, you are in the depths of coverage closure, both functional and design code coverage. You discover that many parts of the re-used design are actually not applicable in the new design, and you manually exclude those RTL lines of code. But wait – there is another design change, and your RTL now has been shifted around...

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IMC | coverage | Incisive Enterprise Simulator | Incisive | metric-driven verification | MDV | Incisive Enterprise Simulator (IES)
Incisive vManager Free Video Training

By John Brennan | 15 Sep 2015

The Incisive vManager tool for professional verification planning and management has now been officially released for almost two years. As demand for the Incisive vManager solution increases, so does our broad-scale support. Many of our users, however, are unaware of how much free training is actually available through Cadence as video content, available directly via Cadence Online Support (COS). This video content is...

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Functional Verification | Cadence Online Support | Incisive | training | vManager
Make Your Debugging Faster by Recording Your Simulator

By teamspecman | 21 Jul 2015

One of the famous quotes of Brian Kernighan is: "Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it". Well, I am not really sure he meant that no one is smart enough to debug one’s own code; however, he did mean that debugging is hard, if not even harder than coding. Hence, you...

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Specman | debug | e | specman elite | simulation | verification
Extending the e Language with Anonymous Methods

By teamspecman | 10 Jul 2015

We're happy to have guest blogger Thorsten Dworzak describe how he added anonymous methods to the vlab_util package from Verilab. So here it goes: Many programming languages like Python, Perl, and Ruby support anonymous methods[1], typically through classes or other constructs representing a block of code. These are useful to construct code by a higher-order method or to be used as arguments by higher-order methods...

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Functional Verification | Ruby | anonymous methods | e language
Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

By teamspecman | 2 Jul 2015

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But sometimes there is a need to know the exact multi-value logic, or to write an mvl value (e.g., init the signal to Z). For this purpose, the e language defines the mvl type – a predefined enumerated type, with values of MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, and MVL_N (based on the VHDL std_logic type). If you...

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performance | Specman | Functional Verification | Incisive | e | e language
The Dark Side of Constraints on 'do-not-generate' Fields

By teamspecman | 30 Jun 2015

The art of expressing hardware functionality through constraint language is often one of the trickiest parts of functional verification. Unlike procedural actions that are executed locally one by one, constraints are scattered declarative entities that define the rules for the gen actions. Therefore you don't necessarily see clearly how constraints are impacting the generation. This situation opens the door for occasional...

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IntelliGen | Specman | Functional Verification | e language | constraint coding
Debugging Multi-Language Verification Environments

By teamspecman | 29 Jun 2015

As shown in previous blog posts in the Multi-Language Verification Environment series, creating multi-language verification environments is not difficult. Using UVM-ML, we can pass data between components via TLM ports, instantiate e components within SystemVerilog (and vise versa), and configure the sub-components – independent of the verification language they are implemented in. But the real challenge, like...

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uvm | UVM-ML | multi-language verification | debugging
Aargh!!! How Can I Read Arguments from the Command Line Without argv?

By teamspecman | 15 Jun 2015

Many times a user would like to be able to modify the behavior of a program based on arguments on the command line. Let’s take as an example a user who would like to pass the name of a file which includes input parameters to the e program. In the C language this can be done using argv, which is an array of strings where each array element represents a command line argument. However, since Specman and the simulator...

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Specman | Functional Verification | e language | simulation
Multi-Language Verification Environment (#4)—Multi-Language Hierarchy

By teamspecman | 11 Jun 2015

In the previous posts in this series on Multi-Language Verification Environment, we created a multi-language environment containing UVCs implemented in e and SystemVerilog. This environment is functional—exercising the DUT interfaces containing one system-level checker—but something is flawed in this picture. We have UVCs instantiated side by side, rather than in their “natural” location...

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uvm | Functional Verification | e | universal verification methodology | e language | multi-language | verification
Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi-Language Environment

By teamspecman | 5 Jun 2015

In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog to a monitor implemented in e . In this post, we will show a fast way for adding a system-level data checker – using the UVM Scoreboard. The UVM Scoreboard is an open-source framework, implemented in e , and is released as part of the UVM e Library. For adding a scoreboard to our XSerial-to-UBus environment...

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SystemVerilog | uvm | multi-language verification | UVM Scoreboard | verification
It’s Time to Modernize Debug Data and It’s Happening at DAC

By Adam Sherilog | 4 Jun 2015

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog 1364-1995 and the open VCD syntax standard for debug data interoperability. Now the leading edge is over 1 billion gates and it’s time to modernize VCD. If you stop by the Verification Academy booth at DAC on Tuesday June 9 at 5pm, you’ll learn how. Now that I’ve piqued your interest, lets take a look...

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Verdi | debug | simvision | VCs | Indago | Debussy | Questa | Incisive Enterprise Simulator (IES) | IES
Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using UVM ML

By teamspecman | 1 Jun 2015

In the previous blog post , we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e . The architecture of the environment is as pictured here: We will now add to this environment a system-level checker, implemented in SystemVerilog. A standard recommended way for passing items is via TLM ports. For connecting ports instantiated within components implemented...

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TAGS:

IEEE 1647 | uvm | methodology | Functional Verification | e | universal verification methodology | e language | multi-language | verification

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