Community Blogs Verification

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Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

Anika Sunda
• 3 min read
featured , coverage , throughput , machine learning , Regression

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
• 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP

Moving Beyond EDA: The Intelligent System Design Strategy

The rising customer expectations, intermingling fields and high performance needs…

Vinod Khera
• 5 min read
optimality , artificial intelligence , featured , intelligent system design
Verification

Latest blogs

Understanding UCIe Design Verification Topologies

UCIe or Universal Chiplet Interconnect Express is the fastest growing chiplet interconnect…

Anunay
• 3 min read
ucie , Verification IP , chiplet , VIP , die

Accelerating Your Overall HW/SW Verification and Validation Productivity Using Dynamic…

With the increasing complexity of system-on-chip (SoC), the associated software…

Reela
• 8 min read
Analog Devices. ADI , software verification , validation , protium x2 , palladium z2 , Accelerate , productivity , Hardware/software co-verification , verification

Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

Anika Sunda
• 3 min read
featured , coverage , throughput , machine learning , Regression , simulation , verification

Training Insights – Webinar –: Solve Tricky SVA Problems with Jasper Visualize and…

Are you experienced in using SVA? It’s been around for a long time, and it’s tempting…

Nizar Hanna
• 2 min read
digital badge , online , Visualize , Jasper , training , webinar , SVA , app , verification

Flex Ethernet (FlexE): Unlocking the Physical Bandwidth Constraints

Efficient and flexible use of bandwidth is the key to optimizing traffic flow…

Krunalkumar
• 3 min read
Verification IP , 5G Network , Ethernet VIP , Functional Verification , FlexE , VIP , Flex Ethernet , Ethernet , Hyperscalers , data centers , OIF , verification

What Makes a Next-Generation Debug Solution?

For the past few decades, design and verification technology have made great progress…

Rich Chang
• 5 min read
Functional Verification , debugging tips , debugging

Improve Regression Throughput and Find Bugs at Pace

Scaling chip size and increasing functionality over SoCs has increased complexity…

Vinod Khera
• 4 min read
xcelium simulator , Xcelium ML A

Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL In…

2023 is here, and technology trends around Compute Express Link (CXL) and the next…

Sangeeta Soni
• 2 min read

USB3 Gen T Tunneling Over USB4

USB Promoter Group recently released USB4 Version 2.0 and this updated specification…

Sanjeet Kumar
• 2 min read

DDR5 DIMM Design and Verification Considerations

DDR5 is the latest generation of the DDR server memory capable of supporting data…

Shyam Sharma
• 4 min read
Verification IP , ddr5 , DDR5 DIMM , VIP , JEDEC , LRDIMM , DRAM , RDIMM , memory models , PCDDR , verification

UCIe: Enabling the Chiplet-Based Ecosystem

Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines…

JHarshit
• 2 min read
ucie , Verification IP , chiplets , System Design and Verification , VIP

Introduction to Embedded DisplayPort (eDP) version 1.5

Embedded DisplayPort 1.5 (eDP 1.5) is an interface standard that is based on the…

tfox
• 1 min read
Verification IP , Functional Verification , DisplayPort , VESA , EDP

Training Insights – VHDL Language and Application

Cadence has released a new online VHDL training course free for Cadence Customers…

Shilpa V
• 2 min read

Demonstrating PCIe 6.0 Equalization Procedure

The Link equalization procedure enables components to adjust the Transmitter and…

mrana
• 4 min read

SD Host Controller for SD Card Verification

SD Host Controller was introduced to transfer data to SD Card from system memory…

Yeshavanth BN
• 2 min read
Verification IP , host , Memory , VIP , SD

Training Insights - Brand New Free Online Course on Perspec System Verifier for Beginner…

Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification…

SANDEEP NASA
• 3 min read
Verification planning and management , verification strategy , Perspec , perspec system verifier , verification management , Verification Acceleration , System Verification , verification coverage , verification

Understanding Latency versus Throughput

One of the effects of adopting a High Level Synthesis design methodology is that…

Corporate
• 2 min read
High-Level Synthesis , throughput , ESL High Level Synthesis , Team ESL , latency , ESL

Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Py…

Join Cadence Training and Principal Application Engineer Daniel Bayer for this…

ManishaP
• 1 min read
Verification planning and management , Verisium Debug , verification

How to Verify Complex PIPE Interface Based PHY Designs?

High-end SOC architectures today requiring more area and higher speed to transfer…

Nehal Patel
• 2 min read

How Renesas Reduced Automotive SoC Verification Time

The automotive world is conquering new technological heights, piggybacking on…

Reela
• 5 min read
Automotive , verification time , Renesas , customer success , Verisium Manager , vManager

PCIe Lane Margining - What changed from Gen4 to Gen6?

With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return…

mrana
• 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification | , PCIe , pcie gen6 , PCI Express , PCI-SIG

CXL Enumeration: How Are Devices Discovered in System Fabric?

PCIe designed system fabrics rely on software enumeration by Operating System (OS…

Sangeeta Soni
• 2 min read

DisplayPort (DP) Tunneling over USB4

USB4 is an industry standard that tunnels three different protocol specifications…

tfox
• 2 min read
Verification IP , USB4 VIP , USB4v2 , USB4 DP Tunneling , DP Tunneling , usb4

Demystifying PCIe Lane Margining Technology

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology…

mrana
• 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group.…

Neelabh
• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

Somya Bansal
• 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and…

Claire Ying
• 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
• 4 min read
Verification IP , VIP , PCIe , pcie gen6 , verification
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