Functional Verification Blogs

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnects are enabling new generations of data servers and high-performance mobile devices. Being at the heart of SoCs, they introduce significant challenges to verification engineers both from functional verification and...

The new cloud, AI, Analytics, and Edge usage models with exponential data growth and connection drive the evolution of high-bandwidth PCIe (Peripheral Component Interconnect Express) version 5.0 and 6.0, CXL (Computer Express Link) version 2.0 and 3.0. Every component can be envisioned as an attack vector in modern computational systems, especially PCIe and CXL components, which are part of the system HW root-of-trust...

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification has been ubiquitous PHY interface for accelerating the design and verification of higher layer protocol stacks for more than 15 years. Since then, there have ...

I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during the previous CDC webinar "Still Relying on Static-Only CDC Signoff? Introducing the JasperGold CDC App". If you didn't have the chance to attend it, we are recommending you to visit the Training Byte webinar recording here before joining this webinar. Clock domain crossing (CDC) issues remain a major problem for designers - contributing...

Join Cadence Training and Software Architect Efrat Shneydor for this free technical Training Webinar. Reflection is a unique capability in the e language, providing a deep inspection of the program, going into the verification environment code and structure, and letting you examine defined types, query current values of instances, and more. Reflections are commonly used with macros, and by using them, you’ll increase...

As discussed in the previous blog, the AMBA® 5 specification updates introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA® 5 CHI (Coherent Hub Interface) specification. Among them is a new class of atomic transactions which make operations at the remote locations more streamlined and efficient. Another new transaction class includes the new cache stash transactions which...

LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs and networking systems built for 5G and AI Application. So not only that the JEDEC LPDDR5 specification has seriously increased in its complexity to meet higher bandw...

Thanks to all the people who attended the webinar Extend the Language! An Introduction to Specman Macros that we had on March the 17 th . If you did not attend, or attended and want to see it again – you can view Extend the Language Using Specman e Macros! Webinar Recording (Video) . The video contains English captions. Many questions were asked during the session, and under limitation of time – not all of them were...

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex systems, and provides a high-bandwidth, high-performance link for interconnecting devices imposed by cloud-based computing power, storage capacity network ban...

The industry-standard ARM AMBA® 5 protocol specifications continue to evolve, further improving performance and efficiency of key ARM architecture features. Besides the updates of powerful AMBA CHI (Coherent Hub Interface) specification with Issue D and Issue E features (which will be discussed in-depth in upcoming blogs), ARM invested in updating their highly successful and very popular AMBA AXI, ACE and AHB on-chip...

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent...

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the industry. TileLink is a free and open standard chip-scale interconnect protocol designed for RISC-V processors and beyond (could be used with other ISAs as well). It’s a fast scalable SoC communication protocol designed to connect...

All the workings of USB4 protocol are primarily about how to transfer the native protocol data through tunneling from their originating points to respective destinations. One may verify thoroughly the core layers, like logical layer and transport layer, of a USB4 design. But that is only half the job done. The next challenge comes up at verifying the tunneling of each native protocol, which are USB3, PCIe, and DisplayPort...

It won’t be incorrect to say that the transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services like paths and routing for tunneled traffic, various types of flow control, link management, which are some of the core features that make a USB4 router work the way it should. A path is like a virtual wire, which is a unidirectional...

Using Cadence ® Specman ® Elite macros lets you extend the e language ─ i.e. invent your own syntax. Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and some are very advanced utilities implementing sophisticated methodologies. With macros, you can replace long complex user code with much shorter and simpler code. And, as we know – the shorter the code is, the less...

To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies supported by its latest low power memory offering LPDDR5 to include the 937MHz and 1066MHz that translates to the max data rates of 7500MT/s and 8533 MT/s. Devices supporting these incredibly high data rates are being categorized...

Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer and non-transparent Link Training-Tunable PHY Repeater (LTTPR) device when connected. The diagram below shows the connection between the source, LTTPRs, and sink devices. The specification allows up to eight LTTPRs....

Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low form factor memory devices to process data temporarily to gain widespread adoption in the market place. HyperRam memory has all above characteristics to improve performance of end devices. The HyperRam device is the high...

RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as possible—to reduce the cost per bug—which puts additional pressure on designers. Conventional methods of design bring-up using unit-level testbenches are no longer the optimal way to address these challenges. Design teams...

Memory is an important part of every electronic system, still it is increasingly becoming a performance bottleneck. While NAND flash is primarily important in consumer and computing applications, there was no standard to help designers integrate NAND...

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to...

RTL designers are creating increasingly complex designs, and are under relentless pressure to provide assurance that the designs are complete and correct, before handing off the designs for RTL verification and implementation. This assurance needs to be provided at the block/IP level as those become mature enough for handoff, and again once the design is integrated to subsystem or chip level. Recently, the multitude...

As a verification engineer, you want your toolbox to be varied and rich. It looks trivial, but if we really ask ourselves why, there are several reasons. First , when you look for your next exciting verification position, the more HVL you know, the more options you have. In addition, you reflect yourself as a knowledgeable person for potential employers. Secondly , familiarity with several HVL, makes you a better verification...

We’re proud to see that many expert verification teams exploit the powers of UVM vr_ad, in implementing intricate verification environments in e . The vr_ad is an open source package, part of UVM- e . It provides means to access the DUT registers and memory, monitor the accesses and check the DUT registers behavior. It is indeed a flexible powerful utility. But with power comes responsibility. During the verification...

If you’re looking for an example of how well the Cadence flow fits together, look no further than Renesas and their experience using the Cadence System Testbench Generator and System Performance Analyzer alongside Perspec and Palladium. With development time requirements shrinking while designs grow, verification engineers and chip designers need access to every advantage they can get, and there’s few ways you can improve...