Functional Verification Blogs

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to...

RTL designers are creating increasingly complex designs, and are under relentless pressure to provide assurance that the designs are complete and correct, before handing off the designs for RTL verification and implementation. This assurance needs to be provided at the block/IP level as those become mature enough for handoff, and again once the design is integrated to subsystem or chip level. Recently, the multitude...

As a verification engineer, you want your toolbox to be varied and rich. It looks trivial, but if we really ask ourselves why, there are several reasons. First , when you look for your next exciting verification position, the more HVL you know, the more options you have. In addition, you reflect yourself as a knowledgeable person for potential employers. Secondly , familiarity with several HVL, makes you a better verification...

We’re proud to see that many expert verification teams exploit the powers of UVM vr_ad, in implementing intricate verification environments in e . The vr_ad is an open source package, part of UVM- e . It provides means to access the DUT registers and memory, monitor the accesses and check the DUT registers behavior. It is indeed a flexible powerful utility. But with power comes responsibility. During the verification...

If you’re looking for an example of how well the Cadence flow fits together, look no further than Renesas and their experience using the Cadence System Testbench Generator and System Performance Analyzer alongside Perspec and Palladium. With development time requirements shrinking while designs grow, verification engineers and chip designers need access to every advantage they can get, and there’s few ways you can improve...

Asynchronous designs happen. They’re not particularly easy to verify, but sometimes they’re necessary. If you don’t have a system clock, or if you have controllers that operate at a high speed with low power dissipation, or even if you do have a system clock but it’s noisy, your design may be asynchronous, and that’s okay. It’s no secret that asynchronous designs are a challenge —so what can you do to make sure they...

If you’re not familiar with the Arm/Cadence collaboration , you’ve been missing out. Arm has been using Cadence’s virtual system platform—Palladium ® Z1 for emulation and Protium S1 for prototyping—for years, and with these, Arm powers their wide array of fast models for virtual prototyping to make the emulation process even faster than it already is. Interested? Well, it’s no secret that virtual prototyping is the...

Looking to learn more about the best practices for emulating today’s billion-gate-plus designs? Rest assured—we’ve got you covered. Cadence has been partnered with Nvidia Mellanox for years, helping them build complete end-to-end solutions for everything from networking to data centers. Mellanox provides and handles every aspect of the process , and they’ve got a long track record of delivering breakthrough technology...

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic Simulator has a new feature just for you. Harnessing the power of machine learning, which is one of the areas of computational software innovation, Xcelium ML is here to help you optimize your regressions. The inherently iterative, data-driven nature of simulation seems ripe for a machine-learning assisted tool, and Xcelium ML is here...

UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology in our current industry. With the growing use of UVM methodology, engineers need to have an in-depth knowledge. For someone getting started with UVM, it can be challenging and a steep learning curve. So, we offer a comprehensive and adaptable course SystemVerilog Accelerated Verification with UVM to sharpen your UVM skills . This...

I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor whom I could ask all my queries. But most of the time, I was on my own, as "learning by doing" was the motto of my mentor. Today, after completing 20 years at Cadence, I can tell you that it works great, especially in cases where the tool...

In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using-coverage-callback - we shared some ideas about how to employ the new Coverage Callback API for increasing the tests efficiency. This blog shows two more ideas for improving tests, using runtime coverage information. Stop the Run After the Goal Is Reached The basic concept of Coverage Driven Verification is running many random tests...

Most have heard the phrase "time is money". Thinking more about it, probably the right phrase would be "time is more valuable than money". People look at their bank accounts with great attention but don't tend to look at their time the same way, ending up wasting this greatly valuable and important resource. You can gain money using time, but you can’t use money to purchase more time. The “Shift Left” concept has been...

When you go to the store, you walk until you get there, stop, get your groceries, and go back home. You do not start circling around the block for few rounds. You do not say “if I walk around the block really fast, I can save time”. It is clear that if you avoid circling the block at first place – you will save even more time. Why don’t we adopt the same rationale in the verification process? Instead of thinking just...

Our customers’ tests have become more complex, longer, and consume more resources than before. This increases the need to optimize the regression while not compromising on coverage. Some advanced customers of Specman use Machine Learning based solutions to optimize the regressions while some use simpler solutions. Based on a request of an advanced customer, we added a new Coverage API in Specman 19.09 called Coverage...

Curious about what’s going on behind the scenes with verification? Bernard Murphy, Jim Hogan, and our own Paul Cunningham are on the case with the “Innovation in Verification” blog stream over at semiwiki.com . Every month, this trio reviews a newly-published paper in academia that pertains to verification and discusses its implications. Be sure to stop by—it’s a great place to see what might be coming down the pipeline...

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online now! 1) Indago 19.09 Better Driver Tracing and More Are you new to Indago and not sure where to start? Luckily, there’s a new Rapid Adoption Kit for you: the Indago 19.09 Overview RAK! This neat package contains everything you need to get your debugging started through Indago. In four short labs, plus a brief introductory lab, you...

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3: According to the 2018 StackOverflow Developer Survey , the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking: Visual Studio Code 34.9% Visual Studio 34.3% Notepad++ 34.2% Sublime Text 28.9% Vim...

In the former blog about Python and Specman: Specman: Python Is here! , we described the technical information around Specman-Python integration. Since Python provides so many easy to use existing libraries in various fields, it is very tempting to leverage these cool Python apps. Coverage has always been the center of the verification methodology, however in the last few years it gets even more focus as people develop...

If you missed the first part of this series, you can find it here . So: what does Green Hills Software propose we do? The issue of “solving security” is, at its core, impossible—security can never be 100% assured. What we can do is make it as difficult as possible for security holes to develop. This can be done in a couple ways; one is to make small code in small packs executed by a “safing plan”—having each individual...

Autonomous vehicles are coming. In a statistic from the U.S. Department of Transportation , about 37,000 people died in car accidents in the United States in 2018. Having safe, fully automatic vehicles could drastically reduce that number—but the trick is figuring out how to make an autonomous vehicle safe. Internet-enabled systems in cars are more common than ever, and it’s unlikely that the use of them will slow or...

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out...

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019. What people refer to as “the cloud” is commonly divided into three categories: Infrastructure...

Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater...

Welcome back to this account of the IP Security Panel at the Accellera Luncheon at DAC 2019. We’ve covered who’s seated on the panel and the moderator’s questions in the last installment (link to first blog)—now it’s time to talk about what the audience had to ask. The first question asked was related to that morning’s keynote speaker, and that speaker’s one criteria for IP developers with regards to security: do they...