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Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High Performance Computing Servers

By XTeam | 25 Oct 2018

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching system design enablement collaboration, the Cadence Verification Suite is ready for use on Arm®-based high-performance computing (HPC) server environments. Now, all of the Cadence verification software tools you know and love—including Xcelium Simulator—can be run on the Hewlett Packard Enterprise (HPE) Apollo 70 system, which uses...

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press release | HPC | ARM | announcement
Learn How Valens uses Specman Macros Automate Configuration of Verification Environments at DVCon EMEA Next Week

By Steve Brown | 16 Oct 2018

Valens has achieved success through applying Specman to their verification projects. At DVCon EMEA (Oct 24-25) you can learn how their use of Specman Macros to automate configuration of the verification environment to their design. This saves them effort and lowers the learning curve for engineers who jump from project to project. In collaboration with Veriest Verification Ltd , a Cadence Connections Verification partner...

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verification
Improving Your Testbench Flexibility with Enhanced Specman Templates

By Steve Brown | 8 Oct 2018

Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible with the Open Verification Methodology (OVM), the Universal Verification Methodology (UVM), and the eReuse Methodology (eRM), so you can quickly and easily integrate it with established verification flows. Attend our...

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Specman 18.09: Avoiding the Small Annoying Mistakes

By teamspecman | 8 Oct 2018

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article takes the small mistakes to the extreme and mentions a few cases of small mistakes that had a huge effect: Messing up big time: 10 tiny mistakes that have caused HUGE problems . How is it relevant to Specman? As a verification...

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enumerator | Specman | Functional Verification | e | e language | specman elite | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Objects

By XTeam | 8 Oct 2018

Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the...

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performance | SystemVerilog | Functional Verification | xcelium simulator
Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

By XTeam | 12 Sep 2018

Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling in ways you may not be aware of. We’ll be covering the following topics: How to use user-defined front doors and back doors to expand what the register layer can do Understanding the role played by the predictor...

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uvm | Functional Verification | webinar | Duolos | uvm register layer
Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much Time?

By teamspecman | 30 Aug 2018

One animation video - Patch Like The Wind - is worth a thousand words :) If you don’t use Specman or don’t use Specman correctly, you spend most of your time waiting for compilation to finish. One of the most frustrating (and common…) scenarios is when you know more or less what the fix should be (such as, “wait additional cycle before sending” or “the variable should be int and not uint”) and the fix can be...

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Specman | Specman/e | Functional Verification | Specman e | tech tips | e language | team specman | save and restart
Tales From DAC: Netspeed and the Cadence Interconnect Workbench Pair Up

By XTeam | 27 Aug 2018

Services like facial detection, efficient cloud server workload management, artificial intelligence, and image enhancement are all the rage these days; but creating a design to accommodate these needs can be incredibly taxing on your engineering resources. Luckily, Netspeed Systems is here to help. The devices being designed nowadays are more complicated than ever, and the design requirements are more complex, too...

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cadence IWB | Interconnect Workbench | Functional Verification | gemini | netspeed
Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meetings

By XTeam | 31 Jul 2018

We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it was a virtual meeting—but those never really feel the same in person, do they? Attending a virtual meeting can feel cold and impersonal, especially since you can barely see everyone else. Everyone is there except you—and even then, saying you’re “there” is a bit of a stretch. Nowadays, though, there’s technology to remedy this problem...

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Functional Verification | DAC 2018 | Altia Systems | xcelium
Tales From DAC: How Syntiant Went From Zero to Tapeout in Six Months

By XTeam | 23 Jul 2018

Here’s something to chew on: Syntiant is an AI startup involved in deep learning technology and semiconductor design. Their goal is to create exceptionally low-power designs for always-on devices, like those used in speech detection. Syntiant went from empty air to tapeout in six months. That sounds hard to believe, but it’s true. They got their first venture-capital funding in October of 2017, taped out initial...

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DAC | Functional Verification | syntiant | DAC 2018 | cadence cloud
Is it Time to Verify Your Chips in the Cloud? Part 3 of 3

By XTeam | 28 Jun 2018

Welcome back to our series on cloud verification solutions. This is the final part of a three-part blog—you can read part one here and part two here . Now, for the moment you’ve all been waiting for: what can Cadence do for you in the realm of cloud verification. Are you ready? In case you saw that list of qualities one should look for in a cloud partner in the last part of this blog, and wondered who ticks all those...

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security | Functional Verification | cadence cloud | xcelium | palladium cloud
UVM-ML- Managers’ Freedom of Choice

By teamspecman | 28 Jun 2018

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is defined in wikipedia as “an individual's opportunity and autonomy to perform an action selected from at least two available options…”. Is having many choices always a good thing? Well, usually it is- who would not want to live in a world where s/he has options and can make choices? However, there are also downsides to having multiple...

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Specman | Specman/e | UVM-ML | Specman e | UVM multi-language | UVM-e | UVM ML | multi-language | multi-language UVM | multi-language verification | verification
Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

By XTeam | 21 Jun 2018

Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here . The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020—that’s an annual growth rate of almost 20%. Cloud providers and other related companies are putting more and more resources into building solutions for this...

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uvm | Functional Verification | EDA | HPC | cadence cloud
App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog Data Structures

By XTeam | 21 Jun 2018

Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium...

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SystemVerilog | Tip | Functional Verification | App Note Spotlight
Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

By XTeam | 15 Jun 2018

Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud. For a while now, there’s been a growing interest in cloud-based EDA solutions, but the time wasn’t ripe for production deployment. People had concerns about security and the sustainability of the data centers. But nowadays, public clouds are highly secure, typically more secure...

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cloud-based verification | Functional Verification | cadence cloud | cloud computing
DMS 2.0 - What's Cool and What's New

By XTeam | 11 Jun 2018

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and wonderful features to help you use Xcelium to verify your mixed-signal designs. The level of interaction between analog structures and digital logic is a lot more complex than it used to be. Divide-and-conquer verification isn...

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digital mixed signal | Functional Verification | DMS 2.0 | xcelium simulator
Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

By XTeam | 7 Jun 2018

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April 2018. One of the fields Microsemi operates in is the realm of optical networking. In optics, a given sensor’s input can vary wildly, but the way the input is processed is largely the same. Thus, a wide variety of tests are...

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SystemVerilog | uvm | Dynamic Test Load | Functional Verification | xcelium
RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs

By XTeam | 5 Jun 2018

The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to verify one of the most critical technology convergences in IoT devices. It’ll talk about the differences in verification of a processor-based design whether it’s powered internally or externally, how to verify SPICE, SystemVerilog...

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Low Power | Functional Verification | RAK | power intent | mixed signal
App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog Semantics

By XTeam | 4 Jun 2018

Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator...

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performance | SystemVerilog | Functional Verification | xcelium simulator
Empowering Generation - Range Generated Fields (RGF)

By teamspecman | 31 May 2018

Specman constraints solver process consists of a series of reductions and assignments . It reduces the range of the field value based on the constraints, and then assigns to it a random value from the reduced range. After assigning one field, the range of all connected fields is reduced accordingly, and the process continues until all fields are assigned. A new feature added in Specman 18.03 – Range Generated Fields...

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Specman | Specman/e | Generation | e language | Constraints
Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress, and HyperRAM

By XTeam | 3 May 2018

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM high-speed memory. We also unveiled a new JEDEC Universal Flash Storage 3.0 (UFS) VIP. Together, these three new VIPs allow early-adopters to leap off the starting line in the race to create new, incredible SoCs and IPs incorporating...

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hyperRAM | Functional Verification | coaxpress | UFS | press release
Xcelium's New Save and Restart Saves You Time

By XTeam | 5 Apr 2018

You may have heard about the overhaul to the old save/restart mechanism that was in Incisive—but are you aware of what the new Xcelium Simulator version can do? While the old version is still supported, there’s a lot of benefits to shifting to the new one. Now called “checkpointing,” this new system uses a process-based implementation and is overviewed in the app note, Using Save/Restart Checkpointing with Xcelium...

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save and restart | xcelium | save and restore | checkpointing
List of TLM Analysis Ports: Where Is This Packet Coming From?

By teamspecman | 1 Apr 2018

Let’s say that you got an invitation from the police station nearest your home to be there the next day at 14:00. Hmm…. What could it be about? You check the letter and envelope for more information, but it does not say which department sent it. Well, it makes a big difference if the invitation was from the “lost and found” department, which means you will probably get something back, or if it came from “investigations...

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Specman | Functional Verification | e | e language | team specman | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part I

By XTeam | 19 Mar 2018

Welcome to a special multi-part edition of the App Note Spotlight, where we’ll be highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerliog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator—in fact, they...

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SystemVerilog | Object Oriented Programming | Functional Verification | Optimize
Temporals, Reset, and Test Phases

By teamspecman | 11 Mar 2018

One of the biggest challenges in dynamic functional verification is testing Reset – resetting the DUT during simulation and check DUT operation afterwards. The main challenges are propagating the reset information in the testbench, and adjusting the components behavior. For performance and accuracy, it is best to have one agent controlling and monitoring the reset, rather than each and every agent monitoring the reset...

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Specman | UVM e | Specman e | e | e language

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