AMBA LTI Verification IP for Arm System MMU

The AMBA LTI (Local Translation Interface) defines the point-to-point protocol between an I/O device and the TLBU (Translation Buffer Unit) of an Arm System Memory Management (SMMU). The LTI protocol is used by systems built based on the Arm System SMMUv3 architecture specification.

The LTI protocol defines three different channels to request a translation for each transaction coming from an I/O Device. Additionally, it defines interface management signals and credit signals for flow control. LA and LR channels can have multiple virtual channels, which enable one VC to progress when another is blocked to avoid deadlock scenarios and can result in higher bandwidth.

LTI Channel

The LTI interface contains the following channels:

• LA Request channel: Address and attributes that require translation are sent to the TBU.
• LR Response channel: Provides the translated address and attributes to the LTI device.
• LC Completion channel: LTI devices must provide information about completion to the TBU.

As shown in the following image, the LTI Manager sends the request on the LA channel for each transaction from the device, which requires a translated address. LTI-TBU component passes the translated address and response on the LR channel. LTI enables devices to directly request a translation for each transaction while leaving the TBU to manage the Translation Lookaside Buffer (TLB). If LTI-TBU does not have a translated address, it sends a request to the TCU component using DTI protocol and forwards the translated address to the LTI Manager. For each translation response, the LTI Manager sends a completion message using the LC channel.

LTI Transaction Flow

A complete LTI transaction consists of a message on all three channels as shown below figure.

• The manager sends a request to the LA channel.
• The subordinate sends a response on the LR channel, enabling the translated transaction to be issued downstream.
• The manager sends a completion on the LC channel, once the downstream transaction is complete.

The following diagram represents the timing for the transactions initiated from device flows through the system.

Cadence AMBA LTI VIP provides complete solutions with Active Drive and Passive Agent with exhaustive protocol checks, functional coverage, and building block sequences to implement complex test cases. The following image represents back-to-back VIP communication where each Active VIP component can be replaced with RTL for verification.

LTI Verification IP provides different levels of callbacks for score boarding and erroneous scenarios.

More Information

Cadence provided complete Verification IP solution for unit level to SoC level Verification.

More details are available in Simulation VIP for AMBA LTI pages.

To get more details on Cadence Simulation Verification IP, please visit our website Cadence Simulation VIP or simply reach out to discuss with Cadence Verification IP experts.