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Featured

Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

Anika Sunda
Anika Sunda 6 Feb 2023 • 3 min read
featured , coverage , throughput , machine learning , Regression

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
xinmu 12 Oct 2022 • 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP

Moving Beyond EDA: The Intelligent System Design Strategy

The rising customer expectations, intermingling fields and high performance needs…

Vinod Khera
Vinod Khera 22 Sep 2022 • 5 min read
optimality , artificial intelligence , featured , intelligent system design
Verification

Latest blogs

PCIe Lane Margining - What changed from Gen4 to Gen6?

With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return…

mrana
mrana 31 Oct 2022 • 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification | , PCIe , pcie gen6 , PCI Express , PCI-SIG

CXL Enumeration: How Are Devices Discovered in System Fabric?

PCIe designed system fabrics rely on software enumeration by Operating System (OS…

Sangeeta Soni
Sangeeta Soni 27 Oct 2022 • 2 min read

DisplayPort (DP) Tunneling over USB4

USB4 is an industry standard that tunnels three different protocol specifications…

tfox
tfox 24 Oct 2022 • 2 min read
Verification IP , USB4 VIP , USB4v2 , USB4 DP Tunneling , DP Tunneling , usb4

Demystifying PCIe Lane Margining Technology

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology…

mrana
mrana 21 Oct 2022 • 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group.…

Neelabh
Neelabh 19 Oct 2022 • 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

Somya Bansal
Somya Bansal 19 Oct 2022 • 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and…

Claire Ying
Claire Ying 17 Oct 2022 • 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
xinmu 17 Oct 2022 • 4 min read
Verification IP , VIP , PCIe , pcie gen6 , verification

Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
xinmu 14 Oct 2022 • 4 min read
Verification IP , PCIe , pcie gen6 , verification

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu
xinmu 12 Oct 2022 • 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP , PCIe , pcie gen6 , verification

Importance of MDIO Interface for Ethernet.

M edia I ndependent I nterface M anagement ( MIIM ), or M anagement D ata I nput…

AyushK
AyushK 12 Oct 2022 • 1 min read
Verification IP , uvm , SoC verification , IP verification , Ethernet VIP , Functional Verification , Cadence VIP portfolio , MDIO Interface , Ethernet

USB4 Version 2.0 Announced

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification…

Neelabh
Neelabh 10 Oct 2022 • less than a min read
usb4

Struggling with Coverage Convergence – Give your Verification Wings with Xcelium…

Functional verification consumes more than 70% of the labor invested in today’s…

Anika Sunda
Anika Sunda 6 Oct 2022 • 1 min read
coverage , machine learning , xcelium , simulation

USB4 Interoperability with Thunderbolt™︎ 3 (TBT3) Systems

One of the key goals for USB4 is to retain compatibility with the existing ecosystem…

Anshul Shah
Anshul Shah 26 Sep 2022 • 2 min read
Verification IP , USB4 VIP , usb4 , usb4 router

Moving Beyond EDA: The Intelligent System Design Strategy

The rising customer expectations, intermingling fields and high performance needs…

Vinod Khera
Vinod Khera 22 Sep 2022 • 5 min read
optimality , artificial intelligence , featured , intelligent system design

TSN-PTP: A Real-Time Network Clock Synchronizing Protocol

In a network containing multiple nodes, the need for synchronization between the…

Vedansh Seth
Vedansh Seth 11 Sep 2022 • 2 min read
Verification IP , uvm , 5G Network , Ethernet VIP , Functional Verification , Cadence VIP portfolio , VIP , Automotive Ethernet , Ethernet , TSN , PTP , precision timing protocol , verification

Flash Toggle NAND 4.0 in a Nutshell

NAND Flash memory is now a widely accepted non-volatile memory in many application…

GauravJ
GauravJ 31 Aug 2022 • 2 min read
Verification IP , Memory , flash , VIP , verification

Achieve 80% Less Late-Stage RTL Changes and Early RTL Bug Detection

It has become challenging to ensure that the designs are complete, correct, and adhere…

Vinod Khera
Vinod Khera 15 Aug 2022 • 5 min read
featured , Jasper RTL Designer Signoff App , Jasper , Early Bug Detection

JEDEC UFS 4.0 for Highest Flash Performance

Speed increase requirements keep on flowing by in all the domains surrounding us…

Yeshavanth BN
Yeshavanth BN 11 Aug 2022 • 2 min read
Verification IP , Memory , UniPro , MIPI Alliance , IoT , VIP , JEDEC , UFS , storage , MPHY

Coalesce Xcelium Apps to Maximize Performance by 10X and Catch More Bugs

Xcelium Simulator has been in the industry for years and is the leading high-performance…

Anika Sunda
Anika Sunda 1 Aug 2022 • 1 min read
performance , featured , SoC , apps , xcelium , simulation , verification

Stay Ahead of Competition with Real-Time Cross-Team Collaborations

To stay ahead in competition in chip design real-time collaborations ensure traceability…

Vinod Khera
Vinod Khera 25 Jul 2022 • 4 min read
collaboration , Palladium , verification management , Traceability , vManager

Xcelium PowerPlayBack App and Dynamic Power Analysis

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay…

Vinod Khera
Vinod Khera 18 Jul 2022 • 5 min read
Dynamic Power Analysis , xcelium , power

Jasper C2RTL App for Datapath Verification

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every…

Vinod Khera
Vinod Khera 12 Jul 2022 • 5 min read
Datapath Verification , c2rtl , Jasper C2RTL , Equivalence Checking

Cadence in Collaboration with Arm Ensures the Software Just Works

The increase in compute and data-intensive applications and the need for lower power…

Vinod Khera
Vinod Khera 11 Jul 2022 • 6 min read
SBSA , Emulation , Pre Silicon compliance Testing , Arm SystemReady

Automotive Revolution with Ethernet Base-T1

The automotive industry revolutionized the definition of a vehicle in terms of safety…

Krunalkumar
Krunalkumar 7 Jul 2022 • 2 min read
Automotive , Verification IP , PTPOverMacSec , 100BaseT1 , uvm , Ethernet VIP , Functional Verification , Cadence VIP portfolio , VIP , Automotive Ethernet , 10BaseT1 , e , Ethernet , TSN , PTP , BaseT1 , 1000BaseT1 , Ethernet PHYs , MacSec , verification

Data Integrity for JEDEC DRAM Memories

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b…

Shyam Sharma
Shyam Sharma 6 Jul 2022 • 3 min read
Verification IP , ddr5 , Memory , DDR5 DIMM , VIP , JEDEC , DRAM , lpddr5 , data integrity , NVDIMM , verification

5X “Time Warp” in Your Next Verification Cycle Using Xcelium Machine Learning

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated…

Anika Sunda
Anika Sunda 21 Jun 2022 • 1 min read
xcelium ml , machine learning , xcelium , simulation

Quest for Bugs – The Constrained-Random Predicament

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of…

Anika Sunda
Anika Sunda 14 Jun 2022 • 2 min read
compression , throughput , machine learning , Hard to Hit Bin , Coverage Closure , Regression , simulation
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