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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

NVMe 2.0 Explained: What’s New and Why It Matters

Non-Volatile Memory Express (NVMe) has become the dominant protocol for high-performance…

• 5 min read
NVMe 2.0 , Verification IP , non-volatile memory , NVM Express , NVMe , Non-Volatile Memory Express , VIP , Zoned Namespaces , NVMe Verification IP , NVMe specification , ZNS

Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training

USB4 systems rely on retimers to enable reliable high-speed communication across…

• 5 min read
USB4 VIP , usb4 , retimers

The Infineon Automotive Ecosystem Summit 2026

The 2026 Infineon Automotive Ecosystem Summit took place in late June at the Infineon…

• 2 min read
Automotive , Infineon , vlab , Digital Twins

Demystifying Address Translation Services (ATS) in PCIe 6.0

Address Translation Services (ATS) is one of the toughest verification problems to…

• 5 min read
Verification IP , VIP , PCIe 6.0 , ATS , verification

Enhancing Ethernet Security with MACsec

Understanding MACsec in Today’s Ethernet World Today, Ethernet is being widely…

• 4 min read
MACsec Verification , Ethernet VIP , Ethernet Security , IEEE 802.1AE , VIP , Cadence VIP , Ethernet , MacSec

Ethernet Auto-Negotiation: Enabling Seamless Link Optimization

Ethernet has evolved significantly from 10 Mbps shared media to today’s multi-hundred…

• 3 min read
Ethernet 800G , Verification IP , uvm , Ethernet VIP , Functional Verification , Ethernet , Ethernet UEC , ethernet 1600G

DDR5 MRDIMM: A Transformational Evolution for DDR5 DIMM

DDR5 is the latest generation of DDR server memory capable of supporting data rates…

• 3 min read
Verification IP , ddr5 , DDR5 MRDIMM , VIP , JEDEC , MRDIMM , DRAM , Dual In Line Memory , DDR5DIMM

Controller Memory Buffer (CMB): NVMe 2.0’s On-Controller Memory Feature

Non-volatile Memory Express (NVMe) has become the dominant interface protocol for…

• 4 min read
Verification IP , Functional Verification , NVMe , VIP , verification

Inside Akeana and Cadence’s Secret Sauce for Faster RISC-V Chip Verification

The Nightmare of Chip Testing (And How to Fix It) Let's be real: designing ambitious…

• 2 min read
cadence , System Design and Verification , Emulation , verification

Cadence Announces PCIe 8.0 Verification IP Availability at PCI‑SIG US

At the recent  PCI ‑ SIG Developers Conference US held on May 6-7,2026 , Cadence…

• 2 min read
Verification IP , Functional Verification , pcie 8.0

VLAB at the MATLAB Expo Japan 2026

The Cadence VLAB team will be part of the Cadence team present at the MATLAB Expo…

• 1 min read
Automotive , Simulink , vlab , MBSE , Testing , event , verification , Matlab

Unraveling Precision Time Measurement (PTM)

Introduction Precision Time Measurement (PTM) is an optional capability for communicating…

• 5 min read
Verification IP , PCIe 6.0

Unraveling Embedded Clock Mode in MIPI D-PHY: Simplifying High-Speed Serial Link

As flagship smartphones push camera sensors beyond 200 megapixels and display resolutions…

• 3 min read
Verification IP , Clock Data Recovery , Embedded clock mode , MIPI D-PHY , PHY Verification , verification

Struggling to Rewrite Functionality in PSS? Import Functions Streamlines

One of the most powerful features of the Portable Stimulus Standard (PSS) is the…

• 9 min read
Perspec , System Design and Verification , perspec system verifier , import function , pss

C-PHYv3.0 Verification, 35% Throughput Boost for Camera and Display Designs

With the evolution of advanced camera systems and higher-resolution displays for…

• 4 min read
Verification IP , PHY Layer , CPHYv3.0 , 18 Wire state Mode , Camera and Display Interface Design , MIPI-CPHY

EUSB2 V2 Explained: Multi Gigabit Symmetric and Asymmetric Operation

eUSB2‑V2 is stepping into the spotlight at a time when hardware designers are being…

• 4 min read
Verification IP , eUSB2v2 , eUSB , verification

Powering the Future of Memory-Centric Computing with CXL 4.0 VIP

CXL 4.0 Verification IP Now Available! Empowering Advanced AI, HPC, and Data-Centric…

• 2 min read
Verification IP , CXL3.0 , verification

Cadence VLAB at the Embedded World 2026

Just like every year, the Embedded World took place in Nürnberg in mid-March. It…

• 5 min read
Automotive , virtual platforms , vlab , Embedded World

UCIe Manageability: The Hidden Control Plane of Chiplet Systems

Chiplet-based architectures are quickly becoming the foundation of next-generation…

• 2 min read
ucie , Verification IP , multi-die , VIP

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI , verification

What Makes LPDDR6 a Key Technological Advancement for DRAM Memory Technologies

Low-power DDR SDRAM is one of the most widely used memory types in the semiconductor…

• 4 min read
Storage Technology , Verification IP , Memory , LPDDR , LOW POWER DRAM , JEDEC , DRAM , memory models , Lpddr6

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System

Modern embedded systems are becoming increasingly compact, power efficient, and feature…

• 3 min read
SerialWireDebug , SWD

Breaking Down UPLI: A Protocol-Level Perspective on UALink 200

In the evolving landscape of high-performance computing, particularly in AI and ML…

• 3 min read
UAL , protocol layer , AI Accelerator , UALink , UPLI , AI

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that…

• 5 min read
UAL , protocol layer , VIP , UALink , UPLI

Cadence VLAB at the Automotive Software Frontier

The VLAB team at Cadence is participating in the 11th Automotive Software Frontier…

• less than a min read
Automotive , vlab , virtual platform , embedded software , event

Palladium – Power Estimation Efficiency from Days to Minutes

In the competitive semiconductor industry, leading innovators consistently set the…

• 2 min read
System Design and Verification , Palladium , SVG , dpa , Power Analysis , hsv , verification

Cadence’s Training and Education Journey Through 2025

As we step into 2026 , it's a great time to reflect on the most popular blogs and…

• 5 min read
digital badge , live training , blended training , System Design and Verification , Protium , SVG , accelerated learning , verisium , Jasper , webinar , training bytes , Stratus , ask , RAKs , verification , tcl

Virtual Platforms Keynote at RAPIDO 2026

Jakob Engblom from Cadence will be presenting a keynote at the RAPIDO (Rapid Simulation…

• less than a min read
Automotive , virtual platforms , vlab , verification
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