Verification(Verification of System and Software) Blogs

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.  

Amongst many new features and changes in PCIe 6.0, we will…

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.  

Amongst many new features and changes in PCIe 6.0…

Media Independent Interface Management (MIIM), or Management Data Input/Output (MDIO), is a serial bus protocol and is used for the IEEE 802.3 Ethernet standard and Media Independent Interface (MII). The MIIM/MDIO protocol is a simple two-wire serial interface with specific terminology to define the various devices on the bus. The device driving the MDIO bus is identified as the Station Management Entity (STA). The STA…

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification, which will enable up to 80 Gbps operation over the USB Type-C® cable and connector.

As per this announcement, the key characteristics of the updated USB4 solution include: 

• Up to 80 Gbps operation, based on a new physical layer architecture, using existing 40 Gbps USB Type-C passive cables and newly-defined 80 Gbps USB…

Functional verification consumes more than 70% of the labor invested in today’s SoC designs. Yet, even with such a large investment in verification, there’s more risk of functional failure at tape out than ever before. The primary reason is that the design team does not know where they are, in terms of functional correctness, relative to the tape-out goal. Coverage Closure in SoC verification is like chasing a mirage…

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt  products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3…

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and…

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication…

NAND Flash memory is now a widely accepted non-volatile memory in many application areas for data storage such as digital cameras, USB drive, SSD and smartphones. One form of NAND flash memory, Toggle NAND, was introduced to transmit high-speed data asynchronously thus consuming less power and increasing the density of the NAND flash device. 

The initial Toggle NAND versions had memory arranged in terms of SLC (Single Level…

It has become challenging to ensure that the designs are complete, correct, and adhere to necessary coding rules before handing them off for RTL verification and implementation. RTL Designer Signoff Solution from Cadence helps the user identify RTL bugs at a very early development stage, saving a lot of effort and cost for the design and verification team. Our reputed customers have confirmed that using RTL signoff for…

Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity. 

UFS is…

Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that ar...

To stay ahead in competition in chip design real-time collaborations ensure traceability, speedy innovations at reduced the cost.

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms for glitch-accurate power estimation of multi-billion gate SoC designs.

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...

The automotive industry revolutionized the definition of a vehicle in terms of safety, comfort, enhanced autonomy, and internet connectivity. With this trend, the automotive industry rapidly adopted automotive Ethernet such as 10Base-T1, 100Base-T1, and in some cases, 1000Base-T1. 

Faster Speed (than CAN-FD), Scalability, embedded security protocols (like MacSec), cost and energy efficiency, and simple yet redundant network…

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and 1c nodes along with the DRAM device speeds going up to 8533 for Lpddr5/8800 for DDR5, Data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed.

It’s a complicated problem that requires…

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.

Design patterns for modeling configuration and reconfiguration in PSS (Portable Stimulus)

It is always beneficial to detect the defects early in the development phase prior to silicon bringup. Learn How Cadence Helium Virtual and Hybrid Studio helps in Pre-Silicon Bring up and HW/SW Co-Verification. The Helium Studio allows designers to build high-quality virtual and hybrid SoC models. Through the native integration of the runtime software engine of the Helium Studio with the Palladium Z2 platform and the…

Broadcom developed a code coverage signoff flow using Xcelium simulator’s constant propagation, and Jasper UNR App. So, in conclusion about this entire flow and the benefits of unreachability analysis from Jasper, the constant propagation and Jaspergold unreachability app helped Broadcom in reducing the effort of code coverage holes review and signoff to days. Broadcom was able to prioritize the area of stimulus generation…

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past, you might have heard Compute Link Express (CXL) is break-through technology for modern day compute requirements driven by high-performance computing, cloud, AI and ML. Of course, CXL buzz is for real and is well resonating with big industry players in processing and storage landscape.  We are already seeing pre-production CXL design demos…

Verifying bus performance by analyzing bandwidth and latency over time in chips is tricky. Renesas in collaboration with Cadence used a comprehensive emulation package and designed a new efficient bus performance verification scheme that helped them to witness a stellar performance with 160x speedup in actual simulation or emulation itself along with 16x speed up in bandwidth and latency calculation and extracting the…