Cooking Up Better Performance for Arm-Based SoCs

With increasing complexity, ascertaining performance in Arm-based SoCs design has become challenging, as it involves system-wide protocols connecting multiple IP in collaboration to deliver the expected performance. Verification teams must do the performance verification at the system level to ensure data integrity and avoid any bandwidth throttling or cache coherency issues at a later stage. However, it is difficult for developers to evaluate this combination's performance running the anticipated mix of workloads. Integrating more functionality and multicores suits the customer's expectations and market demands, but it introduces tremendous challenges for SoC verification teams, such as:

• Performance validation at the system level
• Domain-specific performance analysis to ensure the expectations are met
• Verification to ensure efficient third-party IP integration
• SoC-level data integrity/cache coherence check before tapeout
• Lack of automation in traditional schemes
• Enhancing productivity while conducting in-depth system-level performance verifications

Performance Cookbook for Arm: A Savior

To overcome such challenges, developers must understand how these critical system functions work together to ensure optimum system performance before committing to silicon. The Performance Cookbook for Arm^® by Nick Heaton of Cadence and Colin Osborne of Arm is based on years of collaborative effort between Cadence and designers. It is a deep dive into the intricacies of designing high-performance Arm-based SoCs, offering insights into the latest design methodologies, performance optimization strategies, and analysis techniques.

Ziyad Hanna, corporate vice president of the System Verification Group at Cadence, describes the Performance Handbook for Arm as an invaluable resource covering Arm systems' architectural evolution, defining key performance aspects of each AMBA protocol, and explaining the key mechanisms that can influence the performance of Arm systems:

The book also addresses the challenges of designing for specific workloads and applications, from mobile and data center infrastructure to automotive ADAS compute. It guides configuring various IP to match service priorities for workloads and effectively compares architectural and configuration tradeoffs.

The book helps developers grasp the continuous evolution of Arm SoCs. It explains Arm’s big.LITTLE^tm strategy, distributed virtual memory (DVM^tm ), memory tagging extensions (MTE^tm), memory partitioning and management (MPAM^tm), system-level caches, AMBA^® CHI Chip-to-Chip (C2C^tm), and many more to help designers understand performance issues and address them.

• How do we decide on the optimal mix and capacities of the various memory options available?
• What happens if the requested bandwidth exceeds the real-world maximum transfer limit?
• How are latency and bandwidth defined and measured?
• Can modeling be used to validate system performance?

Unveiling the Secrets of Optimal Performance: A Glimpse into the Performance Cookbook for Arm

The Performance Cookbook for Arm focuses on the concepts and methodologies essential for designing high-performance Arm-based SoCs. It delivers a comprehensive overview of performance optimization strategies and provides practical, hands-on knowledge using real working flows and advanced System VIP tools. The book also delves into how Cadence tools and solutions can assist in achieving optimal performance.

The Performance Cookbook for Arm highlights the significance of generating synthetic traffic workloads as a strategic approach for investigating system performance. Furthermore, it examines methodologies for conducting performance analysis throughout the different phases of system integration. This is done to ascertain the accurate configuration of IP components and achieve the performance benchmarks initially set for the product.

This book comprehensively explains Arm components' evolution, interfaces, and performance aspects. It also guides the reader through the system components, including DDR SDRAM. The content beautifully explains challenging concepts like system performance management and Arm system-level solutions with real-world examples that help analyze performance. Additionally, it covers memory bandwidth analysis through performance analysis tools and examines the performance bottleneck caused by the initial choice of memory architecture. It also discusses designers' rich options across the memory hierarchy to organize memory and optimize workload balancing.

Conclusion

The Performance Cookbook for Arm is more than just a technical manual; it's a testament to the evolution of Arm components and their interfaces and a deep dive into the performance aspects of these entities. The book equips engineers with the skills and knowledge to excel in performance evaluation and Arm-based SoC design. Cadence and Arm have worked together for over 20 years, and this book symbolizes their close collaboration. It's a must-have resource for anyone involved in Arm-based SoC design. The book can also be used as a companion to the rapid adoption kits (RAKs) available on the Cadence online support portal to gain practical hands-on knowledge using real working flows in conjunction with advanced System VIP tools.

The Performance Cookbook for Arm is now available for ordering.