Verification Using Near End Loopback

Near End Loopback (NELB) is a feature introduced by Intel's PHY Interface spec revision 6.1, and its general idea is to facilitate testing the PHY device for high-volume manufacturing. The loopback concept is transmitting something and receiving it back as an echo. This allows the IP to compare transmitted against received data. If there is any difference, it will be marked as an error.

The NELB happens on the pipe interface, so the data is not propagated to the serial part of the link, i.e., the PHY receives data from the MAC and, instead of forwarding it to the serial side, it will loop it back on the pipe interface itself. The main goal is to enable link training without having another partner device on the link.

Figure 1 illustrates the usual topology of devices in regular operation. In a simple PCIe link, there are two device types: an upstream device, a.k.a. Root Complex (RC), and a downstream device, a.k.a. End Point (EP). Figure 2 shows an example of the topology while in NELB. The device in NELB may be either RC or EP, and the corresponding pair is unnecessary.

The last point to highlight about NELB is that it is a testing technique that allows looping back data from different points inside the PHY. Considering this, it is possible to narrow down where there may be an error in the design, facilitating the fault identification and correction.

Entry and Exit Methods

To enable NELB mode, the PowerDown state must be such that both TX and RX are off, but PCLK is operational. 

Then, MAC releases reset and sends PipeMsgs with desired loopback Position and Enable bit set to write on PHY NELB Control register. Once PHY has done its internal setup and is ready, it also sends PipeMsgs to write on the NELB Status register on MAC, indicating the handshake is complete. Both devices are now ready to train in NELB mode. 

There are two possible ways to exit NELB. The first one is the PipeMsg handshake, similar to the entry one, except that the Enable bit is now cleared. However, not all PHYs support this, and they should indicate it on their datasheet. If exit handshake is not supported, once PHY receives PipeMsg to exit NELB, it should respond with another PipeMsg, setting the Error bit. Once MAC sees this message, it will start exiting using the second method, which is through reset - mandatory to be supported by all devices.

After successful exit (either by handshake or reset), both MAC and PHY are ready to train in regular operation.

Verification on NELB Mode

The NELB feature can be tested with active and passive VIP instances. Both are ready to exercise this feature on Device Under Test (DUT).

The active instance will make DUT perform NELB, while the passive instance will keep verifying it and comparing the transmitted against received data.

VIP has checkers to indicate if something goes wrong during this process, and, as mentioned at the beginning, using the NELB feature makes it easier to narrow down possible design failures. 

More Information

• For more info on how Cadence PCIe Verification IP enables users to confidently verify PCIe 6.1, see VIP for PCI Express
• See the PCI-SIG website for more details on PCIe in general and the different PCI standards