Featured

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus
Verification
Latest blogs

Welcome Sharath Siddappa From Rambus, You Are The 5000th OVM World Registrant!

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the…

• 1 min read
SystemVerilog , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , eRM , OVMWorld

OVM - The "O" Means Opportunity

A few months back I blogged that OVM was " Open for Business ". A nice play on words…

• 1 min read
Simantis , eclipse , KPIT , Functional Verification , IBM , Cadence VIP portfolio , OVM , Doulos

Report From the Advanced Verification Techtorial in San Jose Tuesday 10/28

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

The Power of Cadence System Power Flow vs. Viewing from the Top

I feel that I must respond to the following blog published by Frank Schirrmeister…

• 6 min read
Incyte Chip , System Design and Verification , Incisive Enterprise Simulator , Palladium , power engineer , C-to-Silicon , Power Analysis , Frank Schirrmeister

ESC Boston: Day 2

This morning before heading to ESC it dawned on me that the park across the street…

• 4 min read
System Design and Verification , ESC , ISX , Coverage Driven Verification

Virtualization Taxonomy

I arrived safe and sound at the Embedded Systems Conference in Boston today. It's…

• 2 min read
VM ware , virtualization , taxonomy , real-time systems , Embedded Systems Conference , System Design and Verification , ESC

OVM Momentum and Interoperability

The question of how to integrate legacy VMM VIP into OVM verification environments…

• 1 min read
OVM Professionals Network , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , VIP , Verification IP modeling

Verification Techtorial in San Jose next Tuesday 10/28

Apologies for the shameless promotion, but I can't resist touting an event I'm producing…

• less than a min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

Formal Moment Of Zen

Most of my experience in functional verification prior to my dabbling in FPV was…

• 3 min read
OVL , FPV , Functional Verification , Formal Analysis , SCV , SVA , FIFO , PSL , Simulation acceleration , SystemC

Is Host-Code Execution History?

Before getting into the details of today's topic I'm happy to report a brand new…

• 5 min read
Cisco , System Design and Verification , MIPS , Palladium , Sun , Verilog , OVP , ARM , Virtutech , QEMU

Top 5 Stumbling Blocks In FPV Adoption

My first post served as a context for this blog. It also telegraphed my intention…

• 5 min read
verification strategy , Verification methodology , Functional Verification , Formal Analysis , Model-checking , Testbench simulation , Coverage-Driven Verification

More on today's Verification IP portfolio expansion news

Today's announcement on our expanding Verification IP (VIP) portfolio inspired me…

• less than a min read
Functional Verification , Verification IP modeling , multi-language

Getting more value from the OVM using Metric-Driven Verification - Part II

In my last post , I talked about how OVM is a methodology for building automated…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , ARM , Incisive Enterprise Simulator (IES)

Early Embedded Systems Conference Coverage

Today, a friend sent me a link to an article on embedded.com that talks about my…

• less than a min read
System Design and Verification , Embedded Systems Boston Conference

Is there a 1 Billion gate chip on your roadmap?

Yes, I'm asking about chips that will have 1 billion -- that's billion with a "B…

• 1 min read
verification strategy , Verification methodology , Functional Verification , System Verification

System-level design and verification - at the center!

This year, Cadence increases its focus on system-level design and verification events…

• 1 min read
Acceleration , System Design and Verification , embedded software , Emulation , ESL handoff , System simulation and analysis , Coverage Driven Verification for Embedded Software , embedded SW engineer , CDNLive! Silicon Valley 2008 , ISX , Hardware/software co-verification , ESL , architect

Power Aware Design Now at System Level

Several years ago, I have purchased a cell phone with a 2 years contract from one…

• 2 min read
Acceleration , System Design and Verification , Low power verification and analysis , system validation/verification engineer , Verification Acceleration , System simulation and analysis , embedded SW engineer , Simulation acceleration , C-to-Silicon Compiler , Hardware/software co-verification , debugging , ESL , architect

An informal introduction

Formal verification can mean different things depending upon who you speak to. If…

• 1 min read
Formal Analysis , Model-checking

Report from last week's "ClubT" events; preview of next week

As promised, here are some photos last week events, with embedded color commentary…

• 1 min read
SystemVerilog , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , multi-language , coverage driven verification (CDV) , ISX , eRM , System Verification , OVM 2.0 , IES

Users Take Over at CDNLive! 2008

This year I did not attend CDNLive! in San Jose. I wasn't presenting anything and…

• 2 min read
HW/SW , CDNLive San Jose 2008 , Functional Verification' signal integrity , ISX (Incisive Software Extensions)

The cell world

Earlier this Summer, I was lucky enough to attend the CDNLive show in Japan. One…

• 5 min read
IBM , Playstation , Toshiba , cell processor , Sony

In the EU next week for "ClubT" verification events

I'll be in the EU next week supporting "ClubT" events focused on advanced verification…

• 1 min read
SystemVerilog , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , multi-language , coverage driven verification (CDV) , ISX , eRM , System Verification , OVM 2.0 , IES

Embedded Software Bugging and Debugging

In one of my previous posts I introduced an interesting book titled Dreaming in Code…

• 4 min read
bugging and debugging' , System Design and Verification , embedded software

Getting more value from the OVM using Metric-Driven Verification

With all of the momentum around the OVM these days there has been a lot of good discussion…

• 2 min read
SystemVerilog , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , coverage driven verification (CDV) , eRM

Verification community comes together to talk tech

I just finished the week at Cadence's CDNLive User Group in San Jose. Over the past…

• 1 min read
SystemVerilog , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Formal Analysis , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , ISX (Incisive Software Extensions) , Simulation acceleration , coverage driven verification (CDV) , ISX , eRM , System Verification

A few thoughts on CDNLive! and OVM 2.0

My colleague Joe Hupcey has been keeping you informed and entertained with information…

• 1 min read
CDNLive San Jose 2008 , OVM 2.0

OVM 2.0 -- Short Technical Review

By now you may have seen the official announcement of the OVM 2.0 release . So what…

• 3 min read
SystemVerilog , Verification methodology , OVM , CDV , System Verification , OVM 2.0

Day 3 of CDNLive San Jose

Highlights of Day 3: papers all morning, lunch, then closing remarks. Comments on…

• less than a min read
verification strategy , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , ISX
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