Shift Verification Left: AI Tools for Faster, Smarter Chip Design

23 Mar 2026 • 7 minute read

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished Engineer at Cadence; edited by Robbie O Sullivan.

In November 2025, ChipStack officially joined Cadence. This acquisition builds on years of collaboration, integrating ChipStack's agentic AI platform with Cadence's industry-leading verification technologies. Following the acquisition of ChipStack, Cadence has announced the launch of the ChipStack AI Super Agent, marking a significant advancement in semiconductor design and verification.

Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report).

The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-market.

Key Bottlenecks in Verification Workflows

Verification has always been a complex, multi-step process, but the most critical bottlenecks are as follows:

Debugging functional failures: Engineers are required to analyse waveforms, trace signal interactions, and review RTL code to determine the root causes of issues. This process typically consumes a significant portion of the overall project timeline.
Achieving comprehensive coverage: Hitting sign-off thresholds for functional and code coverage requires multiple test iterations, each demanding time-consuming simulation or formal analysis.

These two tasks necessitate a constant back-and-forth between the design and DV teams: designers rewrite code, DV reruns tests, someone finds a new failure, and the cycle repeats. Every turn of that loop costs time and patience.

Shifting Verification Left with AI

Time is money in chip development, especially when it comes to verification. A key strategy for accelerating schedules is enabling designers to handle more verification tasks themselves, thereby reducing handoffs and compressing the overall verification cycle. When designers can verify their own blocks, they can:

Catch bugs immediately: Issues are identified while the design intent is still fresh in mind
Make faster iterations: No waiting for verification team bandwidth to test small changes
Deliver higher-quality RTL: Blocks arrive at the verification team with many basic issues already resolved

If designers can thoroughly verify individual blocks before subsystem integration, the verification team can focus on complex system-level interactions. Shift left is not a new methodology in chip design, by any means; however, this approach was traditionally limited by the steep learning curve of verification tools and methodologies. Now, AI assistants can bridge this gap by translating design intent into effective verification assets without requiring designers to become verification experts.

Emerging AI platforms, especially those powered by large language models (LLMs), are closing the skills gap by:

Translating early design notes into formal, complete specifications
Auto-generating SystemVerilog or formal testbenches that reach 70 – 80% code coverage on first run
Executing simulation or proof runs autonomously and generating diagnostic reports
Synthesizing assertions and covergroups from plain-language intent, no SVA expertise required

Diagram to represent the verification flow

These tasks now occur in minutes, dramatically compressing the verification cycle. Designers can take on more verification tasks "up front" without deep verification knowledge.

In the sections below, we'll explore the key areas where AI is empowering designers to make significant contributions to the verification effort.

High-Fidelity Specifications

Effective verification begins with a clear articulation of design intent, what we call the mental model. LLM-based assistants can expand concise design outlines into the standard structured specifications that define functional behavior, interface protocols, and boundary conditions. A comprehensive specification minimizes ambiguities and provides a definitive reference for later verification activities. This structured, version-controlled document supports every team in the ASIC lifecycle, streamlining onboarding for new engineers and promoting cross-functional alignment.

Traditionally, writing a detailed spec is a laborious task, but AI is changing that. By automating the generation of specification documents, teams can adopt a spec-first (or spec-parallel) methodology without slowing down development. In fact, specification automation is emerging as a powerful "shift left" technique in its own right: auto-generating design and verification collateral from an executable spec ensures consistency and cuts down manual coding errors, which in turn reduces downstream debug and iteration. In short, investing a bit more in the spec up front, now feasible with AI assistance, pays dividends in reduced debugging and patching later.

Rapid Unit-Level Verification

RTL block-level verification, the hardware equivalent of unit testing, can catch the majority of bugs early, often achieving over 80% coverage before integration. Organizations that embrace this philosophy have seen faster overall verification cycles and fewer late-stage surprises. Historically, designers have avoided this step due to the manual labor required to:

Write SystemVerilog testbenches
Create stimuli and assertions
Set up simulation environments
Debug failures

Now, AI-driven verification tools eliminate this manual effort. Auto-generated unit tests are becoming a reality. Designers can input a spec or RTL and, in the time it takes to refill their cup of coffee, receive a complete test environment—built, executed, and analyzed automatically. A FIFO that once took days to verify can reach high coverage in under 10 minutes.

AI-driven verification has two profound effects:

Designers become more inclined to verify their blocks thoroughly, since the effort barrier is low
The central verification team's load is reduced because many simple bugs never make it out of the block stage

Assertion Generation at Scale

Assertions embedded in RTL provide numerous benefits. They help identify bugs early and offer immediate, localised feedback, which speeds up debugging. Designers specify the rules their logic must follow so formal or simulation tools can prove or disprove those rules at the block level, well before full-chip simulation.

Off-the-shelf assertion libraries and protocol-specific ABVIPs further reduce manual engineering effort, enabling complete interface verification in hours rather than weeks. The result is shorter schedules, fewer late-stage surprises, and a smoother hand-off to verification teams, who can then focus exclusively on system-level issues. While protocol-specific libraries help, the biggest barrier has been the steep learning curve of writing assertions in SystemVerilog Assertions (SVA). Many designers either don't know SVA well or simply don't have time to write a lot of properties.

AI assistants now make it easy to generate correct SVA properties from high-level intent, enabling more designers to include assertions as a first-class part of their design process.

Designer-Guided Functional Coverage

Functional coverage is the mechanism by which verification teams measure what scenarios have been exercised by tests. While code coverage tells us which lines of RTL code ran, functional coverage tracks whether specific behaviours or sequences have occurred.

Designers often skip writing functional coverage due to a lack of familiarity with covergroup syntax or the difficulty of identifying interesting scenarios. Yet, they're the ones who understand the design's edge cases best and have unique insight into critical operating scenarios. AI tools can bridge this gap by converting a designer's natural-language insights into SystemVerilog covergroups, ensuring early visibility into what's been tested and what hasn't.

Toward an AI-Augmented Verification Flow

Recognising these advantages, the semiconductor industry is progressing towards more integrated, AI-enhanced verification platforms. The goal is a unified environment where specification, test generation, simulation, formal analysis, and debugging are all interconnected and supported by AI. Such a platform would automate routine tasks and provide intelligent guidance on complex tasks, such as pinpointing the root cause of a failure or recommending the next most productive test to run. The move towards AI-augmented verification aligns with a wider industry trend towards connected, data-driven verification workflows. Rather than viewing simulation, formal methods, emulation, and other approaches as separate silos, future verification platforms will employ AI to share information across these processes and optimise the overall workflow.

For chip development organizations, this integrated approach empowers engineers to spend less time on building and maintaining test infrastructure and more time on creative problem-solving and design optimization. The AI handles the grunt work, while engineers handle the edge cases, design improvements, and truly tricky bugs. By bringing design and verification closer together, the traditional wall between the two starts to erode, and we get closer to the ideal of design with verification: designing and verifying become concurrent activities of equal importance.

The Future of Verification Is AI

As semiconductor designs grow ever more complex, traditional verification methods simply can't keep pace. AI-driven, design-for-verification workflows empower designers and verification engineers to work in parallel, accelerating time-to-market and improving product quality.

Even if not every project achieves a 20X speedup, the direction is clear. By shifting verification left and automating much of the work, organizations gain efficiency, predictability, and a competitive edge. Organizations that incorporate AI into their verification methodology stand to achieve significant gains in efficiency, predictability, and competitive advantage.

Designers catch bugs early. Verification teams receive higher-quality RTL. Everyone wins. The message is clear: the future of verification is earlier, smarter, and deeply intertwined with AI-driven automation. Those who embrace it will undoubtedly race ahead, while those clinging to old methods risk being left behind.

About Hamid Shojaei

Hamid Shojaei is a Distinguished Engineer at Cadence and the former CTO and Co‑Founder of ChipStack, which was acquired by Cadence, where he sets the technical vision and leads development of the company's LLM-powered verification platform. Hamid heads a seasoned team of engineers, turning breakthrough research into practical tools that redefine how semiconductors are designed and verified. Drawing on over 15 years' experience at Qualcomm, Google, and photonics start-up Lightmatter, he has steered teams through multiple generations of TPU and AI-centric chip projects, earning an ACM Best Paper Award along the way. Hamid holds a PhD in Computer Engineering from the University of Wisconsin, Madison, and is recognized for bridging design verification, machine learning, and cutting-edge hardware architecture.