Users Take Over at CDNLive! 2008

This year I did not attend CDNLive! in San Jose. I wasn't presenting anything and was quite busy with other things. The good news was that there were three ISX (Incisive Software Extensions) users making the presentations so I could stay home and keep working on the new stuff for the upcoming 8.2 release.

Two years ago at CDNLive! 2006, I presented ISX for the first time to the Cadence Verification Community. The paper and presentation outlined the use of ISX on an example platform developed by ARM, the ARM926 PrimeXsys platform. In the presentation I outlined how ISX could be used to improve verification by augmenting two of the existing verification techniques used on the platform.

The first was the use of an eVC in place of the processor and the use of constrained random generation on the 2 AHB interfaces of the ARM926. The second was the use of C diagnostics to test hardware behavior with the CPU instantiated. I showed how ISX could leverage the existing C diagnostics by attaching constrained random stimulus to the diagnostic programs to generate new and interesting activity compared to the directed C programs.

At the time a lot of verification engineers were interested and asked good questions after the talk, but in September 2006, ISX was actually not even a released product. Although it had some customer usage with early partners, it was not available for general download by Cadence customers. The first production release actually came with Specman 6.0 in December 2006.

Fast forward two years to CDNLive! 2008. This year there were three papers on the program given by ISX users that talked about using ISX on real projects and real chips, not just example designs like I was forced to talk about. I would like to highlight just one of the three today and hopefully I can cover the others in the near future. The paper I will highlight is about an HDTV chip titled:

An HDTV SoC Development Team’s First Experience with HW/SW Co-Verification

The first thing I noticed about this paper is the use of the words "First Experience" in the title. Many people think co-verification has been around in various forms for at least 10-15 years and probably all the good ideas have already been implemented and there is not much new activity happening in co-verification. The reality is that there are still many new opportunities for co-verification in projects that have not really concentrated on it for one reason or another.

 This paper outlines a set of goals the project team looked at when devising a verification strategy for the HDTV chip:

• Exercise the full-chip HW & SW together in a simulation
• Re-use testbenches from HW verification
• Achieve reasonable performance, e.g. X minutes for typical scenarios of interest
• Provide several capabilities to debug HW/SW interactions