Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor…

• 2 min read
Verification IP , Design IP , JEDEC , LPDDR PHY IP , DRAM , lpddr5 , LPDDR Controller IP , memory models , Lpddr6

Training Webinar on Protium X3: Using FullVision for Debugging

Join me, Sandeep Nasa, Senior Principal Education Application Engineer, in our free…

• 1 min read

The Evolution of CXL.CacheMem IDE: Insights into CXL3.0 Security Feature

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read
CXL3.0 , VIP , PCIe , verification

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium , Palladium , xcelium , VDE , helium , System Verification

Insights from the Verification Software Track at CadenceLIVE Silicon Valley 2025

Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025…

• 2 min read
Verification IP , SVG , software , cadencelive , SimAI , xcelium , verification

UALink: Powering the Future of AI Compute

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification…

• 2 min read
Verification IP , VIP , Ethernet , PCIe , HPC , UALink , AI/ML

eMMC: The Embedded Storage Powering On-Device AI

In today's world of increasingly intelligent devices, efficient and reliable storage…

• 2 min read
Verification IP , VIP , verification

Using PSS Registers with Perspec for Portable Programming Sequences

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus…

• 6 min read
Perspec , perspec system verifier , pss

NOP Flit Payload: A Dedicated Debug Channel

Modern PCIe systems are complex, with high-speed data transfer and intricate protocols…

• 3 min read
NOP Flit Payload , debug , PCIe , PCIe 6.0 , PCI Express , Debug Chunk , NOP.Debug Flit Payload

Unlocking Efficient Debugging with the Verisium WaveMiner App

Overview of the Verisium WaveMiner App Verisium WaveMiner is part of the Verisium…

• 2 min read

Training Insights – Tcl Scripting Course for Beginner and Advanced Users

Tcl is a versatile scripting language used in automation, testing, networking, and…

• 1 min read
EDA tools , scripting , tcl

USB4 Port Operations

Designs are tested in the labs for various electrical compliance tests defined in…

• 3 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

• 3 min read
featured , Perspec , pss , portable stimulus

Cadence's 2024 Training Programs and Resources

As we welcome 2025, let’s take a moment to reflect on the most viewed blogs and videos…

• 4 min read
onboarding , Functional Verification , RTL , System Design and Verification , Protium , training_byes , SVG , verisium , RAK , blended_training , webinar , digital_badge , ucle , live , ask , xcelium , accelerated , verification

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB , eUSB , eUSB2

AMBA LTI Verification IP for Arm System MMU

The AMBA LTI (Local Translation Interface) defines the point-to-point protocol between…

• 2 min read
amba5 , Verification IP , featured , Address translation , LTI , SMMU , AMBA , DTI , ARM

Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems

As technology continues to advance, so do the ways we connect and manage memory and…

• 3 min read
Verification IP , Memory , CXL3.0 , System Design and Verification , VIP , PCIe , AI/ML , data centers , cloud computing

Various Types of Transaction-Based Interfaces (TLM) for DisplayPort VIP

Introduction Different RTL designs often require different specially designed parallel…

• 3 min read
Verification IP , uvm , VIP , DisplayPort , verification

Unraveling Orthogonal Header Content (OHC) in PCIe 6.0

Introduction With the arrival of Flit Mode, the information hold by the TLP header…

• 3 min read
System Design and Verification , VIP , PCIe , verification

Introduction of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard

Universal Serial Bus (USB) technology is the most popular connector in every computing…

• 3 min read
eUSB2v2 , Functional Verification , VIP , USB , eUSB2

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main…

• 4 min read
Verification IP , audio , VIP , DisplayPort

Cadence PCIe 7.0 Solution at PCI-SIG Developers Conference India 2024

Cadence is well-known for supporting PCIe technology and providing a robust ecosystem…

• 3 min read
VIP , PCIExpress , PCIe 7.0 , PCIe , PCIe 6.0 , PCI Express , PCI-SIG

USB4 Sideband Channel Is Not a Side Business

The USB4 specification has been around for several years now. Two years ago, USB4…

• 4 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Randomization Considerations for PCIe Integrity and Data Encryption Verification…

Peripheral Component Interconnect Express (PCIe) is a high-speed interface standard…

• 7 min read
Verification IP , Functional Verification , System Design and Verification , VIP , PCIe , PCIe 6.0 , PCIe Gen5 , IDE

Versatile Use Case for DDR5 DIMM Discrete Component Memory Models

DDR5 DIMM Architectures The DDR5 generation of Double Data Rate DRAM memories has…

• 6 min read
ddr5 , Functional Verification , DDR5 DIMM , System Design and Verification , VIP , MRDIMM , Memory Model

Training Webinar: Fast Track RTL Debug with the Verisium Debug Python App Store

As a verification engineer, you’re surely looking for ways to automate the debugging…

• 2 min read
Functional Verification , Python API , Verisium Debug

Training Webinar: Protium X2: Using Save/Restart for Debugging

Cadence Protium prototyping platforms rapidly bring up an SoC or system prototype…

• 2 min read
protium x2 , save and restore

Deferrable Memory Write Usage and Verification Challenges

The application of real-time data processing or responsiveness is crucial, such as…

• 6 min read
CXL , PCIe , PCIe Gen5 , Deferrable memory write transaction
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