Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor market today. It's used in a diverse set of applications that span mobile/handheld devices, IoT, client and server, automotive, virtual reality/gaming consoles, robotics, data centers, and AI applications, just to name a few.

For over 50 years, JEDEC has been the global leader in developing open standards for the microelectronics industry, and the JEDEC membership includes industry-leading semiconductor companies. JEDEC has just released the LPDDR6 specification, which is expected to take the LPDDR DRAM market to new heights with data transfer speeds that can reach 14.4Gbps—a 50% improvement over LPDDR5X speeds. LPDDR6 device density can range from 4Gb to 64Gb.

Other important features of LPDDR6 devices include:

• 2 subchannels per device
• Metadata built into the data packets
• Per-row activation count (PRAC)
• Low-power optimizations
• System meta mode
• Static and dynamic efficiency modes for increased density with the same ball maps or saving I/O power
• Error detection, correction, and scrub
• Fault diagnostics and notification

On July 9 and 10, 2025, Cadence San Jose hosted the JEDEC LPDDR Task Group face-to-face meeting, which coincided with the release of the first official LPDDR6 specification. This is the fourth year in a row that Cadence has hosted the JEDEC LPDDR Task Group. The meeting was well attended, with approximately 50 members from 20+ member companies joining in person and remotely. Participants included members from leading semiconductor and systems companies from around the world.

"The JEDEC LPDDR Task Group face-to-face meeting is a significant step in defining the future Low-Power DRAM industry standards like LPDDR6 for next-generation applications," said Osamu Nagashima of Advantest and Chair of the JEDEC LPDDR Committee and Task Group. "Cadence, being a valued task group member, has graciously hosted this meeting very frequently for the last four years and organized the celebration of the long-awaited LPDDR6 standard release."

The task group meeting coincided with Cadence announcing its 14.4G LPDDR6/5X memory IP—the first and highest-performance LPDDR6 IP available. 

Cadence Memory IP system solutions offer world-class LPDDR, DDR, GDDR, and HBM PHY and Controller IP that are flexible and configurable to support a wide range of applications.

Cadence Verification IP offers a comprehensive Memory Subsystem solution that includes a memory model and DFI VIP for the just-released LPDDR6 standard. The LPDDR6 memory model comes with comprehensive functional coverage, assertion coverage, and a verification plan.

Learn more about Cadence Simulation VIP for LPDDR6, or contact us with questions at talk_to_vip_expert@cadence.com.