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AMBA Distributed Translation Interface (DTI) for Arm System MMU

In ARM MMU-based systems, DTI protocol defines a standard way to communicate with…

Yeshavanth BN 21 Apr 2022 • 1 min read

AMBA-DTI , AMBA VIP , AMBA Verification IP

Device Training for High Speed DRAMs

As the device frequencies and the data rates go up with every new generation of…

Shyam Sharma 12 Apr 2022 • 3 min read

Verification IP , ddr5 , VIP , JEDEC , Training Modes , lpddr5 , lpddr5x , memory models , DDR5DIMM

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

Vinod Khera 4 Apr 2022 • 6 min read

How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various…

ssalehab 29 Mar 2022 • 2 min read

Verification IP , Industry Insights , Functional Verification , DFI 5.1 , VIP , SoC , DFI , storage , DFI Technical Group , memory models , DDR-PHY , DDR-PHY Interface

Who Inspires You? - An SVG Women's History Month Spotlight

This month, we join millions celebrating and recognizing the achievements of women…

Melisa 25 Mar 2022 • 5 min read

Addressing Hyperscalers' Requirements with Ethernet 800G

Cloud computing, IoT (Internet of Things), machine learning, big data, and data…

Krunalkumar 17 Mar 2022 • 1 min read

Ethernet 800G , Verification IP , Ethernet VIP , Functional Verification , Hyperscalers , data centers , Ethernet 400G , cloud computing

Training Insights - Embracing Datapath Verification with Jasper C2RTL App

Current verification techniques cannot keep pace with the growing arithmetic nature…

Nizar Hanna 8 Mar 2022 • 2 min read

online , c2rtl , training , app , JasperGold , verification

MIPI UniPro 2.0 for Higher Data Rate Transmissions

MIPI specifications are widely used across the Mobile and IoT industries, mainly…

Yeshavanth BN 6 Mar 2022 • 1 min read

UniPro , HS-LSS , VIP , MIPI

Mind reading? Almost. Specman New Typo Error Prediction Feature

Presenting Specman syntax error messages enhancement - provide suggestions to fix…

teamspecman 4 Mar 2022 • 1 min read

Specman , e

Boost your CXL Verification From IP to System-Level

Knowingly or unknowingly, we are consuming huge volumes of data from getting up…

Vinod Khera 24 Feb 2022 • 6 min read

CXL , HIgh Speed Interconnect , PCIe , Compute Express Link

Employee Spotlight – Highlighting Our Colleagues in SVG!

Cadence’s SVG team would like to feature two team members who are making a difference…

Melisa 22 Feb 2022 • 5 min read

SoCs Verification Management, Traceability and Managing Risks in Semiconductor W…

With the increased complexity in SoC design and bigger teams, manually updating the…

Vinod Khera 21 Feb 2022 • 4 min read

Verification planning and management , collaboration , vPlan , IBM , verification management , JIRA , Traceability , OpsHub , IBM DOORS NG , semiconductors , vManager

Optimizing CPU Time, TAT, and Disk Space using Cadence Xcelium Advanced Technologies…

Design for Testability (DFT) simulation is crucial to the SOC design process: rapid…

Vinod Khera 8 Feb 2022 • 8 min read

System Design and Verification , PPA , Disk Space optimization , xcelium , HREF

Re-Timer – The Key for High-Speed Signal Transmission in USB4 Systems

The objective of USB4 protocol to achieve high speed signal transmission and thereby…

Neelabh 3 Feb 2022 • 1 min read

Re-timer , USB4 VIP , VIP , usb4 , usb4 router

5G Network Revolution for Enhanced User Experience and Industry Digitalization

The emerging 5G network is the 5th generation of the cellular network. A 5G network…

Krunalkumar 10 Dec 2021 • 1 min read

eCPRI , Verification IP , Enhanced Common Public Radio Interface , 5G Network , Ethernet VIP , Functional Verification , Ethernet standards , Synchronous Ethernet , Funcional Verification , sync

From AMBA ACE to CHI, Why Move for Coherency?

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from existing AXI protocol…

MinL 6 Dec 2021 • 2 min read

Verification IP , ACE VIP , Functional Verification , VIP , coherency , CHI VIP

Why is Ethernet Time-sensitive Networking (TSN) Adaptation So Rapid in the Automotive…

At a particular point in time, the automotive industry continued to add more and…

Krunalkumar 28 Oct 2021 • 1 min read

Automotive , Verification IP , SoC verification , IP verification , Ethernet VIP , Functional Verification , VIP , Ethernet standards , Automotive Ethernet , TSN

Single DRAM or Multi-DRAMs Memory Sub-system for Your Next SOC ?

Even with the DRAM capacity going up with each generation of DRAM, the demand…

Shyam Sharma 10 Oct 2021 • 2 min read

Verification IP , ddr5 , Memory , DDR5 DIMM , JEDEC , lpddr5 , MMAV

Verification of Integrity and Data Encryption(IDE) for PCIe Devices

The concept of Trusted Execution Environments (TEE) was developed in the early 2000s…

Sangeeta Soni 22 Sep 2021 • 4 min read

security , funtional verification , pcie 5 , PCIExpress , encryption , PCIe , pcie gen6 , IDE

Training Insights - Addressing Security Verification Requirements with JasperGold…

As a chip designer, you’re probably spending as much headspace on security threats…

Nizar Hanna 21 Sep 2021 • 2 min read

online , CDC , training , app , JasperGold , verification

Comprehensive Approach to Verification of Interconnect-Centric Systems

Many of today’s SoCs are built around multi-layered, sophisticated interconnect…

DimitryP 20 Jul 2021 • 2 min read

interconnect , scoreboard , SoC verification , Functional Verification

Why IDE Security Technology for PCIe and CXL?

The new cloud, AI, Analytics, and Edge usage models with exponential data growth…

Claire Ying 19 Jul 2021 • 3 min read

Verification IP , Functional Verification , VIP , System Verification , simulation , verification

PIPE SerDes Architecture for PCIe Gen 5 and Beyond

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification…

Sangeeta Soni 21 Jun 2021 • 2 min read

Intel , IP verification , PHY , pcie 5 , VIP , PCIe , SerDes , pcie gen6

Training Insights — Metastability-Aware Verification: Elevate Your Signoff with JasperGold…

I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during…

Nizar Hanna 13 Jun 2021 • 2 min read

CDC , RTL designer Signoff , Metastability , JasperGold , verification

Webinar: Using e Reflection

Join Cadence Training and Software Architect Efrat Shneydor for this free technical…

teamspecman 6 Jun 2021 • 1 min read

Specman , Specman e , training , webinar , reflection

AMBA 5 ACE/AXI Specification Updates and Their Support in Cadence ACE/AXI VIP

As discussed in the previous blog, the AMBA® 5 specification updates introduced…

DimitryP 1 Jun 2021 • 3 min read

amba5 , ACE5 , AXI5 , Funcional Verification , AMBA Verification IP , System Verification Scoreboard

How to Verify LPDDR5 from IP to System Level?

LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs…

Thierry Berdah 18 May 2021 • 3 min read

Verification IP , SoC verification , Specman , Memory , Functional Verification , VIP , JEDEC , Memory Model Portfolio , storage , lpddr5 , lpddr5x

Introduction to Macros – Answers to Your Questions

Thanks to all the people who attended the webinar Extend the Language! An Introduction…

teamspecman 12 May 2021 • 5 min read

Specman , Functional Verification , e , webinar , training bytes , macro debugging , e language , macros

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