Fast Emulation Requires Fast Debug! This Is How It is Done

Introduction

Emulation has become a critical tool for verifying complex system-on-chip (SoC) designs in semiconductor design. However, debugging in an emulation environment presents unique challenges that can significantly impact the verification process's efficiency and effectiveness. This article explores these challenges and discusses how fast waveform generation and unified compilation can enhance debugging.

Challenges of Emulation Debug

When it comes to emulation, what the user wants to achieve involves complex scenarios and long test cases to ensure the design functions properly under such circumstances. Here are some examples that the user might be running into:

1. Length of tests and failure reproduction: Emulation tests often involve extensive sequences, including resetting the SoC design, booting an operating system, and running various applications. These tests can span billions of clock cycles, making it difficult to pinpoint the root cause of failures. For instance, a bug might manifest only after a billion cycles, complicating debugging.
2. Non-deterministic behavior: Emulation environments can exhibit non-deterministic behavior due to the concurrent execution of the design and testbench. This nondeterminism can make it challenging to reproduce failures consistently, hindering the ability to identify and fix bugs. Sometimes it takes more iterations of emulation runs to find the problem.
3. Data volume and analysis: The sheer size of modern SoCs means the volume of data generated during emulation is enormous. Extracting and analyzing this data to find the root cause of a failure can be daunting, often requiring significant manual effort. Handling such a massive amount of data is also a major problem in the process.
4. Mismatch between emulation and debug solution: Designs require compilations into databases for different purposes. The user compiles his design to run emulation and another compilation for debugging. Because the design has reached a certain complexity level when running emulation, the mismatch between emulation and debugging can cause significant challenges in identifying where the bugs come from, especially when compilers come from different tools.

What Is Needed for Better Debugging Efficiency?

It needs two required data types for the user to start debugging the results from emulation.

1. Waveform: Emulation runs the design behavior to help the design engineer understand if the design works as the SPEC defines. Waveform represents the activities from the design. Generating waveform efficiently help engineer to get to know the correctness of the design quickly.
2. Design data: Design compiled into emulation for emulation run, but the engineer also needs a method to visualize the design to help with debugging. The design hierarchy has to be exactly the same between debug and emulation.

The Solution

Verisium Debug natively integrates with Palladium and provides Full Vision 3.0 (FV3.0) technology for generating Cadence’s unified waveform database, Verisium Waveform DB (VWDB), and uses the same compiler as Palladium's IXCOM to generate a design DB for debugging to guarantee the efficiency and correctness of Palladium results.

How Fast Waveform Generation Helps

Fast waveform generation is a crucial tool in addressing some of these challenges. By quickly generating and replaying waveforms, engineers can more efficiently trace the sequence of events leading to a failure. How to generate a waveform efficiently is definitely a help to engineers when debugging.

Verisium Debug and Palladium’s Full Vision 3.0 (FV3.0) technology helps to reduce waveform generation time and provides a very compact file size for waveform database (VWDB). The following are some testing results from real designs:

The FV3.0 technology leverages a multi-core environment that enables fvCompute to convert waveforms at a very high performance. Overall, we are seeing 2X waveform generation performance, 10X reading performance, and 5X smaller size compared to other data formats.

The Role of Unified Compile

Verisium Debug and Palladium’s unified compile refers to the integration of emulation and debug environments into a single, cohesive flow.

This approach ensures consistency between the emulation and debug phases, eliminating the need for separate compilation steps. By maintaining a unified environment, engineers can seamlessly transition between emulation and debugging, improving overall productivity and reducing the time spent on recompilation. Using the same IXCOM compile between Palladium and Verisium Debug saves users’ efforts to prepare separate compile scripts and guarantees the same results between the two platforms.

The new database for debugging, Sage, is a newly designed debug database that can fulfill the requirements for emulation debugging. Sage is a very scalable database, for larger designs running on emulation, it also ensures the capacity for emulation debugging.

Conclusion

Emulation debug is challenging, from managing extensive test sequences to handling vast amounts of data. However, advancements in fast waveform generation and unified compile are making significant strides in addressing these issues. By leveraging these technologies, engineers can enhance their debugging processes, leading to more efficient and effective verification of complex SoC designs.