Cadence Blogs

Whiteboard Wednesday - Introduction to ADAS with a Real-Life Example

By Corrie Callenbach | 19 Jun 2018

In this week’s Whiteboard Wednesday, Marc Greenberg, walks us through a typical ADAS system architecture and then provides a real-life testimonial on the value of these systems. https://youtu.be/EQL4jeD25_g

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Whiteboard Wednesdays | self-driving car | ISO 26262 | ADAS
How Do You Pick Your IP?

By Meera Collier | 19 Jun 2018

Last week I talked about what IP is, and why it’s important. ( Click here for a quick review!) This week, after being inspired by a Whiteboard Wednesday given by Tom Hackett, I thought I’d talk about what really matters when selecting IP f...

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IP | Cadence on the Beat
RSA Wrapup: Song, Darling, Thrun

By Paul McLellan | 19 Jun 2018

The closing session of the RSA conference was a sort of chat-show hosted by Hugh Thompson, who is the RSA Program Chair. He brought up three people, two of who have featured in Breakfast Bytes posts before. The proceedings started with a session wher...

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sebastian thrun | security | artificial intelligence | rsa conference | rsa | kate darling | dawn song
Virtuoso Video Diary: What's this Net Connected to?

By sarahfino | 19 Jun 2018

Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where you can identify connections that exist for a net, filter on these connections and save the probe path information to a CSV file.

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Virtuoso Schematic Editor | Virtuoso | Schematic Editor | Virtuoso Video Diary | Circuit Design | Probes assistant | Custom IC Design | Schematic
Why Millennial Engineers Should Work for Cadence

By Paul McLellan | 18 Jun 2018

Many years ago, when Nokia was at the top of its game—one in every three phones shipped was a Nokia—I chatted to the sister of a friend of mine who was something senior in Nokia finance. I think she was the controller for a good part of t...

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andy kessler | EDA
Academic Track at CDNLive EMEA 2018

By Anton Klotz | 17 Jun 2018

From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days. For Academic Network in EMEA this is the most important event through the year, as we are organizing the Academic Track and invite our academic partners to attend, p...

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hololens | MEMS Design Contest | Reutlingen University | CDNLive EMEA | Risc V | Academic Network | UC Berkeley
Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

By XTeam | 15 Jun 2018

Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud. For a while now, there’s been a growing interest in cloud-based EDA solutions, but the time wasn’t ripe for...

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cloud-based verification | Functional Verification | cloud computing
The Design Infrastructure Alley

By Paul McLellan | 15 Jun 2018

One of the new things at DAC this year is the Design Infrastructure Alley. The Alley is an initiative from the ESD Alliance and the Association for High-Performance Computing Professionals to highlight the information technology infrastructure,...

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dac55 | DAC | infrastructure alley
Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

By Paul McLellan | 14 Jun 2018

In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet fruit pie, like something Marie Callendar would make, but it is full of minced lamb. And chips are what Americans call fries (except in the phrase "fish & ...

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DAC | ChipEstimate.com | Perspec | pss
What Is COM /JCOM Channel Compliance All About?

By Team Sigrity | 13 Jun 2018

In today’s world of double-digit gigabit-per-second data rates it is imperative that engineers properly design and characterize their system to meet standards compliance. This sounds simple enough but actually simulating a high-speed ser...

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SI | JCOM | Channel Operating Margin (COM) | COM/JCOM | JCOM channel compliance | COM | Channel Operating Margin | signal integrity | SystemSI
30 Years of Innovation - And There’s Still So Much to Do!

By PaulaJones | 13 Jun 2018

Last week I captured the highlights of the progress we’ve made in the past 30 years in the blog post, 30 Years of Innovation – We’ve come so far. And while I’ve witnessed a lot of these changes over the years, I feel lik...

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30 years | SDE | Tensilica | system design enablement | verification
"I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"

By Paul McLellan | 13 Jun 2018

Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine being too poor to afford servants, nor so rich as to be able to afford a car. Like most of us, I've been the other way around. I've owned a car sin...

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exponential | moore's law | baumol's cost disease
Whiteboard Wednesdays - What Really Matters When Selecting IP

By Corrie Callenbach | 12 Jun 2018

In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of the iceberg of requirements to consider when selecting IP for your next chip design. https://youtu.be/2S6V5RpXECM

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Whiteboard Wednesdays | IP | SoC Integration
Cadence Puts the IP in ...well, IP

By Meera Collier | 12 Jun 2018

A lot has been written about AI and machinelearningdeeplearning, but a friend asked me, what does that have to do with Cadence, anyway? And what do you mean when you say, IP? I realized that I haven’t explained it yet. So here goes! Tensilica F...

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IP | complexity | VIP | Cadence on the Beat | autonomous cars | interface IP | Tensilica | AI
High-Level Synthesis: The Secret Is Out

By Dave Pursley | 12 Jun 2018

Gone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out , and now the HLS community is talking and sharing experiences...

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High-Level Synthesis | CDNLive | Stratus | HLS
Imec on EUV. Are We There Yet?

By Paul McLellan | 12 Jun 2018

I already gave an introduction to my first visit to imec in my life in my post If It's Tuesday This Must Be Belgium. My First Visit to imec One of the things I mentioned there is that they have an EUV stepper in their fab, and they work clos...

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imec | stochastics | EUV
What's For Breakfast? Video Preview June 18th to 22nd 2018

By Paul McLellan | 12 Jun 2018

https://youtu.be/puYFl7m50tM Coming from Dilijian Armenia (camera Gary Bengier) Monday: Why Millennial Engineers Should Work for Cadence Tuesday: Wrapup from the RSA Security Conference Wednesday: Dolby DAP Light Thursday: Automotiv Elektronik .....

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rsa conference | rsa | Dolby | millennial | virtual cad | Tensilica | ludwigsburg | dap light
DMS 2.0 - What's Cool and What's New

By XTeam | 11 Jun 2018

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and wonderful features to help you use Xcelium to verify your...

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digital mixed signal | Functional Verification | DMS 2.0 | xcelium simulator
FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey

By Paul McLellan | 11 Jun 2018

Recently, the SOI Consortium held its annual Silicon Valley Symposium. I was only able to attend in the afternoon since I spend the morning at the ESD Alliance workshop on digital marketing (for more on that, see my post Digital Marketing—With ...

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FinFET | FD-SOI
Virtuosity: Let's Have Fun with ADE Debugging – Part 1

By Kabir | 11 Jun 2018

Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues...

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performance | ADE Explorer | ADE L | Virtuoso | ADE-XL | Virtuosity | Simulators | Custom IC Design | ICRP | ADE Assembler
Why Did EDA Have a Hardware Business Model?

By Paul McLellan | 8 Jun 2018

Business models are really important. Just ask any internet startup company that has lots of users and is trying to work out how to monetize them. It is a lot easier to get people to use something for free, much harder to get people to pay for s...

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term license | hardware | EDA | cadence cloud
Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available

By Virtuoso Release Team | 8 Jun 2018

The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download. To find out more, click here…

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IC | ISR20 | ICADV12.3 | ADE | Layout | Virtuoso | Virtuosity | IC6.1.7 | Custom IC Design | Custom IC
Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

By XTeam | 7 Jun 2018

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April 2018. One of the fields Microsemi operates in is the...

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SystemVerilog | uvm | Dynamic Test Load | Functional Verification | xcelium
Imec Roadmap

By Paul McLellan | 7 Jun 2018

I recently visited imec. For an overview of my day, see my earlier post If It's Tuesday This Must Be Belgium. My First Visit to imec . One of the things that imec does is to take the funnel of potential process developments and get some ...

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nanosheet | stco | 3nm | imec | gaa | FinFET | DTCO
Indian Airports Go High Tech

By Madhavi Rao | 6 Jun 2018

No more printed tickets. Shorter queues at check-in counters. Humanoid robots walking amidst you, giving you directions and guidance. Get ready for all this and more in just a few months from now. India is undergoing a technological revolution on ma...

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Kempegowda International Airport | aadhaar | Airports Authority of India | KIAL | KEMPA | Priyank Kharge