Cadence Blogs

Virtuosity: In the Line of Veri-Fire - Episode 4

By Team ADE Verifier | 13 Aug 2020

Want to know what's new in this episode of Veri-Fire? Check it out!

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Computational Logistics

By Paul McLellan | 13 Aug 2020

General Omar Bradley famously said: “Amateurs talk strategy. Professionals talk logistics.” And Napoleon (perhaps) said "An army marches on its stomach". That's not to underestimate other aspects of armies, such as...

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computational logistics | computational software | verification
Custom IC, Analog, and RF Design Training Deep Dive: Part 3

By Kira Jones | 12 Aug 2020

Welcome to part 3 of the Custom IC, Analog, and RF Design Online Training deep dive blog series. Part 3 will be building off the skills learned in Part 1 and Part 2 so be sure that you are familiar with those tools and technologies before beginning t...

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Europractice | Cadence Academic Network | CMC Microsystems | Virtuoso | online training | SKILL | university program
Xcelium ML: Black-Belt Verification Engineer in a Tool

By Paul McLellan | 12 Aug 2020

What if I told you I knew someone who could improve your regression efficiency: make fewer runs, spend less runtime on the runs you do make, and have the same coverage at the end? You'd say that he or she sounds like a great verificati...

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deep learning | xcelium ml | machine learning | DVcon | xcelium | simulation
Virtuoso Meets Maxwell: Magic! – Dynamic Voiding in Virtuoso RF Solution

By skai | 11 Aug 2020

While SiP Layout Option is – and continues to be – one of the most complete solutions for package design, the Virtuoso RF Solution gives access to a constantly increasing set of package layout authoring capabilities inside the Virtuoso Layout Suite. Having...

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ICADVM18.1 | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso RF | Dynamic Shapes | Dynamic Voiding | Custom IC Design
BoardSurfers: Allegro In-Design Crosstalk Analysis: Signal Integrity Simulations on the PCB Canvas

By Shirin Farrahi | 11 Aug 2020

Crosstalk is the transfer of unwanted signals from an “aggressor” net to a “victim” and is one of the major classes of signal integrity (SI) problems that can exist in Printed Circuit Board (PCB) designs. Reducing crosstalk as...

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PCB design and layout | PCB Signal integrity | Allegro PCB Editor | Allegro
IC Packagers: Make Acute Angles a Sharp Problem of the Past

By Tyler | 11 Aug 2020

Sharp angles, whether they create a spike in a poured shape or form an acid trap between two different pieces of metal, are a problem for us all. And as designers, we will go out of our way to try and avoid creating these situations; they will still ...

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Allegro Package Designer | 17.4-2019
Cadence Executives on Computational Software

By Paul McLellan | 11 Aug 2020

CadenceLIVE starts today, Tuesday, August 11, and runs through Thursday. One thing that I know some of the keynotes will cover will be computational software, a name for many of the sorts of algorithms that underlie EDA and system design tools....

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computational software | cadencelive
Virtuosity: Multi-Technology Simulation (MTS)の実行方法は？

By Custom IC Japan | 11 Aug 2020

マルチ・テクノロジ・シミュレーション(Multi-Technology Simulation; MTS)を Virtuoso® ADE Explorer と Virtuoso® ADE Assembler で実行する方法を示したハンズオン型の資料をお探しですか？今日の急速にシュリンクしているテクノロジでは、カスタムICシステム・イン・パッケージ(System-in-Package; SiP)を設計する機会が増えています。しかし、ここで課題となるのが、異なるテクノロジを使用してこれらの...

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Explorer | Rapid Adoption Kit | Virtuoso | Spectre | ADE-XL | Virtuosity | japanese blog | Custom IC Design | Assembler | ADE Assembler
Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme

By Vijetha | 10 Aug 2020

This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.

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effective resistance | Silicon Signoff and Verification | electromigration | Voltus IC Power Integrity Solution | Power Signoff | electrostatic discharge | current density | power integrity | Innovus | Charged Device Model | Full-Chip | ESD
120th Anniversary of Hilbert's Problems

By Paul McLellan | 10 Aug 2020

The computational software algorithms used in EDA are fundamentally mathematical in nature. Many algorithms are various forms of computation using very large sparse matrices. Last Saturday was a significant anniversary in the foundations of mathemati...

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hilbert's problems | computational software | millennium prize problems
电子系统设计中进行片上热分析的四大挑战与应对

By SpbChina | 9 Aug 2020

在大约 138 亿年前的创生之初，我们的宇宙在 0 到 10-43 (10^(-43))秒的短短时间里产生和释放了大量的热量或能量，这在理论上得到了各种模型和测量数据的支持。自那以后，宇宙中各种各样的物理机制一直推动着能量不断转化为其他形式或者转化回热量，大到太阳中的核聚变，小到电子设备中计算机芯片上微型晶体管的自发热。而为了让每个系统都运行良好，无论是像病毒一样的活体，还是像智能手机一样的人造设备，工作温度范围都是与系统敏捷性息息相关的最重要因素之一。因此，在能量输入和输出的各种预期条件下，能...

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Celsius Thermal Solver | 热 | PI | Chinese blog | 电源完整性 | 热分析 | 3D 分析 | EE Thermal | 电热协同仿真 | 热传输 | Voltus | 中文 | 系统分析 | IC封装 | 异质封装
Weekend Update 2

By Paul McLellan | 7 Aug 2020

This is my second update post where I cover things that I have covered before, and where there is some news, but no enough to make a completely new post. The first update was Weekend Update . Cerebras Wafer Scale Engine I wrote about the Cerebras Wafe...

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Rigid-Flex

By Paul McLellan | 6 Aug 2020

Rigid-flex sounds like something that might be a Crossfit workout-of-the-day. But it is actually a way of doing electronic design for small form factors using flexible PCBs (typically along with some normal rigid PCBs too). But they require additiona...

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PCB | Rigid-Flex | Allegro
Why Attend CadenceLIVE Americas?

By Paul McLellan | 5 Aug 2020

We renamed our user conference to CadenceLIVE (from CDNLive) just in time for it not to be live and to go virtual. The first conference is CadenceLIVE Americas coming up from August 11th to 13th. Registration is now open. This is a global event. Comi...

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CDNLive | cadencelive 2020 | cadencelive americas | cadencelive
BoardSurfers：17.4-2019 HotFix 007 for Electrical CAD-Mechanical CAD Library Creator について

By SPB Japan | 4 Aug 2020

Library Creator 17.4-2019 HotFix 007のアップデートより、Templatesダイアログ全体に改良が加えられ、テンプレートを見つけて選択しやすくなりました。また、Propertiesウィンドウに多くの変更が加えられました。もう1つの注目すべき変更は、新しいルールをすばやく追加できるいくつかのボタンをConfigurationダイアログに追加したことです。ここから、変更の詳細についてご紹介します。ルールとコンストレイントを簡単に追加できます。ダイアログに新...

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Library Creator | PCB | 17.4 | PCB Editor | ECAD-MCAD Library Creator | japanese blog
2020年5月リリース、OrCAD / Allegro 17.4-2019 HotFix 007 の新機能ハイライト

By SPB Japan | 4 Aug 2020

OrCAD® 及び Allegro® のHotFix 007 (QIR 1)が Cadence Downloads からダウンロードできます。この新リリースでは、数多くの機能の改善や強化が行われており、その多くはお客様からのご要望、ならびに、我々が継続的に追求している使い易さとユーザーエクスペリエンスの向上というフォーカスに基づくものです。このリリースは、スプラッシュ画面においては”2020”と示されます。この最新バージョンを使い始めてみると、いたる所でちょ...

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PCB | 17.4 | OrCAD Capture | APD | PCB Editor | japanese blog
BoardSurfers: Installation Know-How: Six Things You Need to Know Before Installing Cadence OrCAD and Allegro Products on Windows

By Shikha Jain | 4 Aug 2020

Installation of software applications depends upon certain factors such as system configuration, the number of files getting installed, and network speed. Installation time is influenced by a change in any of these elements and hence individual...

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Allegro OrCAD Installer | OrCAD | Allegro
IC Packagers: Removing and Replacing an Area of a Design

By Tyler | 4 Aug 2020

If you ever have the need to remove an area of your design, you may find it to be a more complex process than you would think. Shapes in that area will, if you select them with show element, want to pick up the entire shape. That may extend well outs...

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IC Package | Allegro Package Designer | 17.4-2019
Accellera Functional Safety

By Paul McLellan | 4 Aug 2020

This is my last post about DAC 2020. During DAC Accellera had a workshop about functional safety. In case you don't know, Accellera has a relatively new working group (WG) on Functional Safety. The chair is Cadence's Alessandra Nardi, who coi...

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automotive | functional safety | Accellera | fusa
Custom IC, Analog, and RF Design Training Deep Dive: Part 2

By Kira Jones | 3 Aug 2020

Let’s continue exploring the training courses related to Custom IC, Analog, and RF Design. We’re going to be introducing some new courses and some new tools in these training recommendations. It is recommended that you start with Custom I...

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Europractice | Cadence Academic Network | CMC Microsystems | Virtuoso | online training | university program
DAC 2020: Chips in 2030

By Paul McLellan | 3 Aug 2020

In 2015, soon after I rejoined Cadence, I went to IEDM, the International Electron Devices Meeting. That year it was in Washington DC. I paid for most of the trip myself since I'd already booked the flights and hotels months in advance to get goo...

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57dac | DAC | Design Automation Conference
Virtuosity: Analog Design Environmentにおけるポストレイアウト関連の機能強化トップ３

By Custom IC Japan | 2 Aug 2020

今日のブログでは、ポストレイアウトフローの最新の機能強化について説明します。これらの機能強化により、回路図とポストレイアウトの名前のマッピング、端子電圧のプロット、DSPFファイルのスイープなど、長年の問題の多くが解決されます。このブログは、 Virtuoso®ADE Assembler 、 Virtuoso®ADE Explorer および Virtuoso® Visualization and Analysis のリリースされたばかりの機能をカバーするために、週に2回（火曜日と...

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ADE Explorer | post-layout | DSPF | Virtuoso Analog Design Environment | postlayout | Virtuosity | japanese blog | ADE Assembler
Virtuoso Meets Maxwell: How Come There is No Mention of Wirebonded ICs?

By Steve PDK Lee | 2 Aug 2020

Hello and welcome to Virtuoso Meets Maxwell. If you are a regular reader you might be thinking to yourself, “There’s not a lot about wirebonds in the Virtuoso RF Solution and I’m interested in wirebond support.” That’s a great observation and it’s time...

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ICADVM18.1 | Co-Design | Virtuoso System Design Environment | Virtuoso RF | Wirebond | Electromagnetic analysis | Virtuoso | Custom IC Design | Allegro
Sunday Brunch Video for 2nd August 2020

By Paul McLellan | 2 Aug 2020

www.youtube.com/watch Made in "Indonesia" (camera me) Monday: Open Source Hardware Tuesday: DAC 2020: The State of the Industry Wednesday: DAC 2020: Open-Source EDA Thursday: Recruiting and Onboarding during WFH Friday: DAC 2020: TSMC ...

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sunday brunch