Cadence Blogs

DesignCon: The Future of Fiber Optic Communications

By Paul McLellan | 24 Feb 2020

At the recent DesignCon, Chris Cole gave the keynote The Future of Fiber Optic Communications: Data Center and Mobile. He was working at Finisar who got acquired, and he had just begun work at photonics startup Luminous Computing. Judging by the...

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Ethernet | silicon photonics | photonics | datacenter | networking
Sunday Brunch Video for 23rd February 2020

By Paul McLellan | 23 Feb 2020

https://youtu.be/CPNy6CjnvEs Made on my balcony (camera Carey Guo) Monday: President's Day Tuesday: DVCon 2020 Preview Wednesday: What If It's Not 5G, But Satellites? Thursday: Getting on to the Internet in 1993 Friday: DesignCon: Design for Security...

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sunday brunch
年度网课：极致PCB设计全流程网课计划

By SpbChina | 21 Feb 2020

“工欲善其事，必先利其器”，我们要高质高效完成PCB设计，除了有效的规划及设计策略外，还必须深入理解工具的使用方法和设计技巧。只有夯实这些基础，我们才能真正避免“重复劳动”，提升设计质量和效率。娴熟的PCB设计者，可以将更多时间分配于传输线理论、SI/PI、电磁场等理论知识的研究，做更深层次的PCB设计。为了兼顾不同观众的需求，今年我们采用“理论知识 + 实战演示”，的方式，循序渐进地与大家在线分享PCB设计各个阶段的基...

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Chinese blog | training | webinar | PCB设计 | 中文 | 直播网课 | online training
Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton and Cadence Liberate Trio

By Seena Shankar | 21 Feb 2020

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors.

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Liberate Trio Characterization | Unified Flow | Variation Modeling | artificial intelligence | ARM-based Graviton Processors | liberate blog | Amazon Web Services | Multi-PVT | Liberate LV | Liberate Variety | machine learning | aws | PVT corners | Liberate | Liberate Characterization Portfolio | TSMC OPI Ecosystem Forum 2019
DesignCon: Design for Security

By Paul McLellan | 21 Feb 2020

At DesignCon, one of the keynotes was by Warren Savage titled Design for Security: The Next Frontier of Smart Silicon. I have known Warren for years—he has been in IP for a long time, most recently as CEO of IPextreme, which he founded in 2004 ...

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Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 1

By Dishika Majumdar | 20 Feb 2020

This blog will take you on a short tour to the Cadence Education Services site, which has several online training courses and bytes based on specific features of Virtuoso products.

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training bytes | Virtuoso | Virtuoso Video Diary | Virtuoso Layout
Getting on to the Internet in 1993

By Paul McLellan | 20 Feb 2020

I recently listened to an a16z podcast about crypto. It was an interview by Katie Haun with Marc Andreessen, the co-founder of Andreessen-Horowitz aka a16z. For me, the most fascinating part was not the crypto, but two aspects of the ...

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Internet | a16z | history
What If It's Not 5G, But Satellites?

By Paul McLellan | 19 Feb 2020

What if the answer to next-generation communication is not 5G but space? Elon Musk apparently noticed that the margins of the companies for which Space X was launching satellites were better than Space X's own margins. So why not use those rocke...

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5G | automotive | mobile | space
IC Packagers: An Introduction to Via Arrays

By Tyler | 18 Feb 2020

Vias are present in every design (except maybe some lead frames and the very rare single-layer substrate). Where they are placed, and how many there are, will depend on a slew of factors, though, as we know. There are different situations and reasons...

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Allegro Package Designer
BoardSurfers: Training Insights - Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

By mrigashira | 18 Feb 2020

In the days of yore when life was simple, there was a world full of DRAMs (Dynamic Random Access Memory). We have come a long way from there. First came Synchronous DRAMs (SDRAMS). Isn't it neater anyway, SDRAM? More systematic and organized, in tune...

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Allegro Package Designer | Sigrity | Allegro PCB Editor
Playing for Good

By Madhavi Rao | 18 Feb 2020

Last Saturday, Cadence and Concern India Foundation hosted a very special event - a charity sports tournament for corporates called “5Cs” – the Corporate Citizenship Challenge for the Cause of Children. It is one of the most fun eve...

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5Cs | NXP Semiconductor | amadeus | Qualcomm
DVCon 2020 Preview

By Paul McLellan | 18 Feb 2020

Coming up to the big conferences like DAC, I like to do one or more preview posts, both as a service for people who are already going to help them decide what to attend, and also to encourage people in the industry to attend. DVCon is another confere...

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DVcon | Accellera | pss
Sunday Brunch Video for 16th February 2020

By Paul McLellan | 16 Feb 2020

https://youtu.be/uc_vrZsq-2I Made in Cadence parking lot (camera Steve Brown) Monday: Benedict Evans 2020: Standing on the Shoulders of Giants Tuesday: Benedict Evans 2020: Regulating the Giants Wednesday: System Analysis: Computational Software....

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sunday brunch
BoardSurfers: PCB Electronics—Why Use Via Arrays?

By mrigashira | 14 Feb 2020

We all know the ubiquitous via. What is it after all but a way to make electrical connections in a multi-layered PCB? But if you think about it, it must have been a clever ....

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Allegro Package Designer | Allegro PCB Editor
Quines on Valentine's

By Paul McLellan | 14 Feb 2020

Monday is President's Day and Cadence is off so, as has become traditional, I write about something off-topic the day before. Today's topic is self-reproducing programs. A self-reproducing program is also known as a Quine. The term Quine was ...

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offtopic
Virtuosity: Updated Virtuoso ADE Explorer and ADE Assembler RAKs in IC6.1.8/ICADVM18.1 ISR9

By Arja H | 13 Feb 2020

To show the latest features in IC6.1.8/ICADVM18.1 ISR9, we've updated the Rapid Adoption Kits for Virtuoso ADE Assembler and Virtuoso ADE Explorer. In addition, we have updated the RAK that explains the Stimuli Assignment form.

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ICADVM18.1 | ADE Explorer | Rapid Adoption Kit | RAK | stimuli | Virtuoso Analog Design Environment | Virtuosity | Custom IC Design | ADE Assembler | Stimuli Assignment form
Under the Hood of Clarity and Celsius Solvers

By Paul McLellan | 13 Feb 2020

Yesterday, in my post System Analysis: Computational Software at Scale, I talked about computational software at scale and the three aspects that Cadence is delivering: Algorithms that operate on unimaginably huge amounts of data Scaling algori...

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celsius | computational software | clarity
System Analysis: Computational Software at Scale

By Paul McLellan | 12 Feb 2020

In about 2000, when I was the VP of Strategic Marketing for Cadence, I got a strange voicemail that started "This is Regis McKenna...". If you are old enough, you know that Regis, and his PR firm Regis McKenna Inc, was a legend in&nbsp...

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celsius | Matrix | intelligent system design | clarity
Third Annual RESCUE Winter Workshop

By Marianne Paz | 11 Feb 2020

Cadence hosted the third annual RESCUE Winter Workshop from 14th to 22nd of November 2019, in Feldkirchen, Germany. The Winter Workshop is an annual event attended by the RESCUE participants. Cad...

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Cadence Academic Network | rescue
IC Packagers: RF Symbols, Coils, and Structures in IC Packages

By Tyler | 11 Feb 2020

So, you need to add more complicated structures into your package design. What options do you have available to you in the Cadence packaging products with the 17.4 release – whether you’re using the base Allegro Package Designer Plus or h...

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Allegro Package Designer
Benedict Evans 2020: Regulating the Giants

By Paul McLellan | 11 Feb 2020

This is the second post about Benedict Evans' annual big presentation about the internet. Part 1 appeared yesterday in my post Benedict Evans 2020: Standing on the Shoulders of Giants . Regulation We connected everyone... including the bad people......

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benedict evans | mobile | regulation
Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple

By Neelabh | 10 Feb 2020

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality. The diagram below shows two lane adapters connected to each other and...

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Verification IP | DP | VIP | DisplayPort | PCIExpress | USB | Lane Adapter | usb4 | PCIe | usb4 router | tunneling
Library Characterization Tidbits: Liberate MX for Memory Characterization Video Series

By Jommy | 10 Feb 2020

As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.

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Liberate MX validation flow | memory characterization | liberate_mx custom flow | standard custom flow | full custom flow | liberate_mx standard custom flow | compiler characterization | liberate_mx full custom flow | liberate_mx | Liberate MX | Characterization Portfolio
Benedict Evans 2020: Standing on the Shoulders of Giants

By Paul McLellan | 10 Feb 2020

For the last five or six years, Benedict Evans worked at Andreesen-Horowitz (a16z) and would do a big presentation on the state and future of the internet at the end of each year. He recently left a16z to return to the UK (he's English) and so hi...

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benedict evans | Internet | mobile
Sunday Brunch Video for 9th February 2020

By Paul McLellan | 9 Feb 2020

https://youtu.be/CVbxaO8cVoM Made in Steve's office (camera Steve Brown) Monday: Persistent Memory at Twitter Tuesday: How Technologies Get into EDA Wednesday: The Signal Integrity Story Thursday: Exadata: An Epic Journey at Oracle with Persisten...

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sunday brunch