Cadence Blogs

Clarity, Sigrity, EMX, and AWR: So Many EM Solvers to Choose From…

By Paul McLellan | 16 Jul 2020

Cadence has multiple electromagnetic (EM) technologies within its product portfolio as of today. Some came via acquisition and others were created internally. With a wide breadth of EM simulation and analysis tools within the Cadence prod...

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RF | AXIEM | Virtuoso RF | EMX | Sigrity | EM | clarity
Analyzing On-Chip RF Passives

By Paul McLellan | 15 Jul 2020

RF stands for radio-frequency. Obviously, this covers radios of all types, but as Brad Brim said to me when I interviewed him on his retirement (see my post Brad Brim and the History of Signal Integrity ) "digital signal frequencies are in the range t...

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RF | EMX | RF design | radio
iSpatial Flow in Genus: A Modern Approach for Physical Synthesis

By Neha Joshi | 14 Jul 2020

With advanced-process nodes, the physical delay of a standard cell, net delay, and congestion all lead to a higher requirement on the netlist. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical...

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Genus | video | Logic Design | physical implementation
BoardSurfers: Training Insights: Adding and Re-Ordering Mask Layers

By Shreyansh | 14 Jul 2020

One idea that completely revolutionized the concept of PCB making is adding layers to it. These layers are everywhere and used for everything in a PCB – whether you have to mount the components, provide insulation while keeping the mounting pads accessible...

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17.4 | 17.4-2019 | PCB design | Allegro PCB Editor
IC Packagers: Renaming Nets in a Layout

By Tyler | 14 Jul 2020

As the component count increases in package/interposer designs, many more of you are turning to front-end schematic tools for managing the netlist and connectivity. When working directly inside the layout design, however, there remain many cases wher...

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17.4 | IC Packaging | Allegro Package Designer | 17.4-2019
Zhuo Li, DAC Chair, Plus Cadence@DAC

By Paul McLellan | 14 Jul 2020

Yesterday was my DAC Preview post. As it happens, Cadence's Zhuo Li is this year's DAC chair. In his day job, Dr Li manages our clock-tree synthesis (CTS) inside Innovus. He is based in Austin. At the end of this post I'll tell ...

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57dac | DAC | Accellera | Design Automation Conference
Virtuosity: 洗練されたExtractedビュー

By Custom IC Japan | 13 Jul 2020

Cadence® Quantus Smart Viewは、Virtuoso環境の次世代のExtracted Viewです。Smart Viewは、Extracted Viewと同等の機能を提供しますが、高効率で拡張可能なストレージ機構が使用されています。これはSmart Viewが、先端ノードにおける大規模で複雑なデザインを、抽出実行時間とネットリストのサイズを削減して扱うことが可能であることを意味しています。実際、Smart Viewは Virtuoso® ADE A...

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Smart View | PAD | ICADVM18.1 | ADE Explorer | Virtuoso | Parastics | Virtuosity | japanese blog | Quantus | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
Streamline Your PCB Design Flow with In-Design and Post-Route Power Integrity Analysis

By Sigrity | 13 Jul 2020

Designing an optimized power supply and a PCB without board-level SI/PI problems on time requires a tight collaboration between the design, layout, and PI engineers through an integrated design platform. A team-oriented design flow will empower the ....

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PCB | Allegro PCB Design Editor | Power Integrity Analysis | sigrity aurora | in-design | PowerTree | DC analysis | IR drop | PowerDC
DAC Preview 2020

By Paul McLellan | 13 Jul 2020

It is the 57th Design Automation Conference later this month from July 20 to 24. Of course, it is a "virtual experience". Apart from being virtual, many of the trappings of the conference remain: keynotes, SKY talks, tech talks, tutori...

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57dac | DAC | Design Automation Conference
Sunday Brunch Video for 12th July 2020

By Paul McLellan | 12 Jul 2020

https://youtu.be/kA0y55I9zMA Made on my balcony (camera Carey Guo) Monday: Cadence holiday Tuesday: How Do You Run One Architecture on Another? Wednesday: Photography of Computers Thursday: Photography with Computers Friday: There Is a Stat.....

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sunday brunch
Virtuosity: 新しいアイダイアグラムの測定

By Custom IC Japan | 10 Jul 2020

Virtuoso® Visualization and Analysis のEye Diagram アシスタントを使用すると、アイダイアグラムを作成したり、マスクを追加したり、いくつかの標準測定値を計算したりできます。最近では、ジッタ計算、アイの最大の高さと幅の計算、レベルの注釈、ビット誤り率（BER）曲線が追加され、測定が強化されています。新しいアイダイアグラムの測定新しいアイダイアグラムの測定値を表示する例を見てみましょう。アイダイアグラムをプロットし、Eye Measur...

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Eye Mask | Analog Design Environment | ViVa-XL | ADE Explorer | Explorer | ADE XL | ADE | eye diagram | ViVA | Virtuosity | japanese blog | Custom IC Design | ADE Assembler
Virtuosity: Usability Enhancements in the Chop Command of Virtuoso Layout Suite

By KomalJohar | 10 Jul 2020

The Chop command in Virtuoso Layout Suite has been enhanced to improve your productivity during interactive wire editing.

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ICADVM18.1 | Layout Suite | Virtuoso | layout editing chop | usability | Custom IC Design | IC6.1.8
BoardSurfers: 17.4-2019 HotFix 007 for ECAD-MCAD Library Creator Is Now Available

By Sanjiv Bhatia | 10 Jul 2020

The Library Creator 17.4-2019 HotFix 007 update is now available. This time, the entire Templates dialog has got a facelift that will make it easier to locate and select a template. A bunch of changes has been made to the Properties window. Another...

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Library Creator | 17.4-2020 | 17.4-QIR1 | 17.4-2019 | ECAD-MCAD Library Creator | PCB design | Allegro PCB Editor | Allegro
There Is a Statue of Nikola Tesla in Palo Alto...with Free WiFi

By Paul McLellan | 10 Jul 2020

Tesla is most famous these days as the name of a car company. But Nikola Tesla was an amazing inventor. Today, July 10, is his birthday. He was born in 1856 at Smiljan in what was the "The Austrian Empire" and today is in Croatia (but...

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anniversary | Nikola Tesla | tesla
Cadence Academic Network Welcomes AWR and EMX Users to Join Us!

By Anton Klotz | 9 Jul 2020

At the beginning of 2020, Cadence made two big announcements, as part of the Intelligent System Design (ISD) Strategy, Cadence has acquired AWR from National Instruments and Integrand for their EM-solver EMX. This move strengthens Cadence’s com...

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integrand | Cadence Academic Network | awr | EMX | intelligent system design | university program
Photography with Computers

By Paul McLellan | 9 Jul 2020

Yesterday, in my post Photography of Computers , I wrote about photographing computers, and in particular the marvelous book Home Computers: 100 Icons that Defined a Digital Generation. Today, I'm going to take a look at computers on the other si.....

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video | photography | mobile | Smartphone
Want to Explore Third-Party DFT Insertion Process in Genus?

By Neha Joshi | 8 Jul 2020

Are you concerned about the process to integrate third-party DFT insertion during synthesis? Stop worrying!! We have the solution! But: How it is done? What changes are recommended in the script while inserting third-party DFT in Genus? Are...

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scan | DFT | Logic Design | third-party
Photography of Computers

By Paul McLellan | 8 Jul 2020

In the early days of computers, I think computers were generally just called "computers". They occupied air-conditioned rooms with raised floors and were typically the size of several large (modern) refrigerators. The main long-term storage...

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fugaku | summit | home computers | photography
Virtuosity: In the Line of Veri-Fire - Episode 1

By Team ADE Verifier | 7 Jul 2020

Hi readers! Welcome to Veri-Fire, a space that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this mini-blog series that is posted within the Virtuosity space, Dr. Walter Hartong, a Product Engineer Architect...

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verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | Analog Coverage | verification plan | analog | ADE | analog verification | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | ADE Blog Series | FAQ | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | custom design technology | ADE Assembler | verification
IC Packagers: Automating Your LVS Text Label Generation

By Tyler | 7 Jul 2020

If you are using Allegro Package Designer Plus with the Silicon Layout option to design your substrates, it is likely that you are also using a formal verification platform such as Cadence Pegasus or PVS to check your physical layout against the logi...

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17.4 | IC Packaging | Allegro Package Designer | 17.4-2019
How Do You Run One Architecture on Another?

By Paul McLellan | 7 Jul 2020

You probably already heard that going forward some Macs are going to be running on the Arm-based chips that Apple developed for iPhone and iPads. You probably don't have time to watch an entire day of presentations but here are some highlights of...

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Intel | Apple | dynamic translation | jit
Sunday Brunch Video for 5th July 2020

By Paul McLellan | 5 Jul 2020

https://youtu.be/qimXaFAFh6w Made for July 4th (camera me) Monday: Yesterday Was Tau Day Tuesday: Alessandra Nardi Receives Marie Pistilli Award for Women in EDA Wednesday: Japanese Arm-Powered Supercomputer Takes the TOP500 Crown Thursday: July...

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sunday brunch
Virtuosity: Virtuoso ADE ユーザビリティ改善に関する最新情報

By Custom IC Japan | 2 Jul 2020

私たちの世界では、ユーザビリティとは、製品を使いやすくし、アクセスを簡単にし、視覚的に魅力的なものにすることです。私たちは製品の使い勝手を改善するため、絶え間なく努力します。Virtuosoのユーザビリティ向上について、ここに毎月投稿しますのでご注目ください。 IC6.1.8/ICADVM18.1のリリース以降、私たちは Virtuoso® ADE Assembler , Virtuoso ADE Explorer および Virtuoso Visualization and Analysi....

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ADE Explorer | Rapid Adoption Kit | ViVA | ADE Design Environment | Virtuosity | usability | japanese blog | Custom IC Design | ADE Assembler
Virtuosity: Good News for our Japanese Readers

By Dishika Majumdar | 2 Jul 2020

In this blog, I’m going to share some great news for our Japanese readers. Let's find out what it is…

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Trunk generation | ICADVM18.1 | AMS Designer | VPR | layout XL | Virtuoso | Japanese blogs | Virtuosity | advanced nodes | ASMD Flex Mode | Virtuoso Layout Suite | Custom IC
Virtuosity：大小一样的乐高积木，能拼出大师级杰作吗？

By KomalJohar | 2 Jul 2020

您需要使用不同大小和类型的积木块，才能拼出大师级的乐高杰作，基于WSP的设计也是如此，它需要将具有不同WSSPDef周期的多个模式的布线区域拼接在一起。接下来，让我们一起来探讨如何实现这一目标。

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Chinese blog | ICADVM18.1 | cadence | WSP | Advanced Node | Local regions | Layout Suite | width spacing patterns | Layout | Virtuoso | Virtuosity | usability | Custom IC Design | ux | WSSPDef