Cadence Blogs

Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III

By Kabir | 11 Nov 2019

This is the third blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. To know about the benefits of preprocessing of layout shapes for electromagnetic analysis, read

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ICADVM18.1 | Virtuoso Layout EXL | Virtuoso RF | Layout EXL | Electromagnetic analysis | Virtuoso | Custom IC Design
What's in a Name? From Allegro EDM to Pulse in 17.4-2019

By Auromala | 11 Nov 2019

Allegro EDM (Engineering Data Management) 17.4-2019 is out! So, what's in it for you?

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allegro edm | what's new | 17.4-2019 | PCB design | Pulse
The 2019 Jasper User Group

By Paul McLellan | 11 Nov 2019

Last week was the Jasper User Group meeting, the biggest annual gathering of formal verification engineers. This is the 13th meeting. Ziyad recalled the first, held at the TechMart, to which about 15 people attended. This year was the sixth since Cad...

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Jasper User Group | formal | Jasper | JasperGold | Formal verification
Exciting Academic News on OrCAD

By Anton Klotz | 9 Nov 2019

There’s some exciting news about the Cadence OrCAD® Software , especially for academics! Generations of analog designers have used Cadence ® PSpice® Simulator , which is a part of the OrCAD package, as their first analog simulator. Now...

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PCB | academia | Contest | OrCAD | university program
隐藏在PCB设计中的七个DFM问题

By TeamAllegro | 8 Nov 2019

本文由Cadence的北美经销商EMA Design Automation撰写。 space 当我们完成设计并将其送到制造厂后，如果我们的产品存在大量可制造性设计（DFM）错误，那么便会造成产品搁置。这种情况不仅令人沮丧，而且代价高昂。在项目早期尽早考虑制造问题有助于降低成本、缩短开发时间，并确保设计顺利过渡到生产阶段。相反，若不这样做，便会造成不良后果。凭借多年的行业经验，我们总结了7大妨碍PCB可制造性的主要DFM问题。虽然以下列出的部分内容是设计方面的最佳实践，但还有一些是由制作/制造...

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Chinese blog | DesignTrue DFM Technology | 可制造性设计 | PCB设计 | 中文 | DFM | Allegro
OpenTitan: Secure Boot with a Silicon Root of Trust

By Paul McLellan | 8 Nov 2019

At HOTCHIPS last year, Google presented its security processor Titan. You can read lots of details at my post Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter . Titan provides a silicon root of trust (RoT) ...

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opentitan | open source hardware | google | open source
Library Characterization Tidbits: Reasons to Start Following This New Blog Series

By AbhaRawat | 7 Nov 2019

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.

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Liberate AMS | videos | Liberate LV | Liberate Variety | library characterization | Application Notes | Liberate MX | training bytes | Liberate | Liberate Characterization Portfolio | RAKs
Computational Software

By Paul McLellan | 7 Nov 2019

This is the third post in a series on computation in EDA and adjacent markets. The previous two were Computation and the Data Explosion and Computational Hardware . All EDA algorithms are computationally intractable, in that it is impossible to ...

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computational software
ECE Master Students of Duke Kunshan University Visited Cadence Shanghai Office

By Tracy Zhu | 6 Nov 2019

The Cadence Academic Network was very excited to host students from Duke Kunshan University ‘s Electrical and Computer Engineering department at the new Cadence Shanghai office on October 25, 2019. Cadence R&...

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university | Cadence Academic Network | university program
Virtuoso Video Diary: Click – Take a Snapshot – Smile!

By Rashmi G | 6 Nov 2019

This blog talks about about the Snapshots feature introduced in ADE Verifier in IC6.1.8 ISR6.

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verifier | Analog Design Environment | ICADVM18.1 | Functional Verification | Formalized Verification | snapshots | ADE Verifier Snapshots | ADE | Mixed-Signal | Virtuoso | cadenceblogs | Virtuoso Video Diary | Custom IC Design | ADE Verifier | IC6.1.8 | Verifier new feature | verification
Tempus Power Integrity Solution

By Paul McLellan | 6 Nov 2019

One of the challenges in leading-edge nodes today is the resistivity of the interconnect. One day, new interconnect materials such as ruthenium (Ru) might help, but for now, we have copper interconnect, which requires a liner made from a relatively h...

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Tempus | Voltus | signoff
Specman: Analyze Your Coverage with Python

By teamspecman | 6 Nov 2019

In the former blog about Python and Specman: Specman: Python Is here! , we described the technical information around Specman-Python integration. Since Python provides so many easy to use existing libraries in various fields, it is very tempting to leverage...

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Specman | Specman coverage engine | coverage | Python | Functional Verification | Specman e | e | e language | specman elite | functional coverage
IC Packagers: Scripting Updates in 17.4

By Tyler | 6 Nov 2019

If you joined us last week to see the visual changes to be expected when you download 17.4, doubtless the next thing you need to know is how migrating will impact your automation. And, if you’ve installed the software already, you’re one ...

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APD | PCB Editor
Dead Ends

By Paul McLellan | 5 Nov 2019

Sometimes something comes along that looks like it is a portent of things to come, but then turns out to be a technological dead end. For example, in the 1990s, it seemed that you couldn't go to the mailbox or rent a video without getting an AOL...

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automotive | Breakfast Bytes
Cadence OrCAD and Allegro 17.4-2019 is Now Available

By AllegroReleaseTeam | 4 Nov 2019

Here is a sleeker and more modern version of the OrCAD and Allegro release, with enhanced usability and a slew of new productivity-enhancing features. With the 17.4-2019 release, you get more intuitive and easy-to-use flows that enable optimized schematic...

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Library Creator | System Capture | 17.4 | IC Packaging | OrCAD Capture | APD | PSPICE | PCB Editor | Constraint Manager | Topology Explorer
Is Design in India on the Upswing?

By Madhavi Rao | 4 Nov 2019

The India Electronics and Semiconductor Association (IESA) recently organized a two-day conference on Strategic Electronics, and, not surprisingly, the overriding message was that India needs indigenous chip design and wafer fabrication facilit...

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IESA | make in india | Design In India
IEDM 2019 Preview

By Paul McLellan | 4 Nov 2019

Coming up in the beginning of December is the 65th International Electron Devices Meeting (IEDM). The slightly strange name comes about because this is the 65th, meaning it started in the fifties, long before integrated circuits had been invented. In...

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IEDM
CDNLive China 2019 现场精彩回顾及演讲资料下载

By SpbChina | 1 Nov 2019

本文翻译节选自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“ CDNLive China 2019 “。 space CDNLive China 2019大会于2019年8月15日在上海成功举办。大会由Cadence中国及东南亚区总经理徐昀致开幕辞，接着由全球总裁Anirudh Devgan向大家介绍Cadence创新的 “智能系统设计（Intelligent System Design）” 战略。图1...

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Chinese blog | CDNLive | 中文 | CDNLive China 2019 | 智能系统设计 | Clarity 3D Solver
Computational Hardware

By Paul McLellan | 1 Nov 2019

This is the second part of a three-part series of posts on computation. The first part, Computation and the Data Explosion , appeared yesterday. Nothing is really as complex as a modern SoC. The AMD Zen2 chiplet contains nearly 4 billion transistors...

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computational software | computation
Virtuoso Video Diary: schTraceNet, a Simple Solution to Complex Questions!

By sarahfino | 31 Oct 2019

Take probing nets to the next level, define a callback based on the SKILL schTraceNet to answer your own complex questions on a schematic design hierarchy.

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schTraceNet | Virtuoso Schematic Editor | ICADVM18.1 | Net Tracing | video | tracing a net | Virtuoso | Schematic Editor | Virtuoso Video Diary | Probing | Circuit Design | Probes assistant | Custom IC Design | Custom IC | IC6.1.8 | Schematic | net area
Sigrity 2019 Release Now Available

By SigrityReleaseTeam | 31 Oct 2019

The Sigrity 2019 production release is now available for download.

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Celsius Thermal Solver | OptimizePI | Sigrity 2019 release | Clarity 3D Solver | XtractIM | PowerDC | PowerSI
Computation and the Data Explosion

By Paul McLellan | 31 Oct 2019

Everywhere you look these days, you get told that there is a data explosion going on. A Boeing 787 generates half-a-terabyte of data per flight. Facebook has 2.5 billion users. Five billion videos are watched on YouTube every day. This impacts the s...

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computational software | computation
Virtuosity: Automated Device Placement和Routing - Grid生成

By Sravasti | 31 Oct 2019

该博客是“Automated Device-Level Placement和Routing ”系列的第三个博客，着重强调了遵循网格化的布局和布线方法的重要性。您将看到automated device-level layout流程如何使您以最少的用户输入， device footprint的覆盖范围，层和DRCs，自动得出WSP和行区域。

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Chinese blog | Cadence blogs | Automated Device Placement | ICADVM18.1 | Automated Device-Level Placement | automation | Automatic Placement | Advanced Node | Auto Device P&R | Layout EXL | APR | Auto P&R | Virtuoso | Virtuosity | Virtuoso Placement | New in EDA | Custom IC Design | Custom IC
IC Packagers: Welcome to 17.4!

By Tyler | 30 Oct 2019

It’s here! Less than two weeks ago, on October 18, 2019, Cadence released the 17.4-2019 version of the Allegro product line. This means exciting new features, enhancements, bug fixes, and performance improvements to the tools you depend on to d...

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17.4 | APD
Implementing Automotive Radar on Tensilica Processors

By Paul McLellan | 30 Oct 2019

The big controversy about sensors in autonomous driving is whether lidar is essential. Radar has improved significantly in resolution and so I like to phrase the question as to whether radar is getting better faster than lidar is getting cheaper. Tod...

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automotive | radar | fmcw | ADAS