• Home
  • :
  • Community
  • :
  • Blogs

Blogs

Cadence Community
Cadence Community
  • Site
  • Community Search
  • User
Cadence Members

Login with a Cadence account.

LOG IN

Not a member yet?

Register | Membership benefits
Subscriptions

Get email delivery of the Cadence blog featured here

  • All Blog Categories
  • Breakfast Bytes
  • Cadence Academic Network
  • Cadence Support
  • Custom IC Design
  • カスタムIC/ミックスシグナル
  • 定制IC芯片设计
  • Digital Implementation
  • Functional Verification
  • IC Packaging and SiP Design
  • Life at Cadence
  • The India Circuit
  • Mixed-Signal Design
  • PCB Design
  • PCB設計/ICパッケージ設計
  • PCB、IC封装:设计与仿真分析
  • PCB解析/ICパッケージ解析
  • RF Design
  • RF /マイクロ波設計
  • Signal and Power Integrity (PCB/IC Packaging)
  • Silicon Signoff
  • Spotlight Taiwan
  • System Design and Verification
  • Tensilica and Design IP
  • Whiteboard Wednesdays
  • Archive
    • Cadence on the Beat
    • Industry Insights
    • Logic Design
    • Low Power
    • The Design Chronicles
  • Paul McLellan
    Update: Hogan, Mars, Australia, Solarwinds
    By Paul McLellan | 1 Mar 2021
    I don't normally do these updates this frequently, and never before have I produced an update on a post from just a week ago. Jim Hogan RIP One of my mentors passed over the weekend from a heart attack. Jim was one of the earliest employees of SDA,...
    0 Comments
    Tags:
    australia | solarwinds | Facebook | perseverance | Mars
  • RF Design Japan
    お客様発表 『 Fast MMIC Design with Distributed EM Analysis』のご案内
    By RF Design Japan | 28 Feb 2021
    概要 回路および電磁界(EM)解析を単一のコンピュータ上の複数のプロセッサ間または外部のリモートコンピューティングファーム全体に分散する機能により、リソースを大量に消費するMMIC、RFIC、およびファブリック間の設計問題の全体的な解析時間を大幅に短縮できます。並列計算を活用することで、設計チームはEMレベルの精度でオンチップ部品の値を容易に最適化し、数千とは言わないまでも数百回の最適化の反復を通じて設計オプションを完全に調査し、大規模システム(チップ、パッケージ、ボードアセンブリ)の性能を検....
    0 Comments
    Tags:
    AWR Analyst | AWR Design Environment | awr | AWR AXIEM | japanese blog
  • teamspecman
    Webinar: Extend the Language Using Specman e Macros!
    By teamspecman | 28 Feb 2021
    Using Cadence ® Specman ® Elite macros lets you extend the e language ─ i.e. invent your own syntax. Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and some are very advanced utilities implementing...
    0 Comments
    Tags:
    Specman | e | training | webinar | macros
  • Paul McLellan
    Sunday Brunch Video for 28th February 2021
    By Paul McLellan | 28 Feb 2021
    https://youtu.be/6wgF8p76x5g Made my personal cloud datacenter Monday: Arm/Cadence on Implementing Advanced Microprocessors in Advanced Processes Tuesday: The Death of Distance Wednesday: The OpenAccess Story Thursday: JAWS: JasperGold in the...
    0 Comments
    Tags:
    sunday brunch
  • Huiling Xiao
    Spectre Tech Tips: Introducing Spectre XDP-HB (Distributed HB)
    By Huiling Xiao | 26 Feb 2021
    Spectre XDP-HB was released in the SPECTRE 20.1 base release as part of the new Spectre X-RF simulation technology. Spectre XDP-HB uses a highly distributed multi-machine multi-core simulation technology to perform HB and HB small-signal analyses. In...
    0 Comments
    Tags:
    Spectre RF | Spectre XDP-HB | Spectre X-RF | Spectre X distributed simulation
  • mrigashira
    (P)SpiceItUp: Simulation Profiles in Five Steps
    By mrigashira | 26 Feb 2021
    After completing a circuit, it’s time to run simulations. The first step is to define a simulation profile. A simulation profile controls which analysis is run and what resources are to be used, for example, the models which define the parts fo...
    0 Comments
    Tags:
    17.4 | OrCAD Capture | PSpiceA/D | Capture CIS | 17.4-2019 | OrCAD
  • colint
    Virtuosity: Design, Plan, and Analysis - The 3 Sides Of A Coin, Episode 2
    By colint | 26 Feb 2021
    Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.
    0 Comments
    Tags:
    Congestion Analysis | Cadence blogs | Virtuoso Layout EXL | Floorplanning | Virtuosity | ICADVM20.1 | dpa | Pin Optimization | pin planning | Custom IC Design | Virtuoso Layout Suite | Design Planning and Analysis
  • Paul McLellan
    Liberate Trio on AWS/Graviton2 Instances
    By Paul McLellan | 26 Feb 2021
    This is a sort of continuation of yesterday's post JAWS: JasperGold in the AWS Cloud . It takes a look at the use of the Liberate Trio Characterization Suite on AWS, but this time on Arm-based Graviton2 instances. There was a recent Cadence/Arm C...
    0 Comments
    Tags:
    liberate trio | aws | ARM
  • Custom IC Japan
    Virtuoso Video Diary: Performance Diagnostic ツール – VirtuosoのMRIスキャナ
    By Custom IC Japan | 25 Feb 2021
    この間、私の母は膝の耐え難い痛みに苦しみ、私たちは医者を訪ねることを余儀なくされました。その痛みは外傷によるものではないため、原因を特定できませんでした。それでも、X線を撮って骨折や靭帯の損傷がないことを確認しました。医者は母にいくつかの鎮静剤を処方し、私たちを帰しました。鎮静剤はしばらく効きましたが、痛みが戻ってきたため、またクリニックに行きました。 今度は、MRIを撮り、その他のいくつかのテストを行って、最終的に痛みの背後にある本当の原因を診断することができました。正しい治療により、母は健康...
    0 Comments
    Tags:
    performance diagnosis | Virtuoso | performance diagnostic | ICADVM20.1 | japanese blog | Custom IC Design | Custom IC | Virtuoso scanner
  • Laura Charabot
    My Life at Cadence: Aspa Karanasiou
    By Laura Charabot | 25 Feb 2021
    At Cadence, we pride ourselves on creating and sustaining a company culture, that drives innovation and business success. To continue our series of EMEA team members’ interviews, we spoke with Aspa Karanasiou, Senior Application Engineer based ...
    0 Comments
    Tags:
    Culture | GPTW | my life at cadence | women | LifeAtCadence | great place to work | cadence emea
  • Paul McLellan
    JAWS: JasperGold in the AWS Cloud
    By Paul McLellan | 25 Feb 2021
    At the CadenceCONNECT Jasper User Group meeting in December, one of the presentations was by Richard Paw of AWS on a Cadence/AWS project called JAWS, for JasperGold on AWS. I covered it in the second half of my presentation Jasper User Group: The Sta...
    0 Comments
    Tags:
    liberate trio | formal | Jasper | aws | ARM | JasperGold
  • RF Design Japan
    μWaveRiders:AWR VSSソフトウェアを使用したミックスドシグナルRFシステムの解析
    By RF Design Japan | 25 Feb 2021
    チームRFの "μWaveRiders" ブログシリーズは、Cadence AWR RF製品のショーケースとしてデビューします。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。 このシリーズの新しいブログに関する通知を受け取るために、Subscri...
    0 Comments
    Tags:
    RF Simulation | AWR Design Environment | AWR Visual System Simulator | Analysis | RF communications | RF design | Radar systems | AWR VSS | japanese blog
  • Claudia Roesch
    Virtuoso Meets Maxwell: Virtuoso RF Solution—The Flow Revolution Enters the Next Level
    By Claudia Roesch | 24 Feb 2021
    In many ways 2020 was an exceptional year with extraordinary challenges for all of us. Despite the unusual circumstances of a global pandemic, it was an exciting year with lot of product innovation that lies behind. To start with the Virtuoso Meets Maxwell...
    0 Comments
    Tags:
    5G | IMS | integrand | SiP | pegusas | Virtuoso Overture | VRF | Celcius | awr | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF | Allegro Package Designer Plus | EMX | AWR AXIEM | RF design | SiP Layout Option | ICADVM20.1 | Sigrity | Quantus | Clarity 3D Solver | Custom IC Design | Allegro | VMM
  • jgrad
    Virtuoso Meets Maxwell: EM 全视图提取功能
    By jgrad | 24 Feb 2021
    摘要: 本博客介绍了Virtuoso RF 解决方案的 全视图(full cellview)提取功能,允许用户提取一个完整布局视图的3D S参数模型用。欲知更多,请继续阅读
    0 Comments
    Tags:
    EM Analysis | Chinese blog | AXIEM | awr | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso RF | Electromagnetic analysis | 3D Planar | ICADVM20.1 | Custom IC Design | Virtuoso Layout Suite
  • Paul McLellan
    The OpenAccess Story
    By Paul McLellan | 24 Feb 2021
    When I worked for Cadence back in the early oughts, we developed a layout database called OpenAccess, usually abbreviated to OA. It had actually been designed from the ground up to be the native database that would underlay Cadence's physica...
    0 Comments
    Tags:
    OpenAccess
  • Team RF
    μWaveRiders: Simulating Mixed-Signal RF Systems with AWR VSS Software
    By Team RF | 24 Feb 2021
    This blog highlights the types of RF systems that AWR Visual System Simulator (VSS) communications and radar systems design software aids in analyzing. Future blogs in this series will include details on time-domain vs. frequency domain analysis, digital...
    0 Comments
    Tags:
    RF Simulation | AWR Design Environment | AWR Visual System Simulator | Analysis | RF communications | RF design | Radar systems | AWR VSS
  • Mary Kasik
    Black Students in Technology Scholarship Recipients Share Their Experiences
    By Mary Kasik | 23 Feb 2021
    In the second installment of our Diversity in Technology Scholarship blog series, we are sharing inspirational words and stories from our eight Black Students in Technology Scholarship recipients. They were selected based on their outstanding academi...
    0 Comments
    Tags:
    university | inclusion | Cadence Academic Network | black students in technology | cadence | diversity scholarships | diversity in technology | diversity | scholarships
  • Johnas Street
    Black History Month 2021: Become the Change Agents Our World Needs
    By Johnas Street | 23 Feb 2021
    While February is Black History Month, we should also take the other 11 months to focus on the future—one that is inclusive and promotes equity and equality. Unfortunately, the Black community is still working hard to remedy what happened in pa...
    0 Comments
    Tags:
    Black History Month | inclusion | LifeAtCadence | diversity
  • Asim Khan
    Mohammad Mujamil: A Story of Hard Work and Fortitude
    By Asim Khan | 23 Feb 2021
    Subsequent to my previous blog about the Cadence Scholarship Program, I bring to you another inspiring story featuring one of our students - Mohammad Mujamil. Meet Mohammad Mujamil Growing up with poverty always at the door, struggling...
    0 Comments
    Tags:
    CadenceCares | CadenceScholarshipProgram | cadence
  • Paul McLellan
    The Death of Distance
    By Paul McLellan | 23 Feb 2021
    You may have seen the news that if you read an interesting article in the Australian press, you cannot share it with your friends on Facebook. Say what? Cable TV Let's start with a bit of history. There is probably some similar story to this base...
    0 Comments
    Tags:
    news | distance | australia
  • RF Design Japan
    新しいミリ波MIMOレーダーシステムの設計
    By RF Design Japan | 22 Feb 2021
    レーダーは、反射した電波を使用して、物体の距離、角度、または速度を決定します。かつては航空宇宙および防衛産業の独占的な領域であったこれらの検出システムは、現在、消費者産業、特に自動車レーダーで人気を集めています[1]。部分的には、シリコンゲルマニウム(SiGe)やCMOS技術などの大量の半導体プロセスにより、大量の商用アプリケーション向けの費用効果の高いシステムが可能になっているため、商用採用が可能です。 このブログでは、商用レーダーアプリケーション向けの60GHz周波数変調連続波(FMCW)....
    0 Comments
    Tags:
    AWR Design Environment | AWR AXIEM | RF design | AWR Microwave Office | Radar systems | japanese blog | MIMO | Visual System Simulator(VSS)
  • Team RF
    Design of a Novel mmWave MIMO Radar System
    By Team RF | 22 Feb 2021
    Radar uses reflected radio waves to determine the range, angle, or velocity of objects. These detection systems that were once the exclusive domain of the aerospace and defense industry are now gaining popularity in the consumer industry, most notably...
    0 Comments
    Tags:
    AWR Design Environment | AWR AXIEM | RF design | AWR Microwave Office | Radar systems | mmWave MIMO radar | Visual System Simulator (VSS) | MIMO
  • Paul McLellan
    Arm/Cadence on Implementing Advanced Microprocessors in Advanced Processes
    By Paul McLellan | 22 Feb 2021
    Late in January, Cadence and Arm ran a joint webinar on implementing advanced microprocessors in advanced processes using the digital full flow for implementation and signoff. The opening presentation was by Arm's Dermot O'Driscoll. Then Yufeng Luo p...
    0 Comments
    Tags:
    graviton | neoverse | digital full flow | ARM
  • Shyam Sharma
    Taking LPDDR5 to the Next Level
    By Shyam Sharma | 19 Feb 2021
    To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies supported by its latest low power memory offering LPDDR5...
    0 Comments
    Tags:
    Verification IP | Memory | VIP | JEDEC | lpddr5 | lpddr5x
  • tfox
    DisplayPort 128b/132b Concurrent LTTPR Link Training
    By tfox | 19 Feb 2021
    Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer and non-transparent Link Training-Tunable PHY Repeater...
    0 Comments
    Tags:
    Verification IP | DisplayPort | TripleCheck
>