Cadence Blogs

IC Packagers: Mysteries Revealed - Why is Flip-Chip Chip-Down the Default Library Die Orientation?

By Tyler | 28 Jan 2020

We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper into the exciting new capabilities to be found in the 17.4 release, though, I’d like to address a question I hear from new users all the time. That q...

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Allegro Package Designer
IEDM: Novel Interconnect Techniques Beyond 3nm

By Paul McLellan | 28 Jan 2020

During the short course on the Sunday before IEDM, Chris Wilson of imec presented Novel Interconnect Techniques for Advanced Devices Beyond 3nm. In some ways, this is a complementary presentation to the one given by TSMC that I covered last week in I...

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interconnect | imec | IEDM
RIP Clayton Christensen

By Paul McLellan | 27 Jan 2020

Clayton Christensen died last Thursday, at the relatively young age of 67. He was the author of what I think is the best book on strategy for high-tech organizations, The Innovator's Dilemma. I have purchased several copies since I first read it,...

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clayton christensen | innovator's dilemma
Virtuosity: Reminiscing About The Last 'Teen' Year of Custom IC Design Blogs

By Dishika Majumdar | 24 Jan 2020

If you have missed reading any of our Virtuosity, Virtuoso Meets Maxwell, Virtuoso Video Diary blogs that were published in 2019, or you would like to go back to an ISR release announcement to see what were the featured enhancements, here's your chance...

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ICADVM18.1 | Automated Device-Level Placement and Routing | Virtuoso RF | Layout EXL | Electromagnetic analysis | Virtuoso | Virtuosity | Custom IC Design | Virtuoso Layout Suite | Custom IC
IEDM: TSMC on 3nm Device Options

By Paul McLellan | 24 Jan 2020

At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and Beyond during the short course on Sunday. He divided his presentation up into four parts: Historical CMOS scaling trends FinFET improvements Nanosheet advantages ...

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TSMC | IEDM
BoardSurfers: Leveraging IPC-2581 Spec Element Capabilities to Streamline Design and Manufacturing Relationship

By Monika | 23 Jan 2020

If you are a PCB designer and follow IPC-2581 guidelines to design a board, this soluti....

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Manuafacturing | PCB Editor | 17.4-2019 | IPC-2581
DesignCon 2020: SI, PCB, Packaging, Photonics

By Paul McLellan | 23 Jan 2020

Next Tuesday through Thursday, January 28 to 30, DesignCon 2020 takes place in the Santa Clara Convention Center. it is actually their 25th anniversary. I think of DesignCon as being about everything other than chip design, but increasingly the focus...

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PCB | DesignCon | signal integrity | OrCAD | Sigrity | Allegro
DATA Pulse: Simplify Your ECAD Data Release Process While Ensuring Process Control

By Auromala | 22 Jan 2020

Do you dread your ECAD to PLM publishing process? If yes, worry not. We have a solution.

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System Capture | allegro edm | PCB design | Pulse | PLM
IEDM: Automating DTCO for 3nm

By Paul McLellan | 22 Jan 2020

At IEDM in December, Lars Liebmann of TEL presented Design Technology Co-Optimization for 3nm and Beyond. The challenge in designing a modern process is that scaling is no longer based on incremental change purely at the process level. Design Te...

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3nm | IEDM | DTCO
Virtuosity：Modgen中的布局重用流程

By Aneesh Shastry | 21 Jan 2020

Modgen 现在支持布局重用流. 请继续阅读，了解如何使用此功能通过减少创建 Modgen 的时间和精力来提高版图效率.

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Chinese blog | Modgen On Canvas | ICADVM18.1 | MODGEN | Layout Suite | Layout | Virtuoso | Virtuosity | Layout design | Custom IC Design | modgens | Virtuoso Layout Suite | Custom IC
IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

By Tyler | 21 Jan 2020

When you need to make an edit to a component, whether that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability changes back to the IC design team, there ar...

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Allegro Package Designer
A Big Problem with Big Data

By Paul McLellan | 21 Jan 2020

I happened to read a blog post that referred to a 2018 paper in The Annals of Applied Statistics with the title Statistical Paradises and Paradoxes in Big Data: Law of Large Populations, Big Data Paradox, and the 2016 Presidential Election . The ...

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deep learning | big data
技术性：器件的自动布局和布线 — 基于行的器件放置

By Sravasti | 21 Jan 2020

Device-level automatic placer允许您以约束和网格兼容的方式放置器件和设备组. 您可以使用交互式设备放置选项半自动放置设备.

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Chinese blog | Automatic Placement | Virtuoso Placer | Auto P&R | Virtuosity | Virtuoso Placement | Custom IC Design
Sunday Brunch Video for 19th January 2020

By Paul McLellan | 19 Jan 2020

https://youtu.be/O90mUZyWIeE Made at Lick Observatory (camera Carey Guo) Monday: Details of TSMC's IEDM Presentation on N5 Tuesday: Mark Cuban on Media and AI Wednesday: 5G in 2020 Thursday: Emerging Memory Friday: Off-topic: Picas...

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sunday brunch
Off-Topic: Picas, Points, and Printing

By Paul McLellan | 17 Jan 2020

Monday is Martin Luther King, Jr Day, and Cadence will be off. Breakfast Bytes will not appear. And so today is the last day before a holiday, and so I write about something off-topic. Today, printing. In fact, it is not totally off-topic since print...

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offtopic | printing
Virtuoso视频日记：简单的方法来解决复杂的问题——schTraceNet

By sarahfino | 16 Jan 2020

基于SKILL函数 schTraceNet 定义一个回调函数，将被探测的信号带入到下一层，这样就可以解决层次化原理图设计中遇到的复杂问题。

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schTraceNet | Chinese blog | Virtuoso Schematic Editor | ICADVM18.1 | Net Tracing | video | tracing a net | Virtuoso | Schematic Editor | Virtuoso Video Diary | Probing | Circuit Design | Probes assistant | Custom IC Design | Custom IC | IC6.1.8 | Schematic | net area
Emerging Memory

By Paul McLellan | 16 Jan 2020

SNIA, the Storage Networking Industry Association, organized a webinar recently with industry analysts Tom Coughlin (of Coughlin Associates) and Jim Handy (of Objective Analysis). The webinar was about emerging memories, meaning MRAM (magnetic), ReRA...

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Memory | optane | MRAM | persistent memory | 3dxpoint
Of Brains and Computers: Keynote by Dr Jan Rabaey

By Madhavi Rao | 15 Jan 2020

One of the industry’s biggest events, the VLSI Design Conference, took place in Bangalore last week. This conference does a round-robin of cities, and this was the 10th time in its 33-year history that Bangalore was hosting it (the last time wa...

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janrabaey | VLSID2020 | BWRC
5G in 2020

By Paul McLellan | 15 Jan 2020

There is a famous quote, attributed to Mark Twain but more likely said by his friend Charles Dudley Warner: Everybody talks about the weather but nobody does anything about it. I think that 5G in 2020 is going to be like that. You will hear lots of...

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5G | CES | ces2020
BoardSurfers: DFF - Three Steps to Perfect Mask Defined Padstacks in Your PCB

By mrigashira | 14 Jan 2020

We will of course not venture into the finer points of the debate about mask-defined pins (SMD) and metal-defined pins (NSMD) but assume that for whatever reasons, we have mask-defined pins in our design and we want our design to be to be fabricated correctly...

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PCB Editor
IC Packagers: The Default Bond Wire Profile - PROFILE1 (And Three Reasons Why Not to Use It)

By Tyler | 14 Jan 2020

For those of you who do wire-bond package substrate – whether you’re designing a single-chip leadframe, a multi-die memory stack, or a complex stack with wire-bonds, flip-chips, interposers, and spacers all in one – you need wire pr...

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Allegro Package Designer
Mark Cuban on Media and AI

By Paul McLellan | 14 Jan 2020

At CES there was a session in which Mark Cuban was interviewed. As he pointed out, he used to be most famous for being an entrepreneur, and then it was because he was the owner of the Mavericks basketball team, and now it is mostly his appearances on...

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CES | ces2020 | AI
Virtuosity: 针对高阶工艺节点的器件级布线工具— 树型布线流程

By Parula | 13 Jan 2020

本博客是Virtuoso器件级布线系列博客的最终篇，将介绍树干和树枝形成树的完整过程，通过这种类比方式，便于用户全面了解Tree Route 的流程及其功能. 前文回顾在进入本篇博客前，让我们回顾下之前的相关博客：

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Chinese blog | tree routing | structured routing | ICADVM18.1 | Virtuoso Space-based Router | mesh routing | Layout EXL | trunk-to-trunk mesh | Mixed-Signal | Tree Route | Layout Suite | trunk creation | Generate Trunk | Custom IC Design | Virtuoso Layout Suite | Custom IC
Details of TSMC's IEDM Presentation on N5

By Paul McLellan | 13 Jan 2020

At IEDM in December, one of the papers in the very last session (a sneaky trick to get us all to stay) was TSMC announcing their 5nm process. The paper actually had the cumbersome title 5nm CMOS Production Technology Platform Featuring Full-Fled...

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n5 | TSMC | 5nm | IEDM
Sunday Brunch Video for 12th January 2020

By Paul McLellan | 12 Jan 2020

https://youtu.be/y62D4tVK-_k Made at CES 2020 (camera Gerard Andrews) Last Thursday: The History of Lithography, Part 1: From Stones to Lasers Last Friday: The History of Lithography, Part 2: From Double-Patterning to EUV Monday: Proti...

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sunday brunch