Cadence Blogs

IC Packagers: Constructing Components from Manufacturing Data

By Tyler | 20 Jun 2019

We’ve all been there. The only (or most accurate) data that we have for a component is the manufacturing data from another process. It could be a GDSII file for the top-layer metal of an IC or a Gerber film for the BGA ball pattern. If all you ...

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IC Packaging and SiP | APD | SiP Layout
BoardSurfers - Aerials and Bails: How to Split a Viastack

By Monika | 20 Jun 2019

Today’s compact and powerful devices require small and high-density PCBs. Tight routing around densely packed components is thus indispensable, but cannot be achieved using conventional blind-buried and through-hole vias. Consequently, stacked vias have...

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APD | PCB Editor | SiP Layout | Allegro
What Is 5G?

By Paul McLellan | 20 Jun 2019

At the DAC theater, Cadence's Ian Dennison talked about 5G Intelligent System Design. He repeated his presentation internally at Cadence a couple of days later. Plus, I sat next to him at both CDNLive EMEA and DAC, while I signed books and he tal...

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5G | mmwave | IoT | mobile
Exploring AI / Machine Learning Implementations with Stratus HLS

By SeanDart | 19 Jun 2019

A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the important goals of achieving lower power or higher performance...

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High-Level Synthesis | TensorFlow | machine learning | Stratus | SystemC | HLS | AI
Assessing Bias in Computer Vision Systems

By Paul McLellan | 19 Jun 2019

I came across a fascinating document from Facebook on methods to assess bias in computer vision systems. At F8 2019 (their user conference), they highlighted some of the things that they are doing to address labeling bias, algorithmic bias, and more...

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imagenet | Computer Vision | Facebook | convolutional neural networks | neural networks | bias
Whiteboard Wednesdays - Passport Partners Program Expands Customer Cloud Deployment Options

By Corrie Callenbach | 18 Jun 2019

In this week's Whiteboard Wednesdays video, Craig Johnson explains the purpose of the Cloud Passport Partners Program and how customers can now connect with authorized and knowledgeable service providers to tackle complex cloud deployment projects. www...

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Whiteboard Wednesdays | Cloud Passport | Cloud-based Design | cadence cloud
DAC: The View from Wall Street

By Paul McLellan | 18 Jun 2019

Jay Vleeschhouwer did his annual...well, he did it last year, too...View from Wall Street in the DAC Pavilion. I've known Jay for years since I spent a couple of years being the person in Cadence who was house-trained on what I could and could no...

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DAC | wall street | vleeschhouweer
IEEE WIE ILC and Diversity

By MeeraC | 17 Jun 2019

Sultry, sultry, Austin, Texas. This was the site of the IEEE WIE ILC conference held on May 23-24, and I had the privilege of attending both days, along with 1400 other attendees. From the IEEE WIE ILC conference website, the conference is described ...

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IEEE WIE ILC | complexity | Cadence on the Beat | gender | ethics | machinelearningdeeplearning | saving the world
Virtuoso IC6.1.8 ISR4 and ICADVM18.1 ISR4 Now Available

By Virtuoso Release Team | 17 Jun 2019

The IC6.1.8 ISR4 and ICADVM18.1 ISR4 production releases are now available for download.

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ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | Interactive and Assisted Routing | Virtuoso RF | ADE | Virtuoso Analog Design Environment | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
Designing a Wi-Fi HaLow Baseband in Less than Six Months

By Paul McLellan | 17 Jun 2019

At CDNLive EMEA last month, Stefan Stanic of Methods2Business (M2B) presented The Challenge of Designing a First-TIme-Right Wi-Fi HaLow Baseband in Less than Six Months. WI-FI HaLow is a standard for superior IoT connectivity. Links can be up to 1km...

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CDNLive | CDNLive EMEA | Stratus | high level synthesis
DATA Pulse: Know How to Effectively Manage Part Obsolescence

By Auromala | 16 Jun 2019

You know what it's like, right? Those sudden urges to declutter the house. Well, during one such exercise, my niece stumbled across some cassettes and looked at them like they were from some prehistoric age. How could I convey the importance of the audio...

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allegro edm | Library and design data management | EDM | PCB design
Sunday Brunch Video for 16th June 2019

By Paul McLellan | 16 Jun 2019

https://youtu.be/CaIc3qOakxs Made at building 9 elevator (camera Sean) Monday: Cadence Cloud Passport Partner Program Tuesday: Making Trouble in Las Vegas Wednesday: Paris Air Show Thursday: Ericsson Using Virtual Platforms for Dynamic Analysis...

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sunday brunch
刚柔板装配与多板系统装配有何不同？

By TeamAllegro | 14 Jun 2019

通常我们考虑多层电路板PCB设计时，往往会想到服务器环境中的电路板机架或游戏平台组合。但是如果我们的典型刚性电路板并不适合多层电路板使用的实体机壳怎么办？我们会愿意付额外的价格来使用柔性电路板吗？如果我们可以将这两者的优点兼而有之呢？本文中，我们将介绍刚柔组合的优点、性质以及如何更好地满足多层电路板的PCB设计需求。什么是刚柔结合的PCB? 在标准多层电路板PCB设计中，我们采用电路板概念，将不同功能电路划分到较小的电路板上，并采用各种互连线路将系统放进一个外壳内。这种标准方法的问题在于....

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PCB | Chinese blog | 柔性电路 | PCB设计 | 中文 | Allegro PCB Editor | 刚柔结合 | Allegro | 多板系统
Single-Stop Learning Resource for JasperGold Formal Verification Platform

By SumeetAggarwal | 14 Jun 2019

While Our next-generation cloud-ready JasperGold® Formal Verification Platform features machine learning technology and core formal technology enhancements across all JasperGold apps, and provides industry-leading performance, capacity, usability...

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JasperGold | Cadence support
Cell-Aware Test: Research Cooperation Between Cadence, imec, and TU Eindhoven...Now Shipping in Modus DFT Software Solution

By Paul McLellan | 14 Jun 2019

At CDNLive EMEA, Zhan Gao presented her results on cell-aware test. This is the paper she presented at the Latin American Test Symposium (LATS) in Santiago, Chile in March and won the Best Paper award there (see Anton's post on the Academic Network b...

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Cadence Academic Network | modus | imec | cell-aware test
Ericsson Using Virtual Platforms for Dynamic Analysis

By Paul McLellan | 13 Jun 2019

At CDNLive EMEA last month, Ola Dahl of Ericsson presented Dynamic Software Analysis in Virtual Platforms. He described his job as "I work in the 5G network business doing basestations and radios." They have a virtual platform for one of th...

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CDNLive | virtual platform | CDNLive EMEA | Ericsson
Europractice and Cadence – A Long Fruitful Partnership

By Anton Klotz | 12 Jun 2019

Those who have studied microelectronics in Europe since 1989 have certainly heard about Europractice and have probably used EDA technologies provided by them. Though most refer to Europractice as an organization, it is actually an EU-funded project, ...

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Europractice | Cadence Academic Network | university program
Specman: Python Is here!

By teamspecman | 12 Jun 2019

Do you know from where Python technology gets its name? It is not from the snake, it is named after the Monty Python comedy group. And indeed, one of the main guidelines behind it is to be fun to use (check out the Zen of Python ). Therefore, Python...

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Specman/e | Python | Specman e | machine learning | specman elite
Paris Air Show

By Paul McLellan | 12 Jun 2019

Next week it is the Paris Air Show, the biggest trade show in aerospace and defense. Cadence will be attending for the first time. The show is held at Le Bourget Airport, which you've probably never heard of. Although it was Paris's first air...

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protium x1 | Aerospace | palladium z1 | Emulation | FPGA prototyping | paris air show
Whiteboard Wednesdays - Cadence Cloud - Fast, Painless, Proven Solutions for Cloud-Based Design

By Corrie Callenbach | 11 Jun 2019

In this week's Whiteboard Wednesdays video, Tom Hackett continues his discussion of the unique needs of different types of companies and introduces the specific Cadence® Cloud solutions designed to meet those needs. https://youtu.be/iTLy4sYQp1Q

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Whiteboard Wednesdays | Cloud-based Design | cadence cloud
IC Packagers: A Classic Revisited - Ball Map Spreadsheets

By Tyler | 11 Jun 2019

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google, and others are becoming more common in EDA, Cadence® SiP has had a great interface since early in the 16.6 release. You, our users, continue to find creative new use...

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APD | SiP Layout
BoardSurfers: Text Labels and Film Views Help Intelligent Designers

By Tyler | 11 Jun 2019

Last time, I talked about color and visibility as it relates to simplifying your design canvas display to make your work easier. Today, we take the next step forward: using your artwork films to drive what you see on screen, as well as dynamic text labels...

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APD | Allegro Package Designer | Allegro PCB Editor | SiP Layout
Making Trouble in Las Vegas

By Paul McLellan | 11 Jun 2019

For years John Cooley has organized what is called the Cooley's DAC Troublemaker Panel. This year, the participants (troublemakers?) were: Naveed Sherwani, CEO of SiFive (a RISC-V implementation company) Joe Costello of Montana (creati...

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DAC | troublemaker | 56dac
Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

By Parula | 10 Jun 2019

The first blog of the series talks about features that are not new but capabilities that are ground-breaking and can support your device-level routing requirements for advanced nodes with the use of the Finish Trunk command.

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Trunk Trimming | Pin to Trunk | Create Wire | space-based router | Virtuoso Space-based Router | layout XL | Layout Suite | Trunk Extending | Layout L | Finish Trunk | EM Trunk Optimization | Custom IC Design
Single-Stop Learning Resource for Cadence Low Power Simulation

By SumeetAggarwal | 10 Jun 2019

Since 2006, low power design has evolved from simple shut off and isolation to very advanced design techniques. This evolution is still in full force. The CPF language was introduced in 2005, and the UPF language was introduced in 2006. Cadence suppo...

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low power simulation | LPS | suppport | power