Cadence Blogs

升级到Allegro17.2-2016的10大理由之8：过孔结构——下一代高速布线解决方案

By TeamAllegro | 19 Oct 2018

过孔转换对信号布线来说十分常见。在高速设计中过孔转换是造成PCB互连中信号衰减的主要原因。而且高速通道需要地孔临近关键信号，在信号走线换层时，提供连续的回流路径，来降低信号损耗。（点击查看大图） space 如果您是一位PCB设计工程师，您会非常清楚，实现符合需求的布局布线很复杂、很花时间。现有的方法常常是手动的、冗长的，容易造成布局布线错误或丢失。我们很容易忘记在关键信号添加回流孔，或者移除关键信号走线之后遗留下的回流孔。此外，布线换层时，在高速差分对周围添加定制的过孔也是非常繁琐的手动过...

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PCB | SI | Chinese blog | Allegro 17.2 | PCB设计 | 差分对支持 | 中文 | 信号完整性 | Allegro升级17.2 | SI分析与建模 | 高速 | 差分对
How is a Multi-board PCB System Assembly Different from Rigid-Flex Assembly

By TeamAllegro | 19 Oct 2018

When people typically think of multi-board PCB design, they tend to picture racks of boards in server farms or the components of a gaming rig. But what if your typical rigid boards don’t fit within the physical envelope of your multi-board application...

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multi-board | multi-board systems | multiboard PCB | HighSpeed | multiboard | PCB design | multiboard systems | Allegro
The DARPA Electronic Resurgence Initiative (ERI)

By Paul McLellan | 19 Oct 2018

Many weeks ago DARPA organized a summit at the Palace of Fine Arts in San Francisco. The first day consisted of a workshop and some other presentations, including one by Cadence's Tom Beckley. Since Tom's presentation was very similar to what he...

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openroad | magestic | idea | posh | eri | darpa
Some Headlines that Caught My Eye

By MeeraC | 18 Oct 2018

Look around, look around at how lucky we are to be alive right now…—Lin-Manuel Miranda, Hamilton Every once in a while, I write a post like this one, to highlight some of the amazing things that are happening in the world of electroni...

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news | Headlines | Cadence on the Beat
Virtuoso IC6.1.8 and ICADVM18.1 Now Available

By Virtuoso Release Team | 18 Oct 2018

The IC6.1.8 and ICADVM18.1 production releases are now available for download. To find out what new and enhanced features do the releases bring, click here…

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Analog Design Environment | ICADVM18.1 | ADE Explorer | ADE | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Virtuoso: The Next Overture | Custom IC Design | Custom IC | IC6.1.8
CDNLive Israel 2018

By Paul McLellan | 18 Oct 2018

This week it was the last CDNLive of the year, CDNLive Israel in Tel Aviv. From my point of view the show ran perfectly. But I'm always reminded of that description of a swan as "serene on top and furiously paddling underneath." I reali...

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Jasper User Group 2018

By Paul McLellan | 17 Oct 2018

This week it is CDNLive Israel. But last week it was Jasper User Group (JUG). At it happens, Jasper was one of the early companies to sign up with SemiWiki when we started it, so I've been going to Jasper User Group for longer than either I'v...

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Jasper User Group | formal | formal signoff | JasperGold | Formal verification
What's in it for Me in Innovus 18.10 Release?

By MJ Cad | 16 Oct 2018

At advanced nodes, there’s always a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). You already know Innovus Implementation System very smartly delivers PPA advantage and accelerates digital design TAT through...

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Digital Implementation forums | Tempus | Release Page | Cadence Online Support | Digital Implementation | Innovus | full flow | blog
Of Arms and the Man I Sing

By Paul McLellan | 16 Oct 2018

Arma virumque cano—of arms and the man I sing. This is the famous opening line of Virgil's Aeneid, the curse of many a schoolboy's Latin learning days, mine included. Anyway, the reason for all this talk about arms (Arma) is that today is ...

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ARM Techcon | arm datacenter | hpe | xcelium | ARM | JasperGold | verification
Learn How Valens uses Specman Macros Automate Configuration of Verification Environments at DVCon EMEA Next Week

By Steve Brown | 16 Oct 2018

Valens has achieved success through applying Specman to their verification projects. At DVCon EMEA (Oct 24-25) you can learn how their use of Specman Macros to automate configuration of the verification environment to their design. This saves them effort...

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verification
Real World (Unexpected) Examples of Multi-Board PCB Systems

By TeamAllegro | 16 Oct 2018

What do reusable rockets, self-driving cars, and the blockchain have in common? Besides breaching major milestones in the last 3-5 years, they are all stellar examples of how advancements in multi-board printed circuit board (PCB) design is propelling...

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TAGS:

multi-board pcb system | multi-board | system architecture design | system level design | PCB system design | electronic system | system simulation | multiboard | system architect software | multiboard pcb system | elecronic system design
DDR5 Is on Our Doorstep

By Paul McLellan | 15 Oct 2018

The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the f...

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OIP | ddr5 | DDR4 | Micron | TSMC | DRAM
ESD Alliance Workshop on Digital Marketing: Tools and Sales

By Paul McLellan | 12 Oct 2018

Yesterday was the first part about the ESD Alliance Digital Marketing workshop. Today, it is part 2 (of 2). Nicolas Part 2: Training and Tools Today's marketers need to be hands-on since there are a lot of different aspects and it is too slow (no...

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digital marketing | onespin | esd alliance
Snapshots of CDNLive Taiwan 2018

By candyyu | 11 Oct 2018

Taiwan is one of the most important hubs for the global semiconductor industry. Served as an annual important event for Cadence in Taiwan, with the efforts to provide tailored lineups for local industry, this year’s CDNLive Taiwan has suc...

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CDNLive | cdnlive taiwan
升级到Allegro17.2-2016的10大理由之7：梯形凸块布线——下一代高速布线解决方案

By TeamAllegro | 11 Oct 2018

通过梯形凸块布线高效利用布线通道梯形凸块布线是一种新方法，可以通过在并行走线上添加梯形形状来控制引脚区域或者突破区域的阻抗，减少开放区域的串扰。这是一个突破性的布线策略，可应对更长、更密的布线。（点击查看大图）不幸的是，这一新的布线技术增加了PCB设计的复杂度，在后续的设计流程中管理这些梯形凸块也很痛苦。我们听到了你们的求助，PCB layout工程师欢欣鼓舞！除了提供生成梯形凸块的方法，我们覆盖了梯形凸块的整个“生命周期”，几大特性如下：生成梯...

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PCB | Chinese blog | Allegro 17.2 | 布线 | PCB设计 | 中文 | Allegro PCB Editor | Allegro PCB编辑器 | Allegro升级17.2 | 高速
Truck Platooning? 10-4, Good Buddy

By MeeraC | 11 Oct 2018

You know how, when geese are flying in a group, they form a V-shape? This is because of the slipstream in the air. Geese take turns being in the leadership position, and the other geese benefit from the reduced energy output required to make their mi...

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automotive | autonomous driving | platooning
ESD Alliance Workshop on Digital Marketing: Agility

By Paul McLellan | 11 Oct 2018

Last week the ESD Alliance ran another workshop on digital marketing, with Nicolas Athanasopoulos of OneSpin and Dave Kelf (now at Breker, but who used to work with Nicolas at OneSpin). Unfortunately, they picked the same day as TSMC's OIP sympos...

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digital marketing | onespin | esd alliance
NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

By PaulaJones | 10 Oct 2018

Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers...

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TAGS:

IP | IoT | HiFi | ip cores | Tensilica | semiconductor IP | Internet of Things
Azure for Silicon Design with Cadence and TSMC

By Paul McLellan | 10 Oct 2018

I used to live on the Cote d'Azur, which is what everyone else calls the French Riviera. The name comes from the blue color of the Mediterranean Sea, azur in French. In English, it is azure. But it is probably more well-known today as the name o...

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OIP | microsoft | TSMC | azure | cadence cloud
Whiteboard Wednesdays - Tensilica Neural Network Compiler: An Offline Tool for Efficient Deployment of Neural Networks

By References4U | 9 Oct 2018

In this week’s Whiteboard Wednesda ys video, Megha Daga describes how the Tensilica Neural Network Compiler works, from a trained floating - point network to an optimized source code generation for a Tensilica AI-enabled DSP or processor. https://youtu...

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DSP | Whiteboard Wednesdays | Tensilica | neural networks | AI
How To Maintain Connectivity in a Multiboard PCB System

By TeamAllegro | 9 Oct 2018

By John Burkhert Jr Bringing a multiboard system together is a chance for the designer to spread their wings. As the circuit spreads, so do the risk of crossed signals. Some of the ways the circuits can get scrambled include: Some connector vendors...

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PCB | allegro edm | multi-board | System-Level Design | Allegro PCB Designer Team Design Option | multiboard | system | PCB design | pcb system | Allegro
David White and Machine Learning

By Paul McLellan | 9 Oct 2018

Recently Cadence held a worldwide event for our interns. To read more about our intern program, see my post CHIPs in the Cadence Cafeteria . The number varies almost on a day-to-day basis, but when I wrote that post we had 259 interns at 13 different...

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artificial intelligence | machine learning | David White | neural networks
Improving Your Testbench Flexibility with Enhanced Specman Templates

By Steve Brown | 8 Oct 2018

Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible with the Open Verification Methodology (OVM)...

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Specman 18.09: Avoiding the Small Annoying Mistakes

By teamspecman | 8 Oct 2018

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article takes the small mistakes to the extreme and mentions...

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enumerator | Specman | Functional Verification | e | e language | specman elite | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Objects

By XTeam | 8 Oct 2018

Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This...

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TAGS:

performance | SystemVerilog | Functional Verification | xcelium simulator