Cadence Blogs

Celsius: Thermal and Electrical Analysis Together at Last

By Paul McLellan | 18 Sep 2019

Today at CDNLive Israel, Anirudh Devgan, Cadence's President, announced the Celsius Thermal Solver. This is Cadence's second product in the system analysis space, following on from the Clarity 3D Solver, announced at CDNLive Silicon Valley ea...

0 Comments

Tags:

celsius | CDNLive | system analysis | Thermal Analysis | cdnlive israel | electrical-thermal analysis
Taiwan National IC Design Competition

By Tracy Zhu | 17 Sep 2019

The Taiwan National IC Design Competition was a great opportunity for Cadence and the Academic Network to build our brand with students, connect with academia and attract top talent. This was the second year that we sponsored the ...

0 Comments

Tags:

Taiwan | Cadence Academic Network | academia | EDA
Announcing Celsius Thermal Solver: A New Approach to System-Level Thermal Analysis

By Corrie Callenbach | 17 Sep 2019

In this week's Whiteboard Wednesdays video, Be Gu introduces Celsius Thermal Solver, a new tool employing finite element analysis (FEA) techniques for thermal analysis of electronic systems. Ben explains how a novel architecture enables Celsius to deliver...

0 Comments

Tags:

celsius | Whiteboard Wednesdays | Thermal Analysis | finite element analysis | FEA
BoardSurfers: PCB Electronics - Defining and Applying Physical and Spacing Constraints

By mrigashira | 17 Sep 2019

If you get frequent calls from your fab houses or your customers regarding your product, or if your schematic, layout, and packaging engineers spend a lot of time exchanging notes about their requirements not being met, resulting in back and forth of...

0 Comments

Tags:

APD | PCB Editor | Constraint Manager
Upcoming Webinar: AI Accelerator Design with Stratus HLS

By dpursley | 17 Sep 2019

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine learning usage for Stratus HLS. In fact, this momentum started in 2017. Noting the increase in machine learning applications in our user base, we researched how to...

0 Comments

Tags:

High-Level Synthesis | webinars | TensorFlow | machine learning | Stratus | SystemC | HLS
PCIe Gen 4: It's Official, We're Compliant

By Paul McLellan | 17 Sep 2019

Way back in April 2016, I wrote a post about Cadence IP for PCI Express (PCIe) Gen4 where we demonstrated compliance with Mellanox (now part of NVIDIA). As Mellanox's Gilad Shainer said to me when I talked to him back then: interoperability...

0 Comments

Tags:

PCIe 4 | PCIe Gen4 | pcie 3
IC Packagers: Capture Your Design for Review

By Tyler | 17 Sep 2019

How do you quickly show another developer an issue that concerns you? Do you need to send them the entire design, start a screen sharing session, or bring up the Symphony server and allow them to connect? All of these are GREAT review mechanisms; however...

0 Comments

Tags:

APD | SiP Layout
Academic Network Engaging with National Taiwan University

By Tracy Zhu | 16 Sep 2019

The National Taiwan University hosted an EDA summer camp for the third consecutive year! Since “EDA" is an unfamiliar concept for many students, the  Graduate Institute of Electronics Engineering National Taiwan University (NTU GIEE) and&nb...

0 Comments

Tags:

university | Student Day | Taiwan | Cadence Academic Network | academia | university program
MLPerf: Benchmarking Machine Learning

By Paul McLellan | 16 Sep 2019

Most presentations at the recent HOT CHIPS conference are about actual chips, mostly processors of one kind or another. But in machine learning, there is a need to be able to compare these processors. This is where MLPerf comes in, putting together a...

0 Comments
Virtuosity: Layout Reuse Flow in Modgen

By Aneesh Shastry | 15 Sep 2019

Modgen now supports the Layout Reuse Flow. Read on to see how you can use this feature to boost your layout productivity by reducing the time and effort to create Modgen.

0 Comments

Tags:

Modgen On Canvas | ICADVM18.1 | MODGEN | Virtuoso | Virtuosity | Custom IC Design | modgens | Virtuoso Layout Suite | Custom IC
DATA Pulse: Track Your Components—Efficient Library and Design Data Management

By Auromala | 15 Sep 2019

Ever noticed how some objects always mysteriously disappear? It's like they have their own legs. Or maybe, secretly, they thirst for adventure and go wandering off. Socks for example. Why does one twin always disappear after a round in the washing machine...

0 Comments

Tags:

lifecycle | RAK | Allegro
Sunday Brunch Video for 15th September 2019

By Paul McLellan | 15 Sep 2019

https://youtu.be/bcAO52jxk10 Made at SFO (camera Carey Guo) Monday: HOT CHIPS: In-DRAM Compute Tuesday: CDNLive India 2019: NXP and More Wednesday: EDPS Preview 2019 Thursday: Intelligent Systems Friday: Intelligent System Design www.breakf...

0 Comments

Tags:

sunday brunch
Ken的博客系列之六 | 千兆位串行链路接口的SI方法

By Sigrity | 13 Sep 2019

作者：Ken Willis 上一篇：高效的互连提取使用IBIS-AMI模型进行仿真此时，SerDes元器件供应商应该已经提供了所需的IBIS-AMI模型，如果这些模型可用，那么替换仿真测试平台中的对应模型。现在，我们重点关注后仿真的验证工作。在仿真测试平台中替换为你自己的模型，尽管这时看起来你好像就马上可以进行仿真工作了，但是对于IBIS-AMI模型仍然有许多工作需要做。如前所述，算法部分或者IBIS-AMI模型的“AMI”部分为SerDes的均衡功能。在双沿数据速...

0 Comments

Tags:

PCB | SI | Chinese blog | ddr5 | 仿真分析 | DDR4 | equalization | IBIS-AMI | 中文 | SerDes | Sigrity | SystemSI | 信号完整性
Intelligent System Design

By Paul McLellan | 13 Sep 2019

Yesterday in my post Intelligent Systems , I wrote about how the imperative for differentiated products, especially at the high end of markets, is pushing both system and semiconductor companies to take a more holistic view of system design. Cadence...

0 Comments

Tags:

system analysis | pervasive intelligence | design excellence | intelligent system design | system innovation
Intelligent Systems

By Paul McLellan | 12 Sep 2019

Cadence's goal is to empower engineers at semiconductor and systems companies to create innovative, intelligent, and highly differentiated electronic products that transform the way people live, work, and play. One big change is for system companies...

0 Comments

Tags:

intelligent system design
Safety and Aging in IoT Devices: What We Know Today

By XTeam | 11 Sep 2019

How do we achieve highly accurate aging data models for critical circuits in automotive or IoT applications? IoT device aging isn’t well understood yet, since most of it is still so new. How will the software stand up against tomorrow’s t...

0 Comments

Tags:

iot devices | DAC 2019 | aging | GlobalFoundries
EDPS Preview 2019

By Paul McLellan | 11 Sep 2019

EDPS, the Electronic Design Process Symposium, is coming up next Monday. It will be on Thursday, October 3 and Friday, October 4. Once again it will be held at SEMI's offices in Milpitas. I think of it as Gary Smith's conference, since he was al...

0 Comments

Tags:

deep learning | 3DIC | EDPS | more than Moore | AI
How to Land a Job at Cadence: Recruiters Share Their Best Tips for Standing Out and Getting an Interview

By Ashley Sneathen | 10 Sep 2019

As we send off the last of our 2019 Summer Interns ( read more about their experience here ) and say goodbye to summer, our recruiting team is already turning their attention to finding the next group of college hires and interns to join the Cadence te...

0 Comments

Tags:

intern | Student | internship
IC Packagers: How Far Away are You?

By Tyler | 10 Sep 2019

Layout design is all about clearances. Daily challenges come from maintaining consistent space between your differential pair members, calculating the number of routing channels you can squeeze between two vias, or ensuring adequate clearance of bond...

0 Comments

Tags:

SiP Layout
BoardSurfers: PCB Electronics - Electrical Constraints

By mrigashira | 10 Sep 2019

Whether it's NASA's space missions or a school camping trip; building a cutting-edge, reusable rocket system or baking a simple lemon tart - planning is a must to avoid disasters, or at least to get a predictable output. So is the case with PCBs. You...

0 Comments

Tags:

Constraint Manager | Allegro Package Designer | Allegro PCB Editor | SiP Layout
Virtuoso IC6.1.8 ISR6 and ICADVM18.1 ISR6 Now Available

By Virtuoso Release Team | 10 Sep 2019

The IC6.1.8 ISR6 and ICADVM18.1 ISR6 production releases are now available for download.

0 Comments

Tags:

Analog Design Environment | Cadence blogs | ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | Automated Device-Level Placement and Routing | Automatic Placement | Interactive and Assisted Routing | IC Release Announcement blog | Virtuoso RF | Layout EXL | ADE | Mixed-Signal | Layout | Virtuoso | advanced nodes | New in EDA | Virtuoso EM Solver | Custom IC Design | Virtuoso Layout Suite | Custom IC | ADE Verifier | IC6.1.8 | ADE Assembler
CDNLive India 2019: NXP and More

By Paul McLellan | 10 Sep 2019

Last week I covered Day 1 of CDNLive India . Today it is the turn of verification and PCB/system. With a digression to India's unusual time zone. Day 2 On Thursday, August 29, there were tracks for Advanced Verification Methodology, Performan...

0 Comments

Tags:

NXP | CDNLive India | CDNLive
Virtuoso Meets Maxwell: Add Some MAGic to Your ElectroMAGnetic Analysis

By kfullerton | 9 Sep 2019

If you’ve ever seen a great magician at work, you know that their talent lies in making the impossible look easy. That’s what we have done with Electromagnetic (EM) Analysis in the Virtuoso RF Solution. If you have struggled with cumbersome EM integrations...

0 Comments

Tags:

ICADVM18.1 | Virtuoso New Design Platform | video | Virtuoso Meets Maxwell | Virtuoso RF | Electromagnetic analysis | EM Analyis | RF design | Custom IC Design | Virtuoso Layout Suite
HOT CHIPS: In-DRAM Compute

By Paul McLellan | 9 Sep 2019

Something that has been discussed for years is the fact that we could add processors to DRAM memory pretty cheaply if we could work out what to do with them. Usually, when people suggest this, they don't really think it through. They are assuming...

0 Comments

Tags:

pim | hot chips | processor in memory
Dimensions to Verifying a USB4 Design

By Neelabh | 8 Sep 2019

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router....

0 Comments

Tags:

Verification IP | Router | DisplayPort | USB | usb4 | PCIe | USB3 | tunneling