Blogs

At 11:10am Korean time this morning, Cadence's Elias Fallon delivered one of the keynotes at ISOCC (International System On Chip Conference). It was titled EDA and Machine Learning: The Next Leap in Semiconductor Design and Productivity. He ...

The low-power format, CPF/UPF/IEEE1801, has been very popular in the digital simulation world for over ten years. Nowadays, it is also commonly used in the mixed-signal simulations.

Arm's Shawn Hung (based in Austin) and Cadence's Rod Metcalfe presented on doing 3D design at Arm DevSummit, in a presentation titled Implementing 3D Neoverse N1: 3D Design Merits Meet In-Depth Analysis. What they described was...

デザインから寄生素子を抽出してDSPFファイルを作成し、そのDSPFファイルを使用して Virtuoso® ADE Assembler もしくは Virtuoso® ADE Explorer からシミュレーションを実行すると、全ての評価式が計算されない、という問題が昔から存在していました。この原因は、DSPFファイルではデザインがフラットであることに加え、抽出ツールによる素子名へのプレフィックスの追加、フィンガーデリミタの変更、ネット名の大小文字の変更などが行われていることがあるためで...

We’re concluding the Online Training Deep Dive blog series, which has been taking the top 15 Online Training courses among students and professors and breaking them down into their different technical areas and sharing the supporting ...

All components on a Printed Circuit Board (PCB) layout will have a footprint. A footprint is where your component gets soldered on the PCB. These footprints need to be extremely accurate so that your PCB can be properly assembled at the time of manufacturing...

CadenceLIVE India gives out a best paper award on each track to the presentation that the attendees vote as the best. Over at The India Circuit Blog, Sangram Jena provides a table with all the winners . I took a look at three of the winners in three d...

This blog is in continuation with the post on the IR-Aware placement technology that is used at the early design stage to mitigate IR drop hotspots and ease final signoff. The second part of this blog discusses targeted PG stripes addition, another IR...

When you are placing components (or defining your BGA pattern), often it is necessary to escape each of those pins to a given internal layer. This could be to get your power and ground supply to the designated plane layer. Or, it might be the first s...

Arm has a program with four teenagers known as Gen Arm 2Z Ambassadors. They appeared on a panel session at the recent Arm DevSummit. Since it was virtual, they never appeared on screen together. But as it happens, they were on stage with Simon S...

Sometimes, you attend an event and it feels like you are present at the start of a new era that will change some aspect of the technology industry. Of course, things don't change overnight. One event I remember from the last decade were hearing ...

让我们一起探讨如何在Virtuoso中实现版图封装设计，在封装中如何处理接地平面，已经如何快速整洁的进行封装布线。

We’re proud to see that many expert verification teams exploit the powers of UVM vr_ad, in implementing intricate verification environments in e . The vr_ad is an open source package, part of UVM- e . It provides means to access the DUT registers and...

https://youtu.be/-e-scl8tg8A Made in front of my TV Monday: Arm and NVIDIA: Simon Segars and Jensen Huang Tuesday: System VIP: Logistics for Cache-Coherent Multiprocessor Systems Wednesday: Electromagnetic Compliance: Anechoic Chamber ...

要按时设计一个优化的电源和一个没有板级 SI/PI 问题的 PCB 设计需要设计师、layout 工程师和 PI 工程师通过一个集成设计平台紧密合作。 面向团队的设计流程允许设计和 layout 工程师在设计周期早期执行基本的电源完整性 (PI) 分析，同时不会给 PI 工程师带来过多的负担，从而加快上市时间并优化最终的设计成本。 PCB 设计流程中的传统角色 通常，PCB 设计流程中的三个主要角色都负责确保 PCB 的电源完整性： 设计工程师负责生成物料清单 (BOM) 和电路原理图来启动流...

At the Arm DevSummit, there were several presentations on the first day about EDA on Graviton. Graviton is an Arm-architecture chip developed by AWS (in its Annapurna Labs group). There was an original version, now known as Graviton 1, a couple of ye...

カスタマイズはとても重要です。アイスクリームの選択からプレミアムカーの装備まで、我々は必要または希望に応じたプロダクトのカスタマイズを求めています。 Virtuoso ユーザも例外ではありません。 ユーザは各機能をコントロールする変数の値を変更することにより、Virtuoso環境のいろいろな機能をカスタマイズできます。これらの変数は各Virtuosoのリリースと一緒に提供される複数の.cdsenvファイルに保存され、Virtuosoの外観または動作を定義します。 これまでの環境設定方法 cdse...

If you’re looking for an example of how well the Cadence flow fits together, look no further than Renesas and their experience using the Cadence System Testbench Generator and System Performance Analyzer alongside Perspec and Palladium. With development...

In the process of developing a PCB design, a multitude of experts are involved in the verification of the design. These experts and various other stakeholders can be from your own company or from your manufacturer and they will be interested in parti...

Are you curious to know about the recent developments in Voltus-Fi? Then, check out these five latest features of Voltus-Fi and see how they are working for you.

For Hispanic Americans and Latino Americans, the American dream is more than just a phrase, it is a guiding light and a goal to be achieved based on the belief that if you work hard there isn’t a single thing you can’t accomplish in thi...

EDA tools have a primary challenge: to be good at whatever it is they do. They have a second challenge, which is to get support from the rest of the ecosystem, such as synthesis libraries (yeah, I used to be at Ambit Design Systems). But signoff tool...

Following on from my last blog about the Cadence Scholarship Program, here is the second inspiring story featuring one of our students - Mousumi Ghorai. The Cadence Scholarship Program A few words about the Cadence Scholarship Program, in case you mi...

Yesterday, I reported on Paul Cunningham's announcement of a new product, System VIP, in my post System VIP: Logistics for Cache-Coherent Systems . A few minutes later Paul announced a second product, the Clarity 3D Transient Solver. This is the...

The shift to heterogeneous integration of module designs implies a transition from PCB-styled flows and methodologies towards IC-styled flows. Cross-fabric design and verification methodologies for multi-die packages have become indispensable parts of...