Cadence Blogs

Sunday Brunch Video for 17th February 2019

By Paul McLellan | 17 Feb 2019

https://youtu.be/ZuoAfBXsbGw Made in front of the green screen (camera Sean) Monday: SPIE 2019: Light Entertainment Tuesday: DVCon Preview: The Year of PSS Wednesday: MWC Barcelona: 5G in Catalonia Thursday: Embedded in Nuremberg Friday: Presidents&#...

0 Comments

TAGS:

MWC | mwc barcelona | DVcon | SPIE | Embedded World | embeddedworld
Presidents' Day Off-Topic: Why You Can't Say "Red Little Riding Hood"

By Paul McLellan | 15 Feb 2019

Monday is Presidents' Day, and Cadence (in the US) will be off for the day. Breakfast Bytes will be off too, and as is now traditional, the post before the break is about whatever I feel like. Today, some obscurities about English that you probab...

0 Comments

TAGS:

spelling | off topic | language
Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct

By NamrataM | 14 Feb 2019

Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations...

0 Comments

TAGS:

electromigration | ICADV12.3 | ICADVM18.1 | EM/IR | Layout Suite | IC6.1.7 | EM | electrically-aware design | IR drop | IC6.1.8
Embedded in Nuremberg

By Paul McLellan | 14 Feb 2019

The last week of February is Embedded World (or, in fact, embeddedworld since they fashionably use all lower case). It is 26th to 28th February in the Exhibition Center. It is the same week as MWC Barcelona, DVCon (San Jose), and SPIE Advanced Lithog...

0 Comments

TAGS:

automotive | Nuremberg | Embedded World
MWC Barcelona: 5G in Catalonia

By Paul McLellan | 13 Feb 2019

The last week of February is MWC Barcelona, formerly known as Mobile World Congress but now officially just initials. It is, obviously, in Barcelona, Spain. If you are in Germany, or Silicon Valley, other conferences are available! That week is ...

0 Comments

TAGS:

5G | Mobile World Congress | MWC | mwc barcelona | mobile
DVCon Preview: The Year of PSS

By Paul McLellan | 12 Feb 2019

The biggest conference on verification is DVCon, which takes place in the San Jose Doubletree Hotel from 25th to the 28th February (yes, the same week as SPIE...and Embedded World...and Mobile World Congress). Verification covers all of simulation, e...

0 Comments

TAGS:

Perspec | formal | Protium | Palladium | Emulation | DVcon | data-driven verification | xcelium | pss | JasperGold | verification
SPIE 2019: Light Entertainment

By Paul McLellan | 11 Feb 2019

SPIE is the international society for optics and photonics, with the purpose of “advancing an interdisciplinary approach to the science and application of light”. What everyone calls "spie" (pronounced "spy"), however,...

0 Comments

TAGS:

lithography | SPIE | EUV
Sunday Brunch Video for 10th February 2019

By Paul McLellan | 10 Feb 2019

https://youtu.be/evsNzak23b4 Made at Cadence basketball court (camera Sean) Monday: DesignCon: Cadence Teaches AMI and IBIS Tuesday: Emerging Memories Poised to Explode Wednesday: DesignCon 2019 Thursday: 60 Years of DARPA—61 Actually...

0 Comments

TAGS:

crypto | DesignCon | persistent memories | emerging memories | darpa
机械、热、SI、PI 、EMI分析：PCB设计缺一不可

By SpbChina | 8 Feb 2019

本文翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章 "Mechanical, Thermal, EMI, SI, PI: PCB Design Needs Them All" 。 space An-Yu Kuo博士曾经在Cadence CDNLive以色列分会场的开幕演讲上讨论过 “PCB设计与分析中弥合电气、机械等领域之间的差距” 主题。现如今，PCB设计与分析涵盖更多领域：电磁学...

0 Comments

TAGS:

SI | Chinese blog | 热分析 | EMI | 机械设计 | PCB设计 | 中文 | Sigrity | 信号完整性 | Allegro
Will Crypto Change the World?

By Paul McLellan | 8 Feb 2019

Do you remember when you had to pay for ringtones? In 2005, analysts were predicting that ringtones would be a $10+B market by 2010. In that pre-smartphone era, you could only install a ringtone if your service provider gave you permission. You had t...

0 Comments

TAGS:

crypto | Internet | mobile | blockchain
Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design

By Hiro Ishikawa | 7 Feb 2019

How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.

0 Comments

TAGS:

Analog Design Environment | Virtuoso New Design Platform | Physical placement and layout | Advanced Node | Virtuoso | Custom IC Design
Simulation for a Song: Downloading Models from the Web and Associating with Parts for PSpice Simulation

By mrigashira | 7 Feb 2019

While on a long drive, I like to sing along; say Eye of the Tiger or Johny B Goode or Sweet Home Alabama (even though I don’t live in Alabama), the music being an active part of the journey, especially when I am just beginning the drive, fresh and...

0 Comments

TAGS:

capture | Models | PSPICE | OrCAD | simulation
Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!

By Rashmi G | 7 Feb 2019

Cutting-edge innovation … Top-down planning … Reliable and formalized verification … Scalable performance ! These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the...

0 Comments

TAGS:

verifier | PVT | ICADVM18.1 | custom/analog | Formalized Verification | Analog Simulation | ADE | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | space | Custom IC Design | ADE Verifier | IC6.1.8 | ADE Assembler | verification
60 Years of DARPA—61 Actually

By Paul McLellan | 7 Feb 2019

On 4th August 1957, the Soviet Union launched the first artificial satellite, Sputnik 1 ("sputnik" means "satellite" in Russian). It wasn't very impressive by modern standards, a 23" metal sphere with 4 radio antennas. It seems that President Eisenho...

0 Comments

TAGS:

Aerospace | magestic | arpa | space | eri | darpa | chips
Virtuosity: Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

By Virtuoso Release Team | 6 Feb 2019

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download.

0 Comments

TAGS:

Analog Design Environment | ICADVM18.1 | ADE Explorer | Virtuoso Space-based Router | ADE | Layout | Virtuoso | cadenceblogs | IC Release Blog | New in EDA | Virtuoso: The Next Overture | Custom IC Design | Virtuoso Layout Suite | Custom IC | IC6.1.8
DesignCon 2019

By Paul McLellan | 6 Feb 2019

It doesn't seem to matter what a show is ostensibly about at the moment. Every show seems to be talk about quantum computing, 5G, or artificial intelligence (AI). DesignCon, the focus of which is PCB design, was no exception, with three keynotes on....

0 Comments

TAGS:

uber | DesignCon | AMI | IBIS | 112g | photonics
Virtuosity: 如何使用ADE Explorer 及ADE Assembler 打开旧版本的ADE 状态和视图文件

By NamrataM | 5 Feb 2019

您是否发现，当您查看 Virtuoso ® ADE L 状态（State）文件，或者 Virtuoso ® ADE XL 视图 (View) 文件时，默认打开程序仍然是旧版本的 ADE L 或者XL? 如果您已经移动至 Virtuoso ® ADE Assembler 或者 Virtuoso ® ADE Explorer ，那么需要打开文件，在 Open File 对话框下，找到应用程序这栏，并将其更改为...

0 Comments

TAGS:

Chinese blog | Analog Design Environment | Virtuoso ICADVM18.1 | ICADVM18.1 | ADE Explorer | ADE Migration | maestro | ADE | Virtuoso IC6.1.8 | Virtuoso ADE Explorer | Virtuoso ADE Assembler | IC6.1.8 | ADE Assembler
Emerging Memories Poised to Explode

By Paul McLellan | 5 Feb 2019

A couple of weeks ago was the Persistent Memory Summit. (For more details, see my post Persistent Memory .) Normally, this might be a minority-interest event, but the potential arrival of a new level in the memory/storage hierarchy means that everyone...

0 Comments

TAGS:

fram | ReRAM | flash | xpoint | 3D NAND | NAND flash | emerging memories | DRAM | nor flash | MRAM | PCRAM
DesignCon: Cadence Teaches AMI and IBIS

By Paul McLellan | 4 Feb 2019

At the recent DesignCon, Cadence and customer IBM presented a tutorial on Advanced IBIS-AMI Techniques for 32 GT/s and Beyond. If you are not well-versed in SerDes and signal integrity, your first need for a tutorial might be to explai...

0 Comments

TAGS:

DesignCon | AMI | IBIS | SerDes
2019七大行业动向预测

By SpbChina | 3 Feb 2019

本文翻译自Cadence “Breakfast Bytes”专栏作者Paul McLellan文章 “ Breakfast Nibbles: Predictions for 2019 "。新年伊始，我来和大家聊聊我眼中的2019年业内主题趋势。内存价格 2018年，整个半导体市场非常强劲，其中很大一部分原因是内存市场尤其是DRAM市场的需求远大于现有产能。而随着额外产能的上线，关注内存市场的人无一不认为其价格将会发生下滑（更多详细内容，请阅读 &qu...

0 Comments

TAGS:

5G | Chinese blog | 内存 | 无人车 | 3nm | 电动车 | DRAM | 中文 | 汽车 | 云 | 5nm | 神经网络 | AI | EUV
Sunday Brunch Video for 3rd February 2019

By Paul McLellan | 3 Feb 2019

https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM: Embedded Memories Tuesday: CES: 5G, All Hat and No Cattle Wednesday: Persistent Memory Thursday: What Next for Modus DFT? Friday: Programming Persistent Memory www...

0 Comments

TAGS:

5G | DFT | Memory | CES | modus | mobile | persistent memory | IEDM
Programming Persistent Memory

By Paul McLellan | 1 Feb 2019

I talked earlier this week about the recent persistent memory summit (see my post Persistent Memory ). If DRAM gets faster or higher capacity, then there isn't anything that software engineers need to change, whether they're writing the operating syst...

0 Comments

TAGS:

programming model | persistent memory
Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

By Yagya Mishra | 31 Jan 2019

An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE...

0 Comments

TAGS:

verifier | PVT | coverage | Analog Coverage | Analog Simulation | Virtuoso Analog Design Environment | space | Custom IC Design | Assembler | verification
What Next for Modus DFT?

By Paul McLellan | 30 Jan 2019

I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the same glory as the more high profile parts of the EDA flow such as synthesis, or place & route, or signoff. Test History Over the years, how we do test has...

0 Comments

TAGS:

modus | Test | scantest
Persistent Memory

By Paul McLellan | 30 Jan 2019

Last week was the latest Persistent Memory Summit. In the semiconductor world, we don't usually use that word, we say non-volatile memory. In practice, this mostly means flash memory (mainly 3D NAND today) and embedded flash memory (eFlash). Both...

0 Comments

TAGS:

persistence | Intel | non-volatile | persistent memory summit | ReRAM | optane | MRAM | persistent memory | 3dxpoint