Cadence Blogs

Whiteboard Wednesdays – What is Happening at the USB IF Standards Meetings?

By Corrie Callenbach | 16 Jul 2019

In this week’s Whiteboard Wednesdays video, Jacek Duda talks about the next-generation standard, USB4. What are the benefits? Overlap with existing USB standards? How does it compare with USB 3.x? Watch the video. https://youtu.be/sKHF8xB-NBk

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Whiteboard Wednesdays | USB
IC Packagers: Bend in Both Directions with J-Loop Bond Wires

By Tyler | 16 Jul 2019

Let’s talk about wire bonding for a quick minute. Still a favorite for many of you, bonding is a cheap way to connect your die to the top layer of your package (or to a lead frame, if that’s what you’re using). A 3D wire is connecte...

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IC Packaging | APD | SiP Layout
GLOBALFOUNDRIES After the Pivot

By Paul McLellan | 16 Jul 2019

At SEMICON West I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to get an update on what is going on since the “pivot”. The Pivot The pivot was the decision last year to pull back from 7nm and EUV development and focus their process ...

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globalfound | semicon | 22fdx | 12fdx | FD-SOI
Cadence and the Expanding Presence of Women in Tech Conferences

By MeeraC | 15 Jul 2019

Cadence sponsors several different tech conferences throughout the year. We use these events as an opportunity to allow employees to take a day out of our normal work routine to network, learn, and develop as leaders—but more importantly, so we...

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Insights on Culture | Culture | STEM | IEEE WIE ILC | women | VerveCon | diversity
Is the Role of Test Chips Changing at Advanced Foundry Nodes?

By TomWong | 15 Jul 2019

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm...

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Design IP | IP | cadence | PCIe Gen4 | IP integration | ip cores | Ethernet | semiconductor IP | PCI Express
Will American Scooters Follow Chinese Bikes?

By Paul McLellan | 15 Jul 2019

I spent the July 4 weekend in San Diego. My public service announcement is that if you go to San Diego, the first thing you should do is buy a week pass to all the museums in Balboa Park, and add on a discount admission to the zoo if you plan to...

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automotive | scooter | app | smarphone | bike
Virtuoso Meets Maxwell: Learn Your Moves – We’re Doing an Edit-in-Concert

By Steve PDK Lee | 14 Jul 2019

This blog showcases the Edit-in-Concert technology available in the Cadence Virtuoso RF Solution, which lets designers view and edit die packages and their corresponding die layouts synchronously.

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Edit-in-Concert | Virtuoso Meets Maxwell | Advanced Node | Virtuoso RF | Virtuoso | Custom IC Design
How to Verify Performance of Complex Interconnect-Based Designs?

By Thierry Berdah | 14 Jul 2019

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices....

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Verification IP | Interconnect Workbench | Interconnect Validator | SoC | Performance modeling | AMBA | ATP | ARM | System Verification
Sunday Brunch Video for 14th July 2019

By Paul McLellan | 14 Jul 2019

https://youtu.be/HO3cViPU6Mw Made at Slovensky Raj, Slovakia (camera Gary Bengier) Monday: Carry: From Logarithms to Mechanical Calculators Tuesday: Carry: Babbage's Engines Wednesday: Carry: Electronics Thursday: NXP: Can Silicon Valley Rea.....

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sunday brunch
The Mercedes Benz Museum and the Invention of the Automobile

By Paul McLellan | 12 Jul 2019

Recently, I was in Stuggart, Germany. This is the home to the headquarters of both Daimler-Benz (or Daimler-Chrysler as it now is) and also Porsche. Both companies have fascinating museums. The thing that makes them especially interesting is that so...

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automotive | mercedes benz
Cadence LPDDR4设计IP通过TSMC 16FFC FinFET 车规工艺验证

By Sigrity | 12 Jul 2019

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“ Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC ”。 space 今年4月份，Cadence宣布其LPDDR4/4X存储器IP子系统通过ISO 26262 ASIL C认证： “楷登电子（Cadence公司，NASDAQ：CDNS）今日宣布，采用TSMC16nm FinFET Com...

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PCB | SI | Chinese blog | 仿真分析 | LPDDR4 | 中文 | Sigrity | 信号完整性
Virtuosity: Device-Level Routing for Advanced Nodes – Using Generate Trunks

By Parula | 12 Jul 2019

The Trunk Generation feature is the founding piece that offers incremental productivity improvement with automation over Pin to Trunk, while still providing all the customizable options in the Pin to Trunk flow.

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Trunk generation | Interactive Routing | Pin to Trunk | ICADVM18.1 | Virtuoso Space-based Router | Layout EXL | Layout Suite | trunk creation | Virtuoso | Generate Trunk | EM Trunk Optimization | Custom IC Design | space based router | Virtuoso Layout Suite | Custom IC
NXP: Can Silicon Valley Really Crack the Automakers' Code?

By Paul McLellan | 11 Jul 2019

The second panel at the recent NXPConnect was about Silicon Valley versus traditional carmakers (OEMs in car industry terminology). The first panel I covered recently in NXP: Self-Driving Cars: What's the Payoff for Carmakers? Can Silicon Va...

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automotive | NXP | ADAS
Virtuosity: 过滤波形

By Arja H | 11 Jul 2019

在接下来的几周内，Virtuosity和Virtuoso Video Diary博客将重点关注 Virtuoso®ADE Assembler , Virtuoso®ADE Explorer 和 Virtuoso® Visualization and Analysis 中刚刚发布的功能。因为我们有很多有趣的新增强改进和功能可供讨论，我们将在每周的周二和周四各发布一次博客。今天的博客是ADE迷你博客系列的第二篇。本博客将重点介绍现在可用于Virtuoso® Visualiz...

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Chinese blog | ADE Explorer | plotting | plot | Filtering | ViVA | Virtuosity | ADE Blog Series | Custom IC Design | ADE Assembler
Carry: Electronics

By Paul McLellan | 10 Jul 2019

The last two days I have written about carry in mechanical calculating devices. See my posts Carry: From Logarithms to Mechanical Calculators and Carry: Babbage's Engines . We have similar problems in designing electronics. Most microprocesso...

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carry | adder
Whiteboard Wednesdays - Cloud-Hosted Design Solution – a Full-Service Cloud Offering

By Corrie Callenbach | 9 Jul 2019

In this week's Whiteboard Wednesdays video, Jeff Critten describes the key benefits of the Cadence® Cloud-Hosted Design Solution in providing a total solution for companies seeking to move entire electronic design projects to the cloud. https://youtu...

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Cloud-Hosted Design | Whiteboard Wednesdays | cadence cloud
AMBA Adaptive Traffic Profiles: Addressing The Challenge

By DimitryP | 9 Jul 2019

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving. With increased number of SoC components...

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Adaptive Traffic Profiles | Performance modeling | AMBA | ATP
BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture Phase

By mrigashira | 9 Jul 2019

View the footprints of symbols during design entry in Capture: verify the footprint and land pattern dimension before exporting your design to a board layout tool, such as PCB Editor,

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Capture CIS | PCB Editor | footprint viewer
IC Packagers: Balance Your Designs with Cadence SiP Layout

By Tyler | 9 Jul 2019

As designs get more complicated, package substrates are seeing more silicon-driven rules and structures. Substrate styles like fan-out wafer level packaging (FOWLP) and elements such as through-silicon vias (TSVs) being injected into the package lay....

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IC Packaging | APD | SiP Layout
Carry: Babbage's Engines

By Paul McLellan | 9 Jul 2019

Yesterday's post Carry: From Logarithms to Mechanical Calculators talked about how carrying was done in the mechanical and electromechanical calculators of my youth. The most famous mechanical calculators ever designed have to be Charles Ba...

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carry | analytical engine | difference engine | Babbage
Virtuoso视频日记：创建和预览激励

By Arja H | 8 Jul 2019

在接下来的几周内，Virtuosity和Virtuoso视频日记博客将重点关注 Virtuoso® ADE Assembler , Virtuoso® ADE Explorer , 和 Virtuoso® Visualization and Analysis 中刚刚发布的功能。因为我们有很多有趣新的功能和改进可以分享给您，我们将在每周的周二和周四发布。今天的博客是ADE迷你博客系列的第一篇。本博客将重点介绍我们推出的新表单，以帮助您的设计创造激励。请继续关注更多有趣的ADE...

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Chinese blog | ADE Explorer | stimuli form | stimuli | Virtuoso Analog Design Environment | ViVA | Virtuosity | ADE Blog Series | Custom IC Design | ADE Assembler
Carry: From Logarithms to Mechanical Calculators

By Paul McLellan | 8 Jul 2019

I hope you had a great July 4th long weekend if you are in the US...and if you were elsewhere I hope you at least had a good short weekend. Today is the first of three posts on "carry", in the sense you first learned in primary school, whe...

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carry | ripple carry
Sunday Brunch Video for 7th July 2019

By Paul McLellan | 7 Jul 2019

https://youtu.be/re7U6Rg0MHA Made at Cadence charge station (camera Sean) Monday: NXP: Self-Driving Cars: What's the Payoff for Carmakers? Tuesday: It's Beyond HOT at ES Design West Next Week Wednesday: Off-topic: Geography Thursda...

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sunday brunch
IC Packagers: Vary Your Assembled Packages, Not Your Databases

By Tyler | 3 Jul 2019

Design variants are a common phenomenon, whether you design package substrates or PCBs. You may source a resistor from multiple vendors, and part of the design flow includes generating a bill of materials (BoM) which lists all the parts that go on a ...

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IC Packaging | APD | SiP Layout
Off-topic: Geography

By Paul McLellan | 3 Jul 2019

It's the day before a holiday so Breakfast Bytes goes completely off-topic as usual. Last time, the Friday before Memorial Day, we went with figures of speech. This time, let's go with maps and geography. Let's see how good your sense of ...

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offtopic