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Corporate News

Fortune & Great Place To Work Name Cadence to 2025 World’s Best Workplaces List

Great Place To Work® and Fortune magazine have honored Cadence as one of the Fortune…

Corporate
• 2 min read
news story , Culture , featured

Corporate News

Spectre FX Simulator Cuts Intrinsic Semi’s Memory Verification Time by 4X

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry…

Corporate
• 2 min read
newstory , featured , spectre fx , Instrinsic Semi , verification

Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

Corporate
• 1 min read
featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY
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Blog - Post List
Latest blogs

Digital Design

Accelerating Silicon Success with Cadence’s Digital Full Flow

Cadence's Digital Full Flow delivers RTL-to-GDSII convergence with industry-leading…

• 1 min read
training , Cadence Cerebrus Intelligent Chip Explorer , digital full flow

SoC and IP

Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard

Modern compute systems have evolved beyond reliance on a single dominant interface…

• 2 min read
Design IP , PHY , AI Inferencing , 25G Ethernet , Edge Computing , 10G-KR , PCIe 5.0 , Ethernet , PCIe , SerDes , SerDes IP , Concurrent Multi-protocol Support , Multi-link , multi-protocol , AI

System, PCB, & Package Design 

BoardSurfers: Training Insights: Automating Artwork Configuration in PCB Editor

The Artwork Configuration feature of Allegro X PCB Editor in Release 24.1 automates…

• 3 min read
PCB Design Automation , Gerber file creation , PCB Editor Workflow , Allegro X PCB Editor , artwork , Automating PCB Artwork , Allegro PCB Editor , artwork film workflow , artwork film generation , Cadence Allegro Training , Film Generation in PCB , Allegro , film setup in Allegro X

Life at Cadence

Empowering the Next Generation of Engineers: UKESF Student Bursary Event 2025

Electronics lies at the heart of today's technological revolution, fuelling innovation…

• 3 min read
STEM , Cadence UK , Cadence Cares , giving back , volunteer

Cloud

Revolutionizing Chip Design in the Cloud

Cadence OnCloud Managed Cloud Service In today's fast-paced semiconductor industry…

• 1 min read
Managed Cloud , EDA , cloud , cadence cloud , cloud eda

Artificial Intelligence (AI)

Arm and Cadence Showcase AI System Collaboration at AI Infra Summit 2025

At the AI Infra Summit 2025 in Santa Clara, California, Arm's VP of Marketing for…

• 1 min read
artificial intelligence , cadence.ai , AI in chip design , Palladium , AI/ML , ARM , AI

Academic Network

Spotlight: Cornell Custom Silicon Systems

Written by Daniel Kaminski, Cornell Custom Silicon Systems Full Team Lead/Analog…

• 4 min read
ASIC , Cadence Academic Network , pegasus , Virtuoso , Spectre , Innovus , Quantus , IC design

Analog/Custom Design

Virtuoso Studio: A Fresh Look - Redefining Your Design Experience

Virtuoso Studio IC 25.1 brings a modern refreshed interface designed for comfort…

• 2 min read
Virtuoso Studio , Custom IC Design

Verification

Regressions, Coverage Integration, and Verification Closure

Don't miss this opportunity to streamline your verification flow and achieve faster…

• 1 min read
webinar , verification

System, PCB, & Package Design 

Cadence OrCAD X and Allegro X 25.1 Is Now Available

The OrCAD X and Allegro X 25.1 release is now available from Cadence Downloads ,…

• 4 min read
System Capture , OrCAD X Capture , package designer , Allegro X PCB Editor , 25.1 , Topology Workbench , Allegro X Advanced Package Designer , Allegro X Design Platform , Aurora , PCB Editor , OrCAD X OnCloud , PCB design , OrCAD X Presto , OrCAD X , Sigrity , Pulse , allegro x

カスタムIC／ミックスシグナル

Virtuoso Studio がモダンな外観に刷新

Virtuoso Studio IC25.1 で刷新された機能についてご紹介しています。快適性のための Dark Gray テーマ、可読性のための TrueType…

• less than a min read
Virtuoso , japanese blog , Custom IC Design

Verification

Streamlining Digital Front-End Design and Verification with Cadence Tools

Plan, Simulate, and Debug: Streamlining Digital Front-End Design and Verification…

• 1 min read
webinar , xcelium , verification

Digital Design

Accelerating Design Closure with Cadence Certus Closure Solution v25.1

Cadence Certus Closure Solution addresses the challenges of timing closure in advanced…

• 2 min read
learning , training , certus , timing convergence

System, PCB, & Package Design 

Stay Future-Ready with Cadence Licensing and Installation Community Hub

Staying ahead in PCB and IC Package design means being ready for the latest releases…

• 1 min read
PCB , install , license , community forum , Cadence forums , PCB design

Digital Design

Smarter, Longer, Cooler: Low-Power Flow for the Devices That Never Sleep

Cadence’s Innovus Low-Power Flow v25.1 offers a comprehensive solution for implementing…

• 2 min read
digital badge , Low Power , Cadence Online Support , training , Innovus , Power Analysis

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium , AI

System, PCB, & Package Design 

Ascent: Training Insights: Smarter Design Reuse with Allegro X System Capture

In today's fast-paced electronics industry, time-to-market is critical. Engineers…

• 3 min read
PCB , System Capture , PCB Editor , Design Reuse , PCB design , Training Insights , ASCENT , Allegro X System Capture

The India Circuit

Story of Preshita Parmar - Cadence Scholarship Program

Preshita Parmar began to shape a life grounded in resilience and self-belief in the…

• 1 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Verification

Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained

Introduction The Flit Sequence Number is a mechanism introduced in the PCIe 6.0…

• 5 min read
Verification IP , VIP , Flit Sequence Number , PCIe , PCIe 6.0 , flit mode , verification
CDNS - Fix Layout Hompage