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Featured

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
Arif Khan 7 Nov 2025 • 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
Corporate 28 Oct 2025 • 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 23 Oct 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
Veena Parthan 21 Oct 2025 • 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform
cdns - all_blogs_categories

  • All 6127
  • Corporate News 206
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  • Analog/Custom Design 773
  • Artificial Intelligence 24
  • Cloud 19
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  • Data Center 41
  • Digital Design 434
  • Learning and Support 56
  • RF Engineering 114
  • SoC and IP 418
  • System, PCB, & Package Design  991
  • Verification 1291
  • Cadence Japan 4

  • CFD(数値流体力学) 45
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  • PCB、IC封装:设计与仿真分析 136
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  • RF /マイクロ波設計 44
  • Spotlight Taiwan 61
  • The India Circuit 90
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Verification

Streamlining Digital Front-End Design and Verification with Cadence Tools

Plan, Simulate, and Debug: Streamlining Digital Front-End Design and Verification…

ErinGrant 29 Oct 2025 • 1 min read
webinar , xcelium , verification

Digital Design

Accelerating Design Closure with Cadence Certus Closure Solution v25.1

Cadence Certus Closure Solution addresses the challenges of timing closure in advanced…

sakshin 28 Oct 2025 • 2 min read
learning , training , certus , timing convergence

System, PCB, & Package Design 

Stay Future-Ready with Cadence Licensing and Installation Community Hub

Staying ahead in PCB and IC Package design means being ready for the latest releases…

Renu Vibha 28 Oct 2025 • 1 min read
PCB , install , license , community forum , Cadence forums , PCB design

Digital Design

Smarter, Longer, Cooler: Low-Power Flow for the Devices That Never Sleep

Cadence’s Innovus Low-Power Flow v25.1 offers a comprehensive solution for implementing…

sakshin 28 Oct 2025 • 2 min read
digital badge , Low Power , Cadence Online Support , training , Innovus , Power Analysis

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate 28 Oct 2025 • 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium , AI

System, PCB, & Package Design 

Ascent: Training Insights: Smarter Design Reuse with Allegro X System Capture

In today's fast-paced electronics industry, time-to-market is critical. Engineers…

Priyadarshini N D 28 Oct 2025 • 3 min read
PCB , System Capture , PCB Editor , Design Reuse , PCB design , Training Insights , ASCENT , Allegro X System Capture

The India Circuit

Story of Preshita Parmar - Cadence Scholarship Program

Preshita Parmar began to shape a life grounded in resilience and self-belief in the…

Asim Khan 27 Oct 2025 • 1 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Verification

Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained

Introduction The Flit Sequence Number is a mechanism introduced in the PCIe 6.0…

Felipe Goncalves 23 Oct 2025 • 5 min read
Verification IP , VIP , Flit Sequence Number , PCIe , PCIe 6.0 , flit mode , verification

Digital Design

From Defects to Diagnostics: How DFT Transforms Chip Manufacturing

In today’s semiconductor industry, the complexity of integrated circuits (ICs) is…

KShubham 23 Oct 2025 • 2 min read
DFT , Chip manufacturing , Genus Synthesis Solution

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team 23 Oct 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement , IC Release Blog , Custom IC Design

SoC and IP

Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch

By Vijay Pawar of Cadence and Matthias Cremon of Meta Introduction Deploying…

pulin 22 Oct 2025 • 2 min read
IP , Tensilica , HiFi DSP

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan 21 Oct 2025 • 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate 21 Oct 2025 • 1 min read
featured , innovation , Beta CAE , event , AI , simulation

Computational Fluid Dynamics

Flutter Analysis: For Safer Air Travel

Recent aviation incidents, including a commercial plane crash attributed to a loss…

Veena Parthan 16 Oct 2025 • 4 min read
fluid-structure interaction , flutter analysis , cadencelive silicon valley , aircraft performance

Cloud

Verification Without Limits: Speed Up Your Burst Simulation with Verisium Cloud

Even with the best tools and smart engineers, chip verification often experiences…

Anika Sunda 15 Oct 2025 • 1 min read
SaaS , verisium , cloud , Jasper , xcelium , verification

Analog/Custom Design

Faster Standard Cell Layout: Auto Place and Route with Virtuoso Layout Suite MXL

Are you still manually placing and routing standard cells, spending hours on repetitive…

Sandeep O 14 Oct 2025 • 4 min read
Virtuoso Studio , Advanced Node , Cadence Education Services , Custom IC Design , IC23.1

Analog/Custom Design

Virtuoso Studio: Design Smarter and Verify Faster with iPegasus

Virtuoso Studio + iPegasus boost IC design with smart DRC, fill, and verification…

JentilTom 14 Oct 2025 • 6 min read
Cadence blogs , Virtuoso Studio , Advanced Node , Layout Suite , Layout , Virtuoso , analog design , Custom IC Design , online training , Virtuoso Layout Suite , Custom IC , verification

Learning and Support

Welcoming ChipMango to the Cadence Certified Training Partner Program

We are thrilled to announce that ChipMango has joined the Cadence Certified Training…

VNelson 14 Oct 2025 • 2 min read
RTL , training , Cadence training , Cadence certified , bridgingthelearninggap , skillgap

System, PCB, & Package Design 

Sigrity and Systems Analysis 2025.1 Release Now Available

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2025.1 release is now available…

SigrityReleaseTeam 14 Oct 2025 • 12 min read
XcitePI , amm , OptimizePI , Celsius Studio , Sigrity , Clarity 3D Solver , Layout Workbench , T2B , Clarity 3D Workbench , PowerSI
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CDNS - Fix Layout Hompage

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