ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard

Non-volatile memories like Nand Flash are key components of most modern system-on-chip (SoC). The I/O speeds and bandwidth of these types of memories are seeing tremendous improvements and advances in the underlying technology are making them increasingly used for a large variety of applications. These applications rely on not just the high density that traditionally has been the main benefit of flash memories, but throughput that can be comparable to DRAMs and other high data rate memory devices. Some of the most used applications of Nand flash devices include mobile/handhelds, data centers, automotive, gaming, and have found applications in memory intensive AI workloads.

NAND Flash

NAND Flash is one of the most popular types of storage technologies. It’s a non-volatile memory where the data is retained even when there is no power supplied to the device. NAND flash technology has evolved over the years to allow for higher density for the same number of memory cells. The initial generation of NAND Flash memory cell only stored a single bit per cell (SLC), which later evolved into multi-level cell (MLC that can store 2 bits per cell) and Triple Level Cell (TLC, where 3 data bits can be stored in each cell). Recent developments have NAND Flash devices using three-dimensional TLC cells and quad-level cells (QLC) to allow for even higher density than a planner TLC device would offer at the expense of additional complexity and cooling challenges. Traditionally, NAND Flash memory devices offered by different memory vendors have all differed in terms of pin interfaces, commands, and timings, to list a few variations.

Open NAND Flash Interface Specification (ONFI) started as an industry initiative to bring standardization to the I/O interface to NAND Flash based devices with more than 100 companies being part of this effort. The first ONFI 1.0 standard was published in 2006. The ONFI Specification has had multiple revisions since then to cater to the needs of higher performance, density, and power efficiency of today’s market.

ONFI 5.2

ONFI 5.2 is the latest generation of ONFI device standard, published in 2024. ONFI 5.2 devices have added several major features over previous generation ONFI standards. Some of the important changes are as follows:

Separate Command Address (SCA)

SCA protocol is a major change for ONFI 5.2 devices. SCA allows Hosts to optimize the command and data scheduling significantly to increase overall available bandwidth. It includes

• Separate command/address (CA) and data busses

ONFI 5.2 compliant devices have additional signals for command/address packet (CA[1:0]_x), command/address bus enable (CA_CEy_x_n), and command/address clock (CA_CLK_x). The host can use these to issue a new command to the device while the previous read or program command’s data transfer hasn’t been completed. Allowing the separation of commands and data transfers helps with concurrent command/address (CA) and data traffic improving NAND interface throughput. This is also used in other high-speed memory devices, such as DRAMs.

• SCA Protocol Command Set

ONFI 5.2 defines a new SCA Protocol Command Set along with the Conventional Protocol Command Set supported by ONFI compliant devices until v5.1. The SCA Protocol Command Set can include a third cycle for operations such as multi-plane page program, page cache program, multiplane copyback program, etc.

• Timing and signal requirements

Other changes in the SCA protocol include new signal value requirements during power on reset initialization and additional timings requirements, such as tWLCEL_CA (CA_CLK low setup to first CE# low after SCA protocol has been enabled) that the host should follow.

• Device Trainings

SCA interface Device training for reads, writes and CA bus/training, etc., is recommended for the proper operation of an ONFI 5.2 device.

DC and Operating Conditions for Raw NAND

ONFI 5.2 has higher values for read, program, standby, and active external supply voltage (Vpp). The LUN Array Read and Program current depends on the operating speeds for ONFI 5.2 devices and can be up to 150 mA. The host must account for the additional current requirements while planning for the device power budget.

Cadence VIP offers memory models for all generations of ONFI devices, including the recently released ONFI5.2 model. Cadence ONFI memory model is not only functionally accurate; but it also checks for specification compliance to all host requirements defined in the standard.

If you have any queries, contact us at talk_to_vip_expert@cadence.com

More information on Cadence ONFI VIP is available at Cadence VIP Memory Models Website.