Forums - Cadence Technology Forums

This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett

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1147

Error in PSS and PNoise simulation of a VCO followed by Frequency detector with 150MHz clock signal

By Jayanta
9/19/2020 10:25:13 PM

PCB Design

From schematic to autorouting what are your challenges in producing high-speed designs?

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24195

after CISAddSearchQuery -> CISExecuteQuery, then how to clear added conditions?

By Terry0909
9/25/2020 10:40:18 AM

PCB SKILL

Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.

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4973

Allegro script runs fine in the SKILL interpreter window, fails when running from the Allegro Command line

By David M Gonzales
9/25/2020 12:50:00 AM

PCell Designer

Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett

How to redefine methods

By Shweta K
9/3/2020 7:48:40 AM

RAVEL DRC Programming for IC Packaging and PCB

Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg

fiducial holes creation

By babu pcb
12/17/2018 12:39:52 AM

RF Design

Moderator: Andrew Beckett.

869

2816

[AWR Microwave Office] Harmonic Balance in Load-Pull analysis

By Eres
9/23/2020 2:30:03 PM

Verification IP

Simvision debugging techniques

By MaheshKumar
8/2/2020 7:24:24 PM

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pcb footprint creation

By Dinesh Moka
9/2/2020 3:40:08 AM

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Moderator: Community Operations

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455

Look up table generation of TFET using verilog-A models in CADENCE

By Kabes
9/17/2020 12:56:10 AM

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