Forums

|

Subscribe for email delivery of all Cadence forum topics here

Nextweb Forums Categories
Site - Banner

Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6406
20104
Spectre hangs before popup the output log window for a long time when running with 900MB netlist.
By
1/19/2021 12:17:29 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4562
15762
Problems with ViVA grid display in app and pdf plots
By
1/18/2021 2:57:35 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2222
4243
generateCapTbl command fails in INNOVUS because "Poly layer is not defined in pcs file"
By
1/5/2021 10:25:03 PM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1650
3508
vManager Regressions failing due to Exclusive Lock
By
1/18/2021 10:52:48 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
58
116
FEV ISSUE
By
4/11/2020 1:38:12 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
295
313
Hardware/Software for messing with field recordings?
By
12/7/2020 9:47:37 PM
High-Level Synthesis
Moderator: Dave Pursley
34
58
How to get full module names in report_area command
By
10/10/2020 1:00:24 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
168
299
Differences between APD & CDNSIP
By
1/7/2021 10:44:34 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
643
1101
Error in Cadence RTL Compiler when estimating Power using VCD
By
1/18/2021 11:52:36 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
482
1221
number of noise/freq pairs in pss/pnoise simulation
By
1/12/2021 6:13:48 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9071
24619
Allegro Library Creator 17.4 Licensing Error
By
1/18/2021 3:36:59 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1638
5047
Implementing "Oops" in a Temp Group
By
1/11/2021 12:35:14 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
890
2903
multiple S-parameter Simulation touchstone save
By
1/13/2021 9:27:59 AM
Verification IP
25
5
User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification
By
10/4/2020 10:18:15 PM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
86
7
pcb footprint creation
By
9/2/2020 3:40:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
353
458
Look up table generation of TFET using verilog-A models in CADENCE
By
9/17/2020 12:56:10 AM

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.