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Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6955
22243
About Multi technology simulation
By
12/8/2021 11:49:16 PM
Custom IC SKILL
Moderator: Andrew Beckett.
4862
16803
How to prevent design rule error (physical property) in virtuoso schematic?
By
12/9/2021 1:27:26 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2237
4257
How to vary βn/βp ratio for a cmos inverter?
By
12/5/2021 10:03:36 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1695
3619
Instance is unresolved in module
By
12/8/2021 1:05:42 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
62
132
Create branches between two ports as an array in VerilogA
By
11/28/2021 10:05:19 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
296
316
xtensa download
By
9/23/2021 9:12:45 AM
High-Level Synthesis
Moderator: Dave Pursley
38
28
How to launch Stratus GUI
By
10/21/2021 1:02:52 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
179
312
How to define comment syntax for a language
By
10/11/2021 11:06:45 PM
Implementation
Board and package design enablement
Moderator: Rishikesh Pawar, Atish Mukhopadhayay
7
0
uvm Error-[IND] Identifier not declared
By
11/11/2021 11:17:19 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
661
1129
How to interpret area reported by Genus in mm2
By
10/15/2021 2:11:53 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
543
1459
Accuracy / Resolution of real variable in SV - AMS simulation beeing limited to 6 bit ?!?!!
By
12/3/2021 8:27:44 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9538
25821
decompose a component
By
12/9/2021 12:26:44 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1737
5266
Finding Un even Shapes
By
12/8/2021 8:45:42 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
932
3143
Error when editing RFTlinelib stackup cell with custom materials
By
10/27/2021 8:34:51 AM
Verification IP
27
5
Driving a spectra /spice (analog) schematic from xcelium
By
11/25/2021 7:16:24 AM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
52
4
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
360
481
Changing username
By
11/22/2021 7:32:55 AM

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