As of July 1, 2021, Google will discontinue the RSS-to-email subscriptions service.
Hence, the email alerts will be impacted while we explore other options. Please stay tuned for further communication from us.

Forums

|

Subscribe for email delivery of all Cadence forum topics here

Nextweb Forums Categories
Site - Banner

Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6685
21264
PEX
By
6/21/2021 3:05:28 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4701
16253
Tried using the ABE to obtain layer within a bBox, got all abutting layer shapes instead
By
6/21/2021 2:54:44 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2221
4243
Library characterization using Cadence
By
6/17/2021 9:55:15 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1668
3547
probe tcl syntax to save variables inside automatic tasks in systemverilog
By
6/16/2021 11:46:46 PM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
61
122
How to verify the functionality of synthesized netlist ?
By
3/25/2021 1:56:38 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
295
315
Issue With Loudness Normalization
By
1/22/2021 6:01:38 AM
High-Level Synthesis
Moderator: Dave Pursley
35
27
Cadence genus Initialisation
By
6/21/2021 6:53:03 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
178
306
Dynamic Shape clearance Error
By
6/21/2021 8:55:25 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
658
1126
Default settings for cell mapping - Genus Synthesis (Legacy)
By
5/31/2021 5:20:32 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
521
1373
Hierarchical calling of VerilogA models
By
6/21/2021 9:22:21 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9298
25206
Place pin around circle
By
6/21/2021 9:41:20 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1697
5175
How to use quotes on skill command on Windows
By
6/8/2021 2:48:45 AM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
915
3050
Plotting Phase Noise for Injection Locked Ring Oscillator
By
6/18/2021 1:24:34 PM
Verification IP
25
5
User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification
By
10/4/2020 10:18:15 PM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
81
6
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
355
471
Tag for English Blogs?
By
5/10/2021 8:17:21 AM

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.