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Cadence Technology Forums

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Custom IC Design
Moderator: Andrew Beckett.
5611
17287
Transient Current Noise vs AC current noise
By
8/16/2019 10:57:55 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4113
14282
Highlight a Shape within a PCELL
By
8/16/2019 8:38:17 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2127
4160
Implementation methodology for driver and receiver implementation
By
7/26/2019 3:09:51 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1577
3347
How to effectively browse verilog source in Cadence
By
8/17/2019 6:56:20 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
115
Creating cover items for sparse values/queue or define in specman
By
7/15/2019 8:51:51 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
292
312
USB crash issue in Linux 4.14.62
By
4/16/2019 1:41:56 AM
High-Level Synthesis
Moderator: Dave Pursley
24
44
Synthesize net to flip-flop cell with differential output.
By
6/22/2019 3:47:22 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
149
216
detecting duplicated shapes
By
7/4/2019 12:41:49 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
620
1093
Post-synthesis Simulation Failing when lp_insert_clock_gating true
By
8/15/2019 6:42:48 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
402
944
Ocean Script (AMS simulator): How to save only digital or analog nets
By
8/15/2019 8:43:26 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8202
22096
Assign Voltage For Power and Ground Nets
By
8/16/2019 10:32:48 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1470
4673
Drawing level property
By
8/15/2019 3:09:40 AM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
3
8
appCell demo library (add-on to CDNLive EMEA 2019 CUS-Techtorial V)
By
6/10/2019 10:35:20 PM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
759
2397
modulated PAC analysis
By
8/13/2019 11:24:17 AM
Verification IP
9
1
Direct driving DP/DM signals from sequence in USB VIP CAT
By
7/1/2019 1:20:42 AM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
48
4
Boost your IIT JEE Preparation with Vibrant Academy
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8/17/2019 4:48:09 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
343
430
How to effectively browse verilog source in Cadence
By
8/17/2019 6:54:23 AM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
72
11
Best Recruitment Marketplace- Emagine People Solutions
By
8/14/2019 5:10:22 AM

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