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Custom IC Design
Moderator: Andrew Beckett.
5889
18195
Simulation of an inverter using FinFETs
By
2/24/2020 8:43:30 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4287
14867
How to Execute Unix Commands through CIW Window and Store the output in a variable on Unix/CIW Window (Rather than file)?
By
2/24/2020 1:08:47 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2160
4180
Can Voltus do an IR drop analysis on a negative supply?
By
2/19/2020 10:20:47 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1603
3404
How to refer the library compiled by INCISIVE 13.20 in Xcelium 19.30
By
2/19/2020 4:06:53 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
115
Creating cover items for sparse values/queue or define in specman
By
7/15/2019 8:51:51 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
291
313
Arduino: how to save the dynamic memory?
By
11/5/2019 11:25:31 PM
High-Level Synthesis
Moderator: Dave Pursley
26
55
Genus Synthesis Timing Report does not make any sense
By
1/3/2020 9:41:54 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
156
234
How to check a cluster of same net vias spacing, with have no shape or cline covered
By
2/13/2020 8:12:15 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
629
1096
About SDF file after synthesis in Genus Tool
By
2/20/2020 1:47:17 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
437
1039
VCOs with Arbitrary Phase Noise Profile
By
2/23/2020 1:00:39 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8585
23104
HDL Schematic
By
2/24/2020 5:49:57 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1533
4837
E- (SPMHDB-187): SHAPE boundary may not cross itself.
By
2/23/2020 11:26:13 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
4
22
Adding Terminal and Pins In Pcell Using Pcell Designer Tool.
By
2/11/2020 5:43:18 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
822
2650
Copying read only problen in cadence virtuoso
By
2/23/2020 8:56:47 AM
Verification IP
17
3
I have a question about UVM_INFO in my output log file
By
1/29/2020 5:49:48 AM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
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International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
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445
Online training
By
2/21/2020 2:45:02 AM

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