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Cadence Technology Forums

Forum Name
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Custom IC Design
Moderator: Andrew Beckett.
5163
15770
Probing internal node to dspf file
By
11/15/2018 4:01:16 PM
Custom IC SKILL
Moderator: Andrew Beckett.
3823
13243
viaGenerateViasAtPoint very slow
By
11/16/2018 5:57:50 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2079
4128
Please help me I'm getting really wired signal violation
By
11/12/2018 1:06:19 PM
Functional Verification
Moderator: Adam Sherer
1509
3170
Compilation error with xcelium
By
11/8/2018 3:46:49 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
57
110
help for $sscanf
By
4/21/2016 9:03:22 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
287
307
TensorFlow Optimization in DSVM: Azure and Cadence
By
10/22/2018 7:27:32 PM
High-Level Synthesis
Moderator: Dave Pursley
23
37
Inverter Chain Synthesis
By
11/5/2018 1:13:20 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
138
209
No such child. Contact Cadence customer support??
By
10/26/2018 11:56:56 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
607
1085
Inverter Chain Synthesis
By
11/5/2018 1:09:48 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
351
806
measurements on eyediagram
By
11/9/2018 11:55:30 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
7787
20953
Match Group..... Option in Relative Propagation Delay is disabled
By
11/16/2018 11:47:57 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1394
4354
How do we calculate length & width of an arc custom shape, or get the mid point of an arc.
By
11/15/2018 1:50:27 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
16
40
Ravel DRC makrer on dielectric layer
By
6/29/2018 10:36:14 AM
RF Design
Moderator: Andrew Beckett.
708
2161
How to define port in cadence which has a impedance value that is frequency dependent
By
11/15/2018 6:26:43 PM
Verification IP
5
0
伪造【澳洲Deakin毕业证书】Q微551190476伪造迪肯大学结业证书#造迪肯大学毕业证#造迪肯大学文凭#造迪肯大学成绩单
By
11/15/2018 11:07:02 PM

General Topics

Forum Name
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Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
28
4
Need help fast? Check out Cadence Training Bytes
By
6/8/2018 9:25:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
335
413
Evaluation board for Tensilica DNA100 processor
By
11/15/2018 4:00:25 PM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
64
11
Looking for CAD/PCB Librarian in Costa Mesa, CA
By
4/25/2018 10:47:31 AM

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