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Cadence Technology Forums

Forum Name
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Custom IC Design
Moderator: Andrew Beckett.
5354
16459
'spectremdl' not showing any results...
By
3/21/2019 1:58:53 AM
Custom IC SKILL
Moderator: Andrew Beckett.
3919
13593
Is there a function that can modify the existing prBoundary Object in layout??
By
3/21/2019 12:12:59 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2109
4150
multiple and indepedent clock in the same circuits without clock domain crossing
By
3/6/2019 7:46:20 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1540
3252
Export signal loads list
By
3/18/2019 7:06:55 PM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
57
112
help for $sscanf
By
4/21/2016 9:03:22 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
291
311
LM117 Spice Model
By
3/20/2019 10:07:08 AM
High-Level Synthesis
Moderator: Dave Pursley
22
38
Genus - Segmentation Fault
By
10/3/2018 3:38:28 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
144
215
plane via/antipad clearance
By
2/27/2019 4:11:17 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
613
1088
functional equivalence check between system verilog and schematic
By
3/14/2019 2:36:55 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
370
849
Inbuilt math functions for RNM SV modelling of mixed signal blocks
By
3/8/2019 9:43:50 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
7954
21389
Unable to change the design extents
By
3/21/2019 3:50:58 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1411
4442
Can I do _something_ as chars are entered in a SKILL form text field?
By
3/19/2019 5:28:22 PM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
733
2255
transistor state in Vpulse source
By
3/18/2019 9:10:19 AM
Verification IP
8
1
How to deploy AMBA c-core VIPs?
By
1/23/2019 1:21:13 PM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
31
4
Get Top Rank in IIT JEE- Vibrant Academy
By
3/4/2019 10:52:31 PM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
338
419
Porting tensorflow model to HiFi 5
By
2/15/2019 4:17:43 AM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
66
11
Looking for a job in Netherlands
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1/6/2019 10:44:29 PM

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