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Cadence Technology Forums

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Custom IC Design
Moderator: Andrew Beckett.
5161
15758
ADE/Virtuoso Question: .scs File Related
By
11/12/2018 11:54:07 PM
Custom IC SKILL
Moderator: Andrew Beckett.
3820
13232
How to resize a page for a tab fields in a form?
By
11/13/2018 2:43:51 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2079
4127
Please help me I'm getting really wired signal violation
By
11/12/2018 1:06:19 PM
Functional Verification
Moderator: Adam Sherer
1509
3170
Compilation error with xcelium
By
11/8/2018 3:46:49 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
57
110
help for $sscanf
By
4/21/2016 9:03:22 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
287
307
TensorFlow Optimization in DSVM: Azure and Cadence
By
10/22/2018 7:27:32 PM
High-Level Synthesis
Moderator: Dave Pursley
23
37
Inverter Chain Synthesis
By
11/5/2018 1:13:20 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
138
209
No such child. Contact Cadence customer support??
By
10/26/2018 11:56:56 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
608
1085
Re-characterizing a tap-less cell library (Cadence Liberate)
By
11/11/2018 1:25:19 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
351
806
measurements on eyediagram
By
11/9/2018 11:55:30 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
7781
20932
Stack up Table Zone ordering
By
11/13/2018 9:19:58 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1393
4354
alignment of a pin on a component to a pin on an adjacent component
By
11/8/2018 1:55:36 PM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
16
40
Ravel DRC makrer on dielectric layer
By
6/29/2018 10:36:14 AM
RF Design
Moderator: Andrew Beckett.
707
2161
gilbert cell mixer using tsmc 90nm
By
10/29/2018 10:29:06 AM
Verification IP
3
0
NC Verilog issue
By
9/18/2018 11:55:43 PM

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
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Need help fast? Check out Cadence Training Bytes
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6/8/2018 9:25:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
334
412
Developing an Idea
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9/14/2018 1:45:43 PM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
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Looking for CAD/PCB Librarian in Costa Mesa, CA
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4/25/2018 10:47:31 AM

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