• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      excellon1
      excellon1 137 Points
    • 2
      masamasa
      masamasa 129 Points
    • 3
      steve
      steve 100 Points
    • 4
      DavidJHutchins
      DavidJHutchins 95 Points
    • 5
      DG202504226528
      DG202504226528 80 Points
  • Leaderboard

    • 1
      steve
      steve 17,699 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,251 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Copy schematic/symbol views hierarchically

    Category: Custom IC Design

    By ycau

    •

    started 20 hours ago

    0 replies • 16 views
  • Discussion

    Recovering "actionable" netlist from GDS II

    Category: Custom IC Design

    By GS202507021424

    •

    updated 1 day ago by Andrew Beckett

    1 replies • 87 views
  • Discussion

    copy of a maestro view and chnaging design cause all the setup to be lost

    Category: Custom IC Design

    By TommasoF

    •

    updated 1 day ago by Andrew Beckett

    11 replies • 340 views
  • Discussion

    Transfer design variable from schematic / layout to av_extracted view

    Category: Custom IC Design

    By FM202408077836

    •

    updated 1 day ago by Andrew Beckett

    2 replies • 140 views
  • Not Answered

    Starting Project from netlist, or layout

    Category: Allegro X System Capture (EE Cockpit)

    By ML202409254454

    •

    updated 1 day ago by avant

    3 replies • 159 views
  • Discussion

    How to interpret a single backslash from an input file?

    Category: Custom IC SKILL

    By MM202511045434

    •

    updated 1 day ago by Andrew Beckett

    3 replies • 134 views
  • Discussion

    Explanation of stb analysis results YG, YL, ZG, and ZL

    Category: Custom IC Design

    By Frank Wiedmann

    •

    started 1 day ago

    0 replies • 48 views
  • Answered

    Remove overlapping vias

    Category: Allegro X PCB Editor

    By bdc66a938f164d

    •

    updated 1 day ago by bdc66a938f164d

    4 replies • 223 views
  • Discussion

    Question on integrated noise in PNOISE (sampled) Noise summary

    Category: Custom IC Design

    By Yuto Lau

    •

    updated 2 days ago by Yuto Lau

    4 replies • 209 views
  • Discussion

    Automating Layout Cell Updates Using SKILL with Cell List from File

    Category: Custom IC Design

    By AR202509246930

    •

    updated 2 days ago by Andrew Beckett

    1 replies • 134 views
>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information