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Custom IC Design
Moderator: Andrew Beckett.
5949
18370
How do I sweep a simulator option parameter (gmin, vabstol, rforce,...) in ADE Explorer / XL?
By
4/2/2020 2:26:30 PM
Custom IC SKILL
Moderator: Andrew Beckett.
4327
15004
Usage of commands dbOpenCellViewByType and deOpenCellView and difference between geGetWindowCellView and geGetEditCellView !!!
By
4/2/2020 11:30:05 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2166
4182
In power pins unconnected
By
3/31/2020 2:59:11 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1607
3414
XmVlog - *F,DIRDEC error
By
3/29/2020 7:40:48 PM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
115
Creating cover items for sparse values/queue or define in specman
By
7/15/2019 8:51:51 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
291
312
Arduino: how to save the dynamic memory?
By
11/5/2019 11:25:31 PM
High-Level Synthesis
Moderator: Dave Pursley
27
60
Using Cadence Genus withou any libraries
By
4/1/2020 1:33:58 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
156
234
How to check a cluster of same net vias spacing, with have no shape or cline covered
By
2/13/2020 8:12:15 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
632
1096
About SDC file
By
2/27/2020 5:58:58 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
441
1044
altergroup
By
3/31/2020 10:10:41 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8654
23331
Dynamic fillet
By
4/2/2020 9:27:40 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1545
4865
How to reload a SKILL-script in Allegro
By
4/2/2020 1:35:23 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
5
27
Facing issue in seeing the changes made in deployed Pcell.
By
3/9/2020 4:41:38 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
839
2691
LNA output noise floor at receiver front end.
By
4/2/2020 12:30:37 AM
Verification IP
17
3
I have a question about UVM_INFO in my output log file
By
1/29/2020 5:49:48 AM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
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7
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
350
447
Images in online support not shown
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3/5/2020 10:45:43 AM

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