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Custom IC Design
Moderator: Andrew Beckett.
6353
19844
Mismatch simulation in Monte Carlo
By
12/4/2020 6:24:54 PM
Custom IC SKILL
Moderator: Andrew Beckett.
4534
15677
Running Cadence in the background of the server and successfully reconnect it after network stops
By
12/3/2020 10:08:06 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2213
4232
trouble with auto routing minimum spanning tree, Layout XL
By
12/4/2020 5:28:17 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1645
3492
OSVVM Support and Xcelium
By
12/3/2020 10:25:47 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
116
FEV ISSUE
By
4/11/2020 1:38:12 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
295
312
Hardware/Software for messing with field recordings?
By
11/24/2020 1:40:18 AM
High-Level Synthesis
Moderator: Dave Pursley
30
56
How to get full module names in report_area command
By
10/10/2020 1:00:24 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
167
297
Scripts or commands to create the package stackup
By
10/22/2020 12:24:34 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
640
1101
Tool for generating 'documentation friendly' schematics from RTL
By
9/24/2020 7:53:09 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
477
1194
How to save digital waveforms in monte carlo
By
11/30/2020 4:10:02 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9020
24463
found new bug
By
12/5/2020 2:31:59 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1628
5029
Component placement -Draw Rectangle
By
11/26/2020 9:14:56 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
30
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
883
2861
identification of diode and monolithic amplifier
By
12/4/2020 8:25:22 AM
Verification IP
25
5
User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification
By
10/4/2020 10:18:15 PM

General Topics

Forum Name
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Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
86
7
pcb footprint creation
By
9/2/2020 3:40:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
354
458
Look up table generation of TFET using verilog-A models in CADENCE
By
9/17/2020 12:56:10 AM

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