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Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6879
21937
Several problems with interfacing Spectre through Matlab
By
10/22/2021 7:24:37 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4823
16646
Save current "state of palette" only to reset later
By
10/22/2021 2:49:12 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2232
4252
[Voltus] Why static IR drop require timing window (TWF) file?
By
10/10/2021 10:04:47 PM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1686
3586
How to check if signal top.moduleA.aaa is directly connected to top.moduleB.bbb using xcellium TCL? (or simvision)
By
10/19/2021 6:57:34 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
62
130
Create branches between two ports as an array in VerilogA
By
10/14/2021 12:45:59 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
296
315
xtensa download
By
9/23/2021 9:12:45 AM
High-Level Synthesis
Moderator: Dave Pursley
38
28
How to launch Stratus GUI
By
10/21/2021 1:02:52 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
179
310
How to define comment syntax for a language
By
10/11/2021 11:06:45 PM
Implementation
Board and package design enablement
Moderator: Rishikesh Pawar, Atish Mukhopadhayay
6
0
pnR problem
By
10/12/2021 11:05:30 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
661
1129
How to interpret area reported by Genus in mm2
By
10/15/2021 2:11:53 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
534
1423
pss simulation issues
By
10/22/2021 5:55:25 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9478
25661
L293DNE Quadruple Half-H Drivers
By
10/22/2021 7:32:24 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1730
5247
axlSetFindFilter keyword "NAMEFORM" is not working if the script is executed by replaying *.scr file
By
10/18/2021 7:04:34 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
931
3128
sampled pnoise on multi-phase switched cap circuit
By
10/22/2021 8:41:35 PM
Verification IP
26
5
changing error severity of a vip error
By
7/26/2021 3:44:46 AM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
81
7
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
358
474
ERROR while creating a verliog file on cadence virtuoso
By
8/30/2021 2:37:45 AM

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The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.