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Custom IC Design
Moderator: Andrew Beckett.
6194
19323
Probing nodes in sub-hierachies with SPF
By
8/13/2020 3:44:52 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4449
15432
performance multiple value vs multiple calls to value in ocean
By
8/12/2020 3:11:40 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2197
4216
Cannot apply preserve attribute in VHDL source file
By
8/11/2020 2:14:43 PM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1631
3454
Prevent SimVision Schematic Viewer from Re-Zooming/Centering after tracing a signal
By
8/13/2020 11:33:45 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
115
FEV ISSUE
By
4/11/2020 1:38:12 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
291
316
QSPI Direct Access bare metal SW driver
By
4/24/2020 2:11:32 AM
High-Level Synthesis
Moderator: Dave Pursley
27
54
Using Cadence Genus withou any libraries
By
4/1/2020 1:33:58 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
164
252
Moving C-Lines to different layer
By
8/12/2020 8:56:09 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
639
1102
Conformal LEC error
By
8/8/2020 11:51:12 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
462
1124
coupling between digital outputs in cosim?
By
8/9/2020 7:29:41 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8849
23988
In Capture 17.4 HF009 show footprint，zoom in zoom out and zoom fit button doesn't work
By
8/12/2020 12:20:15 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1580
4943
Deleting Double Quotes in Report
By
8/13/2020 2:54:58 AM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
7
29
Create a hidden CDF parameter
By
8/10/2020 2:54:17 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
857
2773
Documents for using EMX for EM simulations of inductor and Transmission LIne
By
8/1/2020 10:02:07 AM
Verification IP
24
5
Simvision debugging techniques
By
8/2/2020 7:24:24 PM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
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International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
353
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Single Sign On Error
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7/19/2020 9:49:11 AM

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