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Cadence Technology Forums

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Custom IC Design
Moderator: Andrew Beckett.
5206
15944
variable sweep in ADEXL
By
12/16/2018 1:59:49 AM
Custom IC SKILL
Moderator: Andrew Beckett.
3850
13376
Cant get cutClass type of via from querying the via
By
12/16/2018 2:05:06 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2088
4135
Systemverilog interfaces over hierarchical boundaries
By
12/13/2018 6:50:32 AM
Functional Verification
Moderator: Adam Sherer
1517
3183
how to enlarge simulation time limit of ncsim?
By
12/13/2018 6:22:04 PM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
57
112
help for $sscanf
By
4/21/2016 9:03:22 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
288
307
Using oscillograph waveform file CSV as the Pspice simulation signal source
By
11/19/2018 10:28:04 PM
High-Level Synthesis
Moderator: Dave Pursley
22
38
Genus - Segmentation Fault
By
10/3/2018 3:38:28 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
138
209
No such child. Contact Cadence customer support??
By
10/26/2018 11:56:56 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
608
1086
problem with "REPORT RULE CHECK" command using conformal
By
12/7/2018 9:00:17 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
358
823
Run analogLib/fourier before stop time
By
12/12/2018 11:11:00 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
7827
21060
Symbol not found in PSMPATH or must be "dbdoctor"ed.
By
12/14/2018 4:44:43 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1397
4369
finger number
By
11/25/2018 2:48:13 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
40
fiducial holes creation
By
12/11/2018 2:12:26 AM
RF Design
Moderator: Andrew Beckett.
715
2187
back to back square wave generation
By
12/14/2018 6:26:36 AM
Verification IP
3
0
NC Verilog issue
By
9/18/2018 11:55:43 PM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
28
4
Need help fast? Check out Cadence Training Bytes
By
6/8/2018 9:25:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
335
414
Evaluation board for Tensilica DNA100 processor
By
11/15/2018 4:00:25 PM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
64
11
Looking for CAD/PCB Librarian in Costa Mesa, CA
By
4/25/2018 10:47:31 AM

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