Forums

|

Subscribe for email delivery of all Cadence forum topics here

Site - Banner

Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
5299
16242
Viva plot colors change on every iteration during real time tuning
By
2/18/2019 5:10:22 AM
Custom IC SKILL
Moderator: Andrew Beckett.
3897
13530
How to pass a value from a procedure to another?
By
2/14/2019 8:05:15 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2107
4146
constraints file
By
2/16/2019 8:04:59 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1531
3235
Xcelium Functional Coverage
By
2/14/2019 9:15:53 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
57
112
help for $sscanf
By
4/21/2016 9:03:22 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
289
308
Functional coverage report.
By
2/13/2019 3:37:00 PM
High-Level Synthesis
Moderator: Dave Pursley
23
37
Power consumption per clock cycle using Genus
By
1/30/2019 9:13:10 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
142
211
How to add resistor models in the Power SI[Model Extraction]
By
2/7/2019 9:17:28 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
610
1088
for choosing the frequency range of any digital circuit
By
1/31/2019 10:38:13 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
364
837
ams simulator vs spectre: empty schematic view
By
2/18/2019 12:28:05 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
7909
21257
How to create a template for a BOM in OrCAD Capture 17.2
By
2/18/2019 6:44:03 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1401
4388
grids.il program stopped working when used in v17
By
2/12/2019 9:06:17 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
728
2238
HB simulation of a mixer using two different oscilator sources
By
2/17/2019 9:04:58 AM
Verification IP
8
1
How to deploy AMBA c-core VIPs?
By
1/23/2019 1:21:13 PM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
28
4
Need help fast? Check out Cadence Training Bytes
By
6/8/2018 9:25:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
338
419
Porting tensorflow model to HiFi 5
By
2/15/2019 4:17:43 AM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
66
11
Looking for a job in Netherlands
By
1/6/2019 10:44:29 PM

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.