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Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6487
20449
CCCS - controlling element not available
By
3/1/2021 3:00:19 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4590
15844
SLOTTING_SKILL feature is not enabled for (lxShapeSlotting)
By
2/22/2021 4:25:03 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2232
4256
Mesh router: discover the benefits of wi-fi technology
By
3/2/2021 12:14:36 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1658
3531
getting xrun to quit on error during simulation
By
2/24/2021 9:22:30 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
117
brd file
By
2/26/2021 2:52:07 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
296
316
Issue With Loudness Normalization
By
1/22/2021 6:01:38 AM
High-Level Synthesis
Moderator: Dave Pursley
35
58
How to change font size for help/menus ?
By
2/11/2021 8:06:26 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
171
304
APD/CDNSIP compatible versions for Ravel
By
2/25/2021 10:26:56 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
644
1102
Genus advices on how to handle power and analog signals
By
2/1/2021 2:19:43 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
487
1234
Obtaining power traces using Cadence Virtuoso
By
2/25/2021 6:52:34 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9140
24783
Scaling problem in Cadence
By
3/2/2021 12:43:07 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1651
5082
Duplicate Values in list
By
3/1/2021 8:53:15 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
897
2935
Phase noise and jitter simulation
By
2/23/2021 6:57:04 PM
Verification IP
25
5
User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification
By
10/4/2020 10:18:15 PM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
86
7
pcb footprint creation
By
9/2/2020 3:40:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
353
459
Look up table generation of TFET using verilog-A models in CADENCE
By
9/17/2020 12:56:10 AM

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