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Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6825
21742
Modifying BSIM-IMG model and using it in Cadence
By
9/16/2021 10:58:25 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4797
16563
How to call perl one-linear through system command in skill
By
9/16/2021 5:08:41 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2230
4251
IMPESI-3490 Error in Tempus
By
9/8/2021 5:43:17 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1677
3571
make xcellium process command display only uvm processes?
By
9/16/2021 1:26:57 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
61
130
How to verify the functionality of synthesized netlist ?
By
8/2/2021 1:47:44 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
295
315
Issue With Loudness Normalization
By
1/22/2021 6:01:38 AM
High-Level Synthesis
Moderator: Dave Pursley
36
28
Syhthesizing bluespec verilog (.bsv) code with Cadence Genus
By
8/29/2021 11:49:17 PM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
178
310
Dynamic Shape clearance Error
By
7/18/2021 6:51:05 PM
Implementation
Board and package design enablement
Moderator: Rishikesh Pawar, Atish Mukhopadhayay
3
0
Functional coverage: array of covergroups
By
9/14/2021 12:01:45 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
659
1129
How to add logic when compile
By
8/10/2021 7:35:29 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
532
1422
Problem with understanding the noise integration
By
8/30/2021 11:08:57 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9423
25532
OrCAD Allegro 17.4 - PDF Export - Through Hole Pins needs to be filled
By
9/16/2021 1:54:14 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1720
5233
Looking for ADVFC32 SPICE Model
By
9/12/2021 5:43:21 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
927
3111
Wideband amplifier model in VSS
By
9/3/2021 4:14:00 PM
Verification IP
26
5
changing error severity of a vip error
By
7/26/2021 3:44:46 AM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
81
7
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
358
474
ERROR while creating a verliog file on cadence virtuoso
By
8/30/2021 2:37:45 AM

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.