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Cadence Technology Forums

Forum Name
Topics
Replies
Last Post
Custom IC Design
Moderator: Andrew Beckett.
6586
20795
Stop an area of a schematic being netlisted.
By
4/17/2021 5:56:34 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4628
15952
Generate clones with SKILL
By
4/16/2021 7:11:00 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2217
4235
Innovus hold-time optimization in the presence of synchronizers
By
4/16/2021 6:02:06 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1662
3544
JasperGold SAT solver capacity
By
4/17/2021 3:32:27 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
61
120
How to verify the functionality of synthesized netlist ?
By
3/25/2021 1:56:38 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
296
316
Issue With Loudness Normalization
By
1/22/2021 6:01:38 AM
High-Level Synthesis
Moderator: Dave Pursley
34
26
How to change font size for help/menus ?
By
2/11/2021 8:06:26 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
173
304
Convert from PCB PADS file (.pcb) to Sigrity format (.spd)
By
4/2/2021 9:00:14 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
652
1114
Compiling Xilinx libraries using Xcleium
By
4/10/2021 9:25:34 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
501
1276
How to increase Cadence Spectre simulation speed?
By
4/16/2021 9:41:25 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9193
24904
How to add symmetric ground reference via in PCB editor 17.4?
By
4/17/2021 8:30:29 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1667
5115
How to release the customized function
By
4/16/2021 3:15:09 AM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
908
3002
Generating a pulse signal with specific duty cycle using AWR Cadence
By
4/13/2021 9:41:37 AM
Verification IP
25
5
User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification
By
10/4/2020 10:18:15 PM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
81
6
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
353
465
InstallScape
By
3/16/2021 4:36:21 AM

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