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Custom IC Design
Moderator: Andrew Beckett.
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16862
LVS: Calibre Missing Instance
By
5/24/2019 9:18:33 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4000
13865
Merging and creating new shapes in PCell
By
5/24/2019 3:07:44 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2116
4153
Innovus Parasitic Extraction Compatible for Spice Simulation
By
5/14/2019 1:19:32 PM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1555
3286
Is there a way to adapt vRfine file after RTL source file updated and line number changed
By
5/20/2019 10:34:23 PM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
58
113
Creating transition coverage bins using a queue or dynamically
By
4/20/2019 6:31:28 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
292
312
USB crash issue in Linux 4.14.62
By
4/16/2019 1:41:56 AM
High-Level Synthesis
Moderator: Dave Pursley
23
38
Stratus PnR Configs
By
5/20/2019 5:14:24 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
147
215
Allegro Package Designer 16.6 Concern: AddComponent Function not Found
By
4/24/2019 1:17:32 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
615
1088
Conformal ECO use cell out of spare(NO_MAP)
By
4/16/2019 12:58:53 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
379
862
Hierarchical Block Design
By
5/24/2019 1:43:13 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8077
21738
How to check total thermal reliel on thru pin holes
By
5/24/2019 12:10:52 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1429
4510
command line editors of CIW,skill and telskill are difficult to use.
By
5/24/2019 10:56:53 AM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
3
7
appCell demo library (add-on to CDNLive EMEA 2019 CUS-Techtorial V)
By
5/23/2019 9:26:34 PM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
747
2321
problem creating symbol of netlist subcircuit
By
5/24/2019 12:05:32 AM
Verification IP
8
1
How to deploy AMBA c-core VIPs?
By
1/23/2019 1:21:13 PM

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News, FAQs, and related info about how to best use the community.
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5/24/2019 2:17:10 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
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Analysis Modes Constraints Reference
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5/8/2019 9:33:30 PM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
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Fresher Zones- Latest Government Vacancies in India
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4/18/2019 9:06:50 PM

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