Forums - Cadence Technology Forums

This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
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AMS Simulation Error for INCISIV Version

By Mostafa A
5/26/2020 11:44:38 AM

PCB Design

From schematic to autorouting what are your challenges in producing high-speed designs?

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Drill File Missing Holes Because Generates into Multiple Files

By alintz
5/25/2020 10:40:04 AM

PCB SKILL

Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.

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4888

Exit axlSingleSelectPoint(nil) from blocking other code

By leto
5/25/2020 7:26:21 PM

PCell Designer

Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett

Facing issue in seeing the changes made in deployed Pcell.

By AkshayN
3/9/2020 4:41:38 AM

RAVEL DRC Programming for IC Packaging and PCB

Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg

fiducial holes creation

By babu pcb
12/17/2018 12:39:52 AM

RF Design

Moderator: Andrew Beckett.

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2754

discrepancy between spectrum peak value and calculator value in Direct Plot Form after hb simulation

By aidenK
5/25/2020 8:04:00 PM

Verification IP

can we get CHI UVC with 4 RN's

By swathiv
5/14/2020 4:50:52 AM

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Best double eyelid

By ChrisHenry
5/20/2020 1:08:47 AM

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By Arijit Sengupta
4/10/2020 12:47:02 AM

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