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Cadence Technology Forums

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Custom IC Design
Moderator: Andrew Beckett.
5836
18009
How to know the END of a Spectre Simulation fired in the Linux terminal.
By
1/27/2020 12:58:22 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4263
14775
IC1616 Custom Toolbar Icons That Change on State
By
1/28/2020 7:54:00 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2154
4173
LVS Error
By
1/27/2020 7:52:43 PM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1599
3394
Xcelium Probe -Screen Issue
By
1/26/2020 10:33:54 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
115
Creating cover items for sparse values/queue or define in specman
By
7/15/2019 8:51:51 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
291
311
Arduino: how to save the dynamic memory?
By
11/5/2019 11:25:31 PM
High-Level Synthesis
Moderator: Dave Pursley
26
53
Genus Synthesis Timing Report does not make any sense
By
1/3/2020 9:41:54 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
154
231
SIP to Allegro pcb designer 17.2 ver
By
1/28/2020 5:25:18 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
628
1096
Simvision
By
1/10/2020 10:57:23 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
431
1018
control verilog search path in virtuoso "check"
By
1/28/2020 10:30:05 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8522
22963
NPTH hole not visible on 3D Viewer
By
1/28/2020 10:30:11 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1523
4818
Reports of Cline segment.
By
1/28/2020 8:01:18 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
3
8
appCell demo library (add-on to CDNLive EMEA 2019 CUS-Techtorial V)
By
6/10/2019 10:35:20 PM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
811
2608
Powering a circuit with a rectifier
By
1/28/2020 1:10:47 PM
Verification IP
17
2
I have a question about UVM_INFO in my output log file
By
1/27/2020 6:40:55 AM

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News, FAQs, and related info about how to best use the community.
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Want to find a bride?
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1/28/2020 10:10:40 PM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
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how to connect external cassandra service with cadence
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1/20/2020 3:47:43 AM

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