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Cadence Technology Forums

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Custom IC Design
Moderator: Andrew Beckett.
5092
15560
alter option
By
9/21/2018 7:07:47 AM
Custom IC SKILL
Moderator: Andrew Beckett.
3777
13114
Saving node voltages in Cadence
By
9/22/2018 4:42:25 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2069
4103
how to reduce power in post layout simulation
By
9/16/2018 10:56:41 PM
Functional Verification
Moderator: Adam Sherer
1501
3154
How do I exclude my CPU netlist from probe?
By
9/13/2018 6:40:38 PM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
57
166
help for $sscanf
By
4/21/2016 9:03:22 PM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
286
306
A Guide to Build A Mini Guitar/Audio Amplifier Based on LM386
By
3/29/2018 3:05:29 AM
High-Level Synthesis
Moderator: Dave Pursley
21
36
set_multicycle_path using clock enable signals
By
6/12/2018 2:46:10 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
136
209
How to simulate a fully differential input/output buffer .ibis model in Cadence Virtuoso?!
By
6/11/2018 5:05:27 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
605
1085
Irun driver contention with SystemVerilog port defaults (15.20.001)
By
8/2/2018 2:45:01 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
346
782
Spectre simulation with schematic in Verilog-A
By
9/22/2018 6:49:16 AM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
7723
20775
Calculation of microstrip impedance in topology extraction (Allegro PCB SI)
By
9/21/2018 3:18:42 AM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1382
4334
axlDBGetDesign()->pins returns nil?
By
9/17/2018 7:42:33 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
16
40
Ravel DRC makrer on dielectric layer
By
6/29/2018 10:36:14 AM
RF Design
Moderator: Andrew Beckett.
701
2149
GPDK090 I V characteristics
By
9/10/2018 5:32:23 AM
Verification IP
3
0
NC Verilog issue
By
9/18/2018 11:55:43 PM

General Topics

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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
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Need help fast? Check out Cadence Training Bytes
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6/8/2018 9:25:08 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
336
413
Developing an Idea
By
9/14/2018 1:45:43 PM
Jobs
Post jobs announcements related primarily, but not exclusively, to jobs utilizing Cadence design tools.
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Looking for CAD/PCB Librarian in Costa Mesa, CA
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4/25/2018 10:47:31 AM

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