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Cadence Technology Forums

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Custom IC Design
Moderator: Andrew Beckett.
5737
17656
Hspice replacement for Switch from AnalogLib
By
11/17/2019 12:59:11 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4212
14614
How do I code a skill statement that changes the pin in the input direction to the output direction?
By
11/14/2019 6:57:30 AM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2147
4169
Varying a digital IIR filter's poles&zeros over time
By
11/14/2019 6:24:53 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1587
3374
Design library not defined while reading module with ncsim
By
10/25/2019 10:14:22 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
59
115
Creating cover items for sparse values/queue or define in specman
By
7/15/2019 8:51:51 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
291
311
Arduino: how to save the dynamic memory?
By
11/5/2019 11:25:31 PM
High-Level Synthesis
Moderator: Dave Pursley
25
50
High level synthesis
By
9/12/2019 4:49:13 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
152
224
Chiplet Interface for Heterogeneous SiP
By
10/17/2019 12:38:18 AM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
624
1094
Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC
By
11/14/2019 11:13:48 AM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
416
981
Is it possible to create and simulate SystemC cell view within Virtuoso ADE environment
By
11/6/2019 1:05:31 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
8372
22600
Using Orcad SIGNAL_MODEL attribute?.
By
11/16/2019 9:15:44 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1504
4773
PCB Design: Python Scripts: PCB Skill
By
11/16/2019 11:14:37 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
3
8
appCell demo library (add-on to CDNLive EMEA 2019 CUS-Techtorial V)
By
6/10/2019 10:35:20 PM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
793
2528
Modulated PXF results are confusing
By
11/14/2019 5:35:30 PM
Verification IP
11
2
Send SetAddress from VIP Host to VIP device via usb 2.0 4-port hub (du
By
10/8/2019 4:42:03 AM

General Topics

Forum Name
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Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
83
9
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
342
430
Hardware section for technical forum
By
7/17/2019 6:00:17 AM

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