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Forum Name
Topics
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Last Post
Custom IC Design
Moderator: Andrew Beckett.
6616
20941
Using variables with spectrumMeas
By
5/7/2021 9:47:59 AM
Custom IC SKILL
Moderator: Andrew Beckett.
4643
16009
add customized button and field to ADE L analyses form
By
5/7/2021 12:38:29 PM
Digital Implementation
Design Planning, Place-and-Route, Low Power Implementation, Signoff
Moderator: Bob, Kari, Vince Pham
2218
4223
Netclass and Netgroup in Innovus
By
5/5/2021 7:40:23 AM
Functional Verification
Moderators: Adam Sherer, Steve Hobbs
1664
3546
How to avoid rounding during the force of a real variable
By
4/26/2021 11:55:42 AM
Functional Verification Shared Code
Upload your code here. Please give a brief summary of how to use it.
61
119
How to verify the functionality of synthesized netlist ?
By
3/25/2021 1:56:38 AM
Hardware/Software Co-Development, Verification and Integration
Moderator: Frank Schirrmeister
295
315
Issue With Loudness Normalization
By
1/22/2021 6:01:38 AM
High-Level Synthesis
Moderator: Dave Pursley
34
26
How to change font size for help/menus ?
By
2/11/2021 8:06:26 AM
IC Packaging and SiP Design
Packaging solutions can make or break the cost budget. What design issues are you facing today?
174
304
How do you create a footprint symbol for a DIE that will be referenced in system capture schematic?
By
5/5/2021 1:21:51 PM
Logic Design
Synthesis, Equivalence Checking, Low Power Validation, Test
Moderator: Diego Hammerschlag, Vince Pham, Lisa
652
1116
Compiling Xilinx libraries using Xcleium
By
4/10/2021 9:25:34 PM
Mixed-Signal Design
This Forum is in place to cover and discuss cross functional topics you may encounter designing and layout a Mixed-Signal Design.
Moderator: Andrew Beckett
509
1304
Using "cross" function (or an equivalent) in AC sim
By
5/7/2021 7:15:53 PM
PCB Design
From schematic to autorouting what are your challenges in producing high-speed designs?
9231
25033
DDR4 Trace Length Matching with Via Z-Axis Delay and Via-In-Pad
By
5/7/2021 8:13:59 PM
PCB SKILL
Upload your SKILL files here. Give a brief summary of how to best use the SKILL code.
1676
5131
How to store association table in attachment
By
5/7/2021 12:44:58 PM
PCell Designer
Questions about development of PCells, Module PCells and App Cells using the Cadence PCell Designer product as well as a place to share examples.
Moderator: Andrew Beckett
8
31
How to redefine methods
By
9/3/2020 7:48:40 AM
RAVEL DRC Programming for IC Packaging and PCB
Everything related to ICP & PCB DRC rule programming in the RAVEL language. Topics concerning the RAVEL engine and compiler as well as RAVEL flows and integration are also appropriate.
Moderator: Bjoern Lindberg
17
41
fiducial holes creation
By
12/17/2018 12:39:52 AM
RF Design
Moderator: Andrew Beckett.
908
3002
Generating a pulse signal with specific duty cycle using AWR Cadence
By
4/13/2021 9:41:37 AM
Verification IP
25
5
User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification
By
10/4/2020 10:18:15 PM

General Topics

Forum Name
Topics
Replies
Last Post
Announcements
News, FAQs, and related info about how to best use the community.
Moderators: Community Operations
81
6
International Journal of Embedded Systems and Applications (IJESA)
By
11/11/2019 7:50:22 AM
Feedback, Suggestions, and Questions
Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.
Moderator: Community Operations
354
470
Print IC layout in cadence virtuoso
By
5/6/2021 9:53:45 AM

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