High-Level Synthesis Forums

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Power consumption per clock cycle using Genus
started by on 30 Jan 2019 9:13 AM
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30 Jan 2019 9:13 AM
Unable to map design without a suitable latch. [MAP-3] [synthesize]
started by on 25 Apr 2013 6:46 AM
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28 Nov 2018 2:07 AM
Genus - Segmentation Fault
started by on 3 Oct 2018 3:38 AM
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3 Oct 2018 3:38 AM
set_multicycle_path using clock enable signals
started by on 12 Jun 2018 2:46 AM
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12 Jun 2018 2:46 AM
(Cadence Genus Synthesis) How to use more than one library file for synthesis?
started by on 13 Apr 2018 5:29 AM
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13 Apr 2018 5:29 AM
Synthesis Area plus power estimate concatenation
started by on 7 Feb 2018 9:59 AM
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16 Feb 2018 3:53 AM
Domino Logic Synthesis using Genus
started by on 22 Jan 2018 8:35 AM
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22 Jan 2018 8:35 AM
systemC motion detector
started by on 28 Apr 2017 12:05 AM
1
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26 Oct 2017 7:00 AM
ERROR (CTOS-13110): Internal error
started by on 27 Oct 2014 4:04 AM
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2 Aug 2017 4:52 AM
inserting scan chain - DFT
started by on 22 May 2017 11:31 PM
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22 May 2017 11:31 PM
Welcome to High Level Synthesis Forum
started by on 17 Jul 2012 11:56 AM
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28 Apr 2017 12:34 AM
Does RTL compiler support Tempus commands
started by on 14 Apr 2017 3:25 PM
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14 Apr 2017 3:25 PM
create_clock constraint for Tempus
started by on 14 Nov 2016 1:53 PM
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14 Nov 2016 1:53 PM
MaskCompose Reticle and Wafer Synthesis Suite Information
started by on 21 Apr 2016 11:46 AM
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21 Apr 2016 11:46 AM
ERROR(CTOS-13110): Internal error
started by on 9 Mar 2016 10:36 PM
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9 Mar 2016 10:36 PM

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