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Last Post
High level synthesis
started by
techbud
on 12 Sep 2019 4:49 AM
0
69
By
techbud
12 Sep 2019 4:49 AM
Unable to map design without a suitable latch. [MAP-3] [synthesize]
started by
20050710212
on 25 Apr 2013 6:46 AM
25
194868
By
Ewan John
4 Sep 2019 10:18 PM
Synthesis Area plus power estimate concatenation
started by
GioFz
on 7 Feb 2018 9:59 AM
11
47591
By
wickjohn
23 Aug 2019 6:07 AM
Synthesize net to flip-flop cell with differential output.
started by
RemyP
on 22 Jun 2019 3:47 PM
0
1193
By
RemyP
22 Jun 2019 3:47 PM
Stratus PnR Configs
started by
kvasa
on 20 May 2019 5:14 AM
0
1037
By
kvasa
20 May 2019 5:14 AM
Domino Logic Synthesis using Genus
started by
Schriek
on 22 Jan 2018 8:35 AM
1
9133
By
Ayande
9 Mar 2019 8:36 AM
Genus - Segmentation Fault
started by
nokta
on 3 Oct 2018 3:38 AM
0
1710
By
nokta
3 Oct 2018 3:38 AM
set_multicycle_path using clock enable signals
started by
Hildebrandt
on 12 Jun 2018 2:46 AM
0
6143
By
Hildebrandt
12 Jun 2018 2:46 AM
(Cadence Genus Synthesis) How to use more than one library file for synthesis?
started by
Raveen Kumar
on 13 Apr 2018 5:29 AM
0
7250
By
Raveen Kumar
13 Apr 2018 5:29 AM
systemC motion detector
started by
yosri
on 28 Apr 2017 12:05 AM
1
26847
By
dpursley
26 Oct 2017 7:00 AM
ERROR (CTOS-13110): Internal error
started by
Ahmad Obeid
on 27 Oct 2014 4:04 AM
1
85861
By
hamze60
2 Aug 2017 4:52 AM
inserting scan chain - DFT
started by
subashrajam
on 22 May 2017 11:31 PM
0
16309
By
subashrajam
22 May 2017 11:31 PM
Welcome to High Level Synthesis Forum
started by
rradhakr
on 17 Jul 2012 11:56 AM
1
84090
By
yosri
28 Apr 2017 12:34 AM
Does RTL compiler support Tempus commands
started by
MickeySingh
on 14 Apr 2017 3:25 PM
0
17748
By
MickeySingh
14 Apr 2017 3:25 PM
create_clock constraint for Tempus
started by
MickeySingh
on 14 Nov 2016 1:53 PM
0
23003
By
MickeySingh
14 Nov 2016 1:53 PM
>
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