High-Level Synthesis Forums

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Domino Logic Synthesis using Genus
started by on 22 Jan 2018 8:35 AM
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19 Sep 2020 1:22 AM
Why does Stratus HLS report this error?
started by on 2 Sep 2020 10:18 PM
0
201
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2 Sep 2020 10:18 PM
Using Cadence Genus withou any libraries
started by on 6 Mar 2020 10:24 AM
1
2910
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1 Apr 2020 1:33 AM
Unable to map design without a suitable latch. [MAP-3] [synthesize]
started by on 25 Apr 2013 6:46 AM
26
202089
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24 Mar 2020 7:46 AM
Synthesis Area plus power estimate concatenation
started by on 7 Feb 2018 9:59 AM
12
53538
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19 Feb 2020 10:06 PM
Genus Synthesis Timing Report does not make any sense
started by on 3 Jan 2020 9:41 AM
0
2690
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3 Jan 2020 9:41 AM
High level synthesis
started by on 12 Sep 2019 4:49 AM
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3348
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12 Sep 2019 4:49 AM
Synthesize net to flip-flop cell with differential output.
started by on 22 Jun 2019 3:47 PM
0
4405
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22 Jun 2019 3:47 PM
Stratus PnR Configs
started by on 20 May 2019 5:14 AM
0
4226
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20 May 2019 5:14 AM
Genus - Segmentation Fault
started by on 3 Oct 2018 3:38 AM
0
2531
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3 Oct 2018 3:38 AM
set_multicycle_path using clock enable signals
started by on 12 Jun 2018 2:46 AM
0
9716
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12 Jun 2018 2:46 AM
(Cadence Genus Synthesis) How to use more than one library file for synthesis?
started by on 13 Apr 2018 5:29 AM
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13 Apr 2018 5:29 AM
systemC motion detector
started by on 28 Apr 2017 12:05 AM
1
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26 Oct 2017 7:00 AM
ERROR (CTOS-13110): Internal error
started by on 27 Oct 2014 4:04 AM
1
89323
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2 Aug 2017 4:52 AM
inserting scan chain - DFT
started by on 22 May 2017 11:31 PM
0
17179
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22 May 2017 11:31 PM

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