High-Level Synthesis Forums

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Unable to map design without a suitable latch. [MAP-3] [synthesize]
started by on 25 Apr 2013 6:46 AM
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28 Jan 2020 2:22 AM
Genus Synthesis Timing Report does not make any sense
started by on 3 Jan 2020 9:41 AM
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236
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3 Jan 2020 9:41 AM
High level synthesis
started by on 12 Sep 2019 4:49 AM
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1019
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12 Sep 2019 4:49 AM
Synthesis Area plus power estimate concatenation
started by on 7 Feb 2018 9:59 AM
11
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23 Aug 2019 6:07 AM
Synthesize net to flip-flop cell with differential output.
started by on 22 Jun 2019 3:47 PM
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22 Jun 2019 3:47 PM
Stratus PnR Configs
started by on 20 May 2019 5:14 AM
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20 May 2019 5:14 AM
Domino Logic Synthesis using Genus
started by on 22 Jan 2018 8:35 AM
1
10091
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9 Mar 2019 8:36 AM
Genus - Segmentation Fault
started by on 3 Oct 2018 3:38 AM
0
1935
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3 Oct 2018 3:38 AM
set_multicycle_path using clock enable signals
started by on 12 Jun 2018 2:46 AM
0
7201
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12 Jun 2018 2:46 AM
(Cadence Genus Synthesis) How to use more than one library file for synthesis?
started by on 13 Apr 2018 5:29 AM
0
8499
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13 Apr 2018 5:29 AM
systemC motion detector
started by on 28 Apr 2017 12:05 AM
1
27784
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26 Oct 2017 7:00 AM
ERROR (CTOS-13110): Internal error
started by on 27 Oct 2014 4:04 AM
1
86819
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2 Aug 2017 4:52 AM
inserting scan chain - DFT
started by on 22 May 2017 11:31 PM
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16528
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22 May 2017 11:31 PM
Welcome to High Level Synthesis Forum
started by on 17 Jul 2012 11:56 AM
1
85090
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28 Apr 2017 12:34 AM
Does RTL compiler support Tempus commands
started by on 14 Apr 2017 3:25 PM
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14 Apr 2017 3:25 PM

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