How to generate Verilog Library with verilog submodules in Stratus?

Hi!

I'm doing co-sim in Stratus which has a struct that involves both the Generated Verilog and also the imported Verilog modules.

I generated the verilog library used the command like below:

>> bdw_import_verilog -hls_lib "./my_hls_lib/" -clocks "clk" -resets "rst_n" -vfiles "top.sv sub1.sv sub2.sv"

where: the sub1.sv and the sub2.sv are the submodules of top.sv. But if I use this library in the co-sim project, the error below had been came out:

>> xmelab: *E,CUVMUR (top.sv,72|15): instance 'sc_main.system.m_xxxx.xxxx.xxxx0@xxxx<module>.top@top<module>.i_sub1' of design unit 'r_y_top' is unresolved in 'V.sub1:sv'.

>> xmelab: *E,CUVMUR (top.sv,72|15): instance 'sc_main.system.m_xxxx.xxxx.xxxx0@xxxx<module>.top@top<module>.i_sub2' of design unit 'r_y_top' is unresolved in 'V.sub2:sv'.

Now I have to write the sub1 and sub2 modules into top.sv to make the co-sim work. But this is not convenient.

So how to generate the verilog library with top and also submodules in separated .sv files?

Looking forward to your reply.

Thanks!