Verification IP

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use avip (tba mode ) on pz2， warning CTL socket cannot execute control from HW and did not find scope axiMaster.vr_axi_master_bfm.ctl_socket ,and Stuck in “wait reset done”

Category: Verification IP

By FQ202507317042

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started 1 day ago

0 replies • 48 views
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How to implement a basic clean read-write sequence in Specman? Is this approach correct?

Category: Verification IP

By AP202508036621

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started 2 months ago

0 replies • 387 views
Discussion

Formal Verification IVA method.

Category: Verification IP

By AP202411193629

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started 6 months ago

0 replies • 607 views
Discussion

How to Become a Certified Fraud Examiner (CFE) with Comprehensive Study Materials

Category: Verification IP

By Marc54

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started over 1 year ago

0 replies • 2664 views
Discussion

UCIe and other specs

Category: Verification IP

By masamasa

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started over 2 years ago

0 replies • 4635 views
Discussion

VoltusFi temperature settings

Category: Verification IP

By dakuang01

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started over 2 years ago

0 replies • 4748 views
Discussion

UCIe: Enabling the Chiplet-based Ecosystem

Category: Verification IP

By JHarshit

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started over 2 years ago

0 replies • 6692 views
Discussion

Can't drive the Slave Active AXI Stream Tready signal

Category: Verification IP

By TomasPrudente

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started over 2 years ago

0 replies • 1914 views
Discussion

Ec-council Certified Ethical Hacker (CEHv12) 312-50v12 Dumps

Category: Verification IP

By karonbill

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started over 2 years ago

0 replies • 7235 views
Discussion

H12-711_V4.0-ENU HCIA-Security V4.0 Exam Dumps

Category: Verification IP

By karonbill

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started over 2 years ago

0 replies • 6750 views
Discussion

test flow in the specman for calling start_test()

Category: Verification IP

By muku1kr

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started over 3 years ago

0 replies • 7621 views
Discussion

+escchars option meaning

Category: Verification IP

By markris

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started over 3 years ago

0 replies • 7944 views
Discussion

Regular expressions for keeping

Category: Verification IP

By LorincAntoni

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started over 3 years ago

0 replies • 8368 views
Discussion

Jasper Gold - System Verilog Assertion Prove time estimation

Category: Verification IP

By Shahidhussain

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started over 3 years ago

0 replies • 4834 views
Discussion

Driving a spectra /spice (analog) schematic from xcelium

Category: Verification IP

By pnpras

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started over 3 years ago

0 replies • 9711 views

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