Asynchronous Reset Assertion

I am a beginner in FPV and I have a scenario. Active low reset is asynchronously asserted in my design. When doing formal property verification, after running the tcl file, that is after running the " analyze command", and doing reset analysis, I am able to see the "reset" is applied on the internal registers. But while writing property for it, it is giving me vacuous success/pass. Antecedent is not triggering.

The property I write for asynchronous reset. Does the JG FPV automatically assert the reset at first cycle and then deassert it after one cycle

property async_resetn_prop_chk;
@(negedge PRESETn)
!(PRESETn) |-> (reg_ctrl == 4'h0);    // internal register
endproperty

Kindly suggest.