Functional Verification Forums

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How to get the output from this button in Simvison(counts of edge, high/low time...) by tcl command?
started by on 13 Jul 2018 12:48 AM
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13 Jul 2018 12:48 AM
Interface port coercion
started by on 11 Jul 2018 8:28 AM
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12 Jul 2018 12:35 AM
ERROR: ncvlog: *E,EXPRLC (/file/hierarchy/**.sv,14|18): expecting a left brace ('{') [SystemVerilog]. (Prohibited pattern (?-xism:\*E,))
started by on 11 Jul 2018 10:39 AM
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53
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11 Jul 2018 10:39 AM
Constraints for multidimensional array
started by on 9 Jul 2018 7:16 AM
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173
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10 Jul 2018 4:57 AM
How to remove multiple Markers quickly in Simvision?
started by on 9 Jul 2018 7:09 PM
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132
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10 Jul 2018 2:18 AM
Specman - init a param value of internal sequence (execute from another sequence) directly from test
started by on 8 Jul 2018 11:27 PM
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119
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8 Jul 2018 11:27 PM
How to query if a database has been opened in Simvision with tcl command?
started by on 3 Jul 2018 11:07 PM
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197
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5 Jul 2018 1:28 AM
Can we create directories using the code we write in Ocean script?
started by on 2 Jul 2018 10:39 AM
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163
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2 Jul 2018 10:39 AM
Using strings in constraints to randomize data
started by on 21 Jun 2018 5:44 AM
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313
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21 Jun 2018 8:19 AM
cannot pass uvm_sequence_item to send_to_dut
started by on 16 Jun 2018 3:28 AM
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325
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18 Jun 2018 8:10 AM
Create Functional Verilog from Schematic.
started by on 15 Jun 2018 6:52 AM
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298
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18 Jun 2018 4:17 AM
vManager API
started by on 20 May 2016 5:29 AM
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47896
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15 Jun 2018 3:06 AM
Unable to simulate Verilog Testbench - 'lic_error-18'
started by on 10 Jun 2018 11:10 PM
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274
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14 Jun 2018 1:23 AM
How to use uvm_agent for sequencing
started by on 1 Jun 2018 7:39 AM
4
578
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4 Jun 2018 5:48 AM
Multi Dimensional Dynamic Array Constraint support Issue in System Verilog/UVM
started by on 7 May 2018 10:20 PM
3
720
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30 May 2018 4:09 AM

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