Functional Verification Forums

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[JasperGold] Behavioral Analysis - How to exercise it properly?
started by on 8 Jul 2020 11:15 AM
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8 Jul 2020 11:15 AM
generate over a loop the same module with different parameter and maintain it in systemverilog UVM environment
started by on 1 Jul 2020 5:17 AM
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508
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1 Jul 2020 7:28 AM
Does driver trace through system verilog interfaces ever work?
started by on 24 Jun 2020 7:34 PM
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950
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25 Jun 2020 7:24 AM
Lint errors
started by on 23 Jun 2020 5:58 AM
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930
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23 Jun 2020 5:58 AM
irun & ncvlog version conflict
started by on 18 May 2012 3:16 AM
3
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16 Jun 2020 11:40 PM
Excluding unused functions in JasperGold Superlint
started by on 14 Jun 2020 10:04 PM
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1347
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14 Jun 2020 10:04 PM
How do we extract a full path design from Scoreboard when there is a `uvm_error?
started by on 31 May 2020 3:11 AM
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2104
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5 Jun 2020 2:03 AM
VManager : Increase and Decrease the number of parallel runs in the on-going running sessions.
started by on 11 May 2020 6:20 AM
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2238
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5 Jun 2020 1:30 AM
Can Cadence Incisive Enterprise Verifier be used for functional verification?
started by on 16 May 2020 10:05 AM
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2136
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18 May 2020 1:19 AM
Add a button to specview?
started by on 13 May 2020 11:46 PM
3
2245
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14 May 2020 2:07 AM
Portable Stmulus tool Perspec System Verifier
started by on 10 May 2020 1:51 PM
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2242
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11 May 2020 1:21 AM
ncsim: *E,FLTIGF: [FLT] Failed to inject fault at NET
started by on 9 May 2020 9:40 AM
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1838
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11 May 2020 1:10 AM
How to get product to license feature mapping information?
started by on 5 May 2020 8:45 PM
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2525
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7 May 2020 1:20 AM
Post synthesis simulation with XCELIUM - SDF
started by on 11 Apr 2020 5:27 AM
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2050
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17 Apr 2020 1:23 AM
Binding systemverilog modules (module ports' directions)
started by on 19 Aug 2014 3:49 AM
8
60622
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9 Apr 2020 9:07 AM

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