Functional Verification Forums

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Is it possible to create two vcd files during the same simulation
started by on 17 Dec 2018 12:58 AM
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17 Dec 2018 1:28 AM
how to enlarge simulation time limit of ncsim?
started by on 12 Dec 2018 12:11 AM
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166
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13 Dec 2018 6:22 PM
How to suppress glitch caused by Expression Calculator in Simvision?
started by on 11 Dec 2018 6:36 PM
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127
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11 Dec 2018 6:36 PM
Download documentation from Cadence page
started by on 10 Dec 2018 6:38 PM
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210
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11 Dec 2018 1:09 AM
Grammar of language E about check that
started by on 3 Dec 2018 7:38 PM
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4 Dec 2018 10:32 PM
Jasper Gold formal connectivity verification :: Reverse connectivity generated report contains duplicate connections
started by on 28 Nov 2018 11:09 PM
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682
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4 Dec 2018 5:44 AM
Cadence Spectre Design Simulation
started by on 21 Nov 2018 4:46 PM
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714
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21 Nov 2018 4:46 PM
Does irun support interface classes (SV 1800-2012) ?
started by on 20 Nov 2018 5:15 AM
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1400
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20 Nov 2018 7:10 AM
-access option in irun
started by on 17 Nov 2018 3:40 PM
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1679
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18 Nov 2018 3:05 PM
How do I control probe start/stop in ncsim from embedded CPU?
started by on 18 Oct 2018 6:32 PM
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2633
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12 Nov 2018 5:41 PM
Statement coverage is n/a after running and merging testcase coverage results
started by on 5 Nov 2018 4:28 AM
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4148
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8 Nov 2018 6:06 AM
Getting Elaboration Error *E,BIGOBJ
started by on 8 Nov 2018 1:28 AM
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2111
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8 Nov 2018 4:43 AM
Compilation error with xcelium
started by on 8 Nov 2018 3:37 AM
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8 Nov 2018 3:46 AM
Verilog generics on vhdl instances
started by on 30 Sep 2013 7:52 AM
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53796
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31 Oct 2018 7:19 AM
Query regarding the ncelab: *F,CUHUNL fatal
started by on 26 Oct 2018 5:49 PM
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1159
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26 Oct 2018 5:49 PM

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