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Functional Verification

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  • Discussion

    Windows/ Mac compatibility for Cadence softwares

    Category: Functional Verification

    By asiddharthrao asiddharthrao

    •

    updated 9 hours ago by StephenH

    1 replies • 42 views
  • Discussion

    xcellium compiles every RTL hierarchy into a "library_cell", how do I get rid of that?

    Category: Functional Verification

    By mxlusereight mxlusereight

    •

    updated 2 days ago by mxlusereight

    2 replies • 65 views
  • Discussion

    simvision

    Category: Functional Verification

    By schetan schetan

    •

    started 8 days ago

    0 replies • 85 views
  • Discussion

    Error : lps_1801 elaboration : *E,MTOMDU : More than one unit matches 'TESTBENCH'

    Category: Functional Verification

    By Zero00 Zero00

    •

    updated 13 days ago by Zero00

    4 replies • 157 views
  • Discussion

    <EE> ERROR: VRsrc instance behavioral_modelling_doubler_full.I26.S0o node P unconverged at T=125005ns

    Category: Functional Verification

    By swethasam swethasam

    •

    started 16 days ago

    0 replies • 25 views
  • Discussion

    unable to simulate VHDL record constant assignment through component port

    Category: Functional Verification

    By Hunen Hunen

    •

    updated 28 days ago by tpylant

    3 replies • 319 views
  • Discussion

    Can queues be used to drive RTL?

    Category: Functional Verification

    By shareefj shareefj

    •

    updated 29 days ago by shareefj

    5 replies • 370 views
  • Discussion

    Xcelium: Link a third-party library to your simulation

    Category: Functional Verification

    By Anas2023a95 Anas2023a95

    •

    updated 1 month ago by StephenH

    10 replies • 942 views
  • Discussion

    Jaspergold -- Net does not have a driver

    Category: Functional Verification

    By Vivek Kakkireni Vivek Kakkireni

    •

    started 1 month ago

    0 replies • 170 views
  • Discussion

    Why does simvision sometimes causes the desktop freezed?

    Category: Functional Verification

    By aICer aICer

    •

    updated 1 month ago by HoWei

    5 replies • 1930 views
  • Discussion

    Create image from vcd file

    Category: Functional Verification

    By PontusT PontusT

    •

    updated 1 month ago by PontusT

    3 replies • 647 views
  • Discussion

    Internal SV signal not created properly when simulated with xrun/simvision

    Category: Functional Verification

    By HoWei HoWei

    •

    started 1 month ago

    0 replies • 142 views
  • Discussion

    SystemVerilog task() output signal does not have correct value

    Category: Functional Verification

    By HoWei HoWei

    •

    updated 2 months ago by HoWei

    4 replies • 724 views
  • Discussion

    Enabling code coverage deeper into SV function calls

    Category: Functional Verification

    By efisherdukosi efisherdukosi

    •

    updated 2 months ago by efisherdukosi

    5 replies • 823 views
  • Discussion

    Merge command error

    Category: Functional Verification

    By Rakeshp97 Rakeshp97

    •

    updated 2 months ago by StephenH

    3 replies • 713 views
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