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Functional Verification Forums

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Running SVA for a VHDL design (binding method)
started by on 19 Jul 2021 9:40 AM
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26 Jul 2021 1:50 AM
Crossbararray in Veriloga with for loop
started by on 12 Jul 2021 1:28 PM
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12 Jul 2021 1:28 PM
How to use variable array in laplace_nd function?
started by on 7 Jul 2021 1:05 AM
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283
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7 Jul 2021 1:05 AM
Print only the file name and exclude file path getting printed in the log file
started by on 4 Jul 2021 10:19 PM
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299
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4 Jul 2021 10:19 PM
[vManager] Questions about Exclude options for Code coverage improvement
started by on 27 Jun 2021 11:51 PM
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382
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27 Jun 2021 11:51 PM
convert analog bit to signed decimal with analog bits
started by on 26 Jun 2021 10:57 AM
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368
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26 Jun 2021 10:57 AM
probe tcl syntax to save variables inside automatic tasks in systemverilog
started by on 16 Jun 2021 11:46 PM
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493
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16 Jun 2021 11:46 PM
convert bus sıgnal
started by on 5 Jun 2021 1:59 PM
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224
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5 Jun 2021 1:59 PM
SEC RTL vs Gatelevel
started by on 18 May 2021 12:05 PM
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18 May 2021 1:16 PM
Simvision: xmsim: *E,TRRANGEC: range constraint violation
started by on 10 May 2021 4:58 AM
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360
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10 May 2021 4:58 AM
license search order in Xcelium
started by on 23 Apr 2021 4:19 PM
2
1113
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4 May 2021 8:54 AM
How to avoid rounding during the force of a real variable
started by on 26 Apr 2021 11:55 AM
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990
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26 Apr 2021 11:55 AM
JasperGold SAT solver capacity
started by on 15 Apr 2021 12:38 AM
2
1294
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17 Apr 2021 3:32 AM
Prevent SimVision Schematic Viewer from Re-Zooming/Centering after tracing a signal?
started by on 31 Mar 2021 1:31 AM
1
585
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31 Mar 2021 5:23 AM
IEEE float radix in Simvision
started by on 14 Mar 2021 6:25 AM
11
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15 Mar 2021 5:36 AM

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