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How should analog reference outputs be modeled in a pure Verilog REFGEN/BIASGEN cell?

AT202609033946 10 days ago

Hi,

I am developing a behavioral Verilog model for an IO REFGEN/BIASGEN cell.

In silicon, the cell generates different analog reference voltages:

-Biasp = 2.2V when Enable = high

- Biasp = 3.3V when Enable =low

The model is intended for use in pure digital RTL/gate-level simulations, not Verilog-AMS or mixed-signal simulations.

Since standard Verilog only supports digital values (0, 1, X, Z), what is the recommended industry practice for modeling such analog reference outputs?

Would both 1.5V and 3.3V typically be abstracted as logic '1'?

Any guidance, modeling practices suggested would be appreciated.

Thanks.

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