Mixed-Signal Design Forums

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Welcome to the Cadence Mixed-Signal Forum!
started by on 9 Nov 2012 7:26 AM
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35804
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9 Nov 2012 7:26 AM
control verilog search path in virtuoso "check"
started by on 28 Jan 2020 10:30 AM
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28 Jan 2020 10:30 AM
vector net cannot be connected to a spice/spectre instance by port name
started by on 26 Dec 2019 11:33 AM
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27 Jan 2020 1:16 AM
How to use +sv option in AMS simulation
started by on 22 Jan 2020 4:01 PM
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129
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23 Jan 2020 11:44 AM
schematic that uses spectre M_TWO_PI unhappy in ams
started by on 16 Jan 2020 5:19 AM
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16 Jan 2020 5:59 AM
DNL/INL Using Cadence ahdlLib blocks for ADC
started by on 20 Jul 2019 5:45 PM
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706
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15 Jan 2020 6:41 AM
Calling one macro within another macro in Verilog-a
started by on 13 Jan 2020 4:22 AM
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13 Jan 2020 7:03 AM
Is there an eval command in Verilog-a?
started by on 12 Jan 2020 3:27 AM
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12 Jan 2020 3:45 AM
comparator delay with calculator
started by on 6 Oct 2014 9:42 AM
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12057
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8 Jan 2020 10:32 PM
multiple macro definitions in verilog-a
started by on 6 Jan 2020 5:03 AM
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218
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6 Jan 2020 5:19 AM
Building Config tree for System Verilog Testbench when using external HDL
started by on 15 Dec 2019 8:09 AM
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5 Jan 2020 2:54 AM
timer equivalent for "DC " analysis for verilog-a
started by on 1 Jan 2020 5:21 AM
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1 Jan 2020 8:03 AM
Accessing LINUX environment variables in verilog-AMS/verilog-A
started by on 31 Dec 2019 3:58 AM
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31 Dec 2019 4:37 AM
AMS simulations with DSPF netlist
started by on 26 Dec 2019 3:05 AM
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277
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26 Dec 2019 3:05 AM
bus instances of the AMS netlisting
started by on 18 Dec 2019 4:28 PM
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19 Dec 2019 4:41 PM

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