Mixed-Signal Design Forums

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Welcome to the Cadence Mixed-Signal Forum!
started by on 9 Nov 2012 7:26 AM
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9 Nov 2012 7:26 AM
IP3 Simulation of a Sample and Hold Circuit in Spectre
started by on 26 Mar 2020 4:19 PM
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26 Mar 2020 4:19 PM
PLL Phase noise simulation in Cadence Virtuoso
started by on 29 Feb 2020 10:22 PM
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1 Mar 2020 2:27 AM
how to setup customized rules file to simulation a circuit with 2 level of voltage 1.8v and 3.3v ?
started by on 10 Feb 2020 9:01 AM
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23 Feb 2020 4:34 AM
VCOs with Arbitrary Phase Noise Profile
started by on 18 Feb 2020 8:55 PM
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23 Feb 2020 1:00 AM
Dynamic Comparator Performance Parameter
started by on 17 Feb 2020 12:58 AM
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17 Feb 2020 9:16 AM
comparator delay with calculator
started by on 6 Oct 2014 9:42 AM
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17 Feb 2020 12:38 AM
schematic that uses spectre M_TWO_PI unhappy in ams
started by on 16 Jan 2020 5:19 AM
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10 Feb 2020 4:42 AM
Layout in cadence
started by on 4 Feb 2020 4:16 AM
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6 Feb 2020 3:28 AM
Which errpreset takes precedence, APS accuracy+speed or tran analysis?
started by on 30 Jan 2020 11:05 AM
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31 Jan 2020 4:31 PM
control verilog search path in virtuoso "check"
started by on 28 Jan 2020 10:30 AM
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30 Jan 2020 5:15 AM
Best practices for Verilog-a modelling time variant resistance
started by on 29 Jan 2020 6:54 AM
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30 Jan 2020 2:19 AM
vector net cannot be connected to a spice/spectre instance by port name
started by on 26 Dec 2019 11:33 AM
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27 Jan 2020 1:16 AM
How to use +sv option in AMS simulation
started by on 22 Jan 2020 4:01 PM
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23 Jan 2020 11:44 AM
DNL/INL Using Cadence ahdlLib blocks for ADC
started by on 20 Jul 2019 5:45 PM
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15 Jan 2020 6:41 AM

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