Mixed-Signal Design

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Welcome to the Cadence Mixed-Signal Forum!

Category: Mixed-Signal Design

By admin

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started over 13 years ago

0 replies • 18232 views
Discussion

save AHDL variables

Category: Mixed-Signal Design

By PE202503078250

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updated 1 day ago by Andrew Beckett

3 replies • 162 views
Discussion

Unfamiliar and confused about analog-on-top design flow and tools

Category: Mixed-Signal Design

By JD202506199142

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started 21 days ago

0 replies • 235 views
Discussion

IC6.1.8: Introduction to AMS Designer Simulation ( 10 Oct 2025) - RAK : Issue of NMOS and PMOS transistor not in its range of parameters

Category: Mixed-Signal Design

By CM202508086341

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updated 27 days ago by CM202508086341

2 replies • 268 views
Discussion

Programmable voltage/current sources

Category: Mixed-Signal Design

By LostBoy

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started 1 month ago

0 replies • 144 views
Discussion

Period jitter and TiE Jitter simulations of RC Relaxation Oscillator

Category: Mixed-Signal Design

By GirishW

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started 1 month ago

0 replies • 421 views
Discussion

Including variables from a fil

Category: Mixed-Signal Design

By AA202510057331

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updated 1 month ago by AA202510057331

5 replies • 1349 views
Discussion

rand_bit_stream not reproducible across runs despite setting seed

Category: Mixed-Signal Design

By MB202509174350

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started 1 month ago

0 replies • 459 views
Discussion

Simulation of VerilogA model of a VCO ?

Category: Mixed-Signal Design

By PE202503078250

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updated 2 months ago by Andrew Beckett

4 replies • 1702 views
Discussion

max usage of CPU cores in spectre/aps++ simulation

Category: Mixed-Signal Design

By Tarique mohd

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updated 2 months ago by Andrew Beckett

3 replies • 1565 views
Discussion

DC convergence problem with Basic ring amplifier

Category: Mixed-Signal Design

By SC202503236954

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updated 3 months ago by SC202503236954

2 replies • 1591 views
Discussion

Attach load to a pin for AMS verification

Category: Mixed-Signal Design

By PedroC

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started 3 months ago

0 replies • 1056 views
Discussion

White phase noise in VCO decays with frequency – not flat as expected

Category: Mixed-Signal Design

By brunoalexandrefraga

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updated 4 months ago by Andrew Beckett

1 replies • 1793 views
Discussion

Issue on Running simulation with VerilogA and SystemVerilog in virtuoso - Z output

Category: Mixed-Signal Design

By AmirMasnadi

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updated 5 months ago by engineer27

1 replies • 1069 views
Discussion

Illegal argument for signal access function [4.3(AMSLRM)]. Verilog AMS error.

Category: Mixed-Signal Design

By BS20240726490

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updated 5 months ago by Saloni Chhabra

1 replies • 894 views

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