Mixed-Signal Design Forums

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Welcome to the Cadence Mixed-Signal Forum!
started by on 9 Nov 2012 7:26 AM
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9 Nov 2012 7:26 AM
Spectre simulation with schematic in Verilog-A
started by on 20 Sep 2018 5:28 AM
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20 Sep 2018 5:28 AM
Detecting floating node in schematic in Verilog-A code
started by on 13 Sep 2018 6:49 AM
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18 Sep 2018 3:48 AM
Unable to edit a cellview in a RAK
started by on 17 Sep 2018 9:23 AM
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17 Sep 2018 11:08 AM
How to make schematic CDF parameter become integer in AMS?
started by on 23 Aug 2018 7:01 AM
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7 Sep 2018 7:06 AM
DC offset
started by on 4 Sep 2018 6:08 AM
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5 Sep 2018 1:25 AM
Routing Layers in Cadence Virtuoso
started by on 23 Aug 2018 1:47 PM
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3 Sep 2018 3:46 AM
OCEAN Tutorial
started by on 31 Aug 2018 10:36 PM
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3 Sep 2018 3:15 AM
PSS/PAC and PSTB for Fully Differential SC CMFB Opamps
started by on 3 Sep 2018 1:17 AM
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380
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3 Sep 2018 3:07 AM
Fourier Component in Cadence Virtuoso
started by on 17 Aug 2018 8:02 AM
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608
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17 Aug 2018 10:41 AM
Mixed IC Design Flow Using: Synopsys DC-ICC & Cadence Virtuoso
started by on 17 Aug 2018 12:45 AM
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162
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17 Aug 2018 12:45 AM
Bidir_2 connect module getting "stuck"
started by on 14 Aug 2018 12:10 PM
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178
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14 Aug 2018 12:10 PM
display analog signal voltage in VerilogAMS
started by on 8 Aug 2018 9:13 AM
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10 Aug 2018 2:04 PM
Importing Files from ASITIC (CIF files) Into Cadence
started by on 3 Aug 2018 5:10 PM
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7 Aug 2018 11:12 PM
Is there a way to change the value of a voltage source (or a generic parameter), "during" the execution of an Interactive mode AMS simulation?
started by on 29 Jul 2018 7:49 AM
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29 Jul 2018 7:49 AM

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