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Mixed-Signal Design Forums

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Welcome to the Cadence Mixed-Signal Forum!
started by on 9 Nov 2012 7:26 AM
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9 Nov 2012 7:26 AM
Spice to Spectre conversion
started by on 26 Jul 2021 12:47 PM
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28 Jul 2021 2:39 PM
Running Monte carlo simulations in Process corners(SS,FF..)
started by on 27 Jul 2021 7:34 AM
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27 Jul 2021 7:34 AM
Set initial value for inputs/outputs for verilog cells in mixed-signal simulation (XCELIUM UNL)
started by on 19 Jul 2021 5:27 AM
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20 Jul 2021 1:46 AM
Verilog-A module instantiating
started by on 11 Jun 2014 12:07 AM
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19 Jul 2021 3:28 AM
Does xrun support connection module between nettype and logic?
started by on 12 Jul 2021 2:18 PM
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12 Jul 2021 11:01 PM
In Cadence simulation how to introduce noise in current source
started by on 2 May 2021 12:29 AM
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9 Jul 2021 1:10 AM
Virtuoso: cloning vs unit cell
started by on 1 Jul 2021 1:43 PM
1
355
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2 Jul 2021 3:43 AM
Problem with ahdlcmi module library
started by on 28 Jun 2021 5:40 AM
4
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28 Jun 2021 7:39 AM
File directory if using GUI
started by on 22 Jun 2021 3:03 PM
3
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26 Jun 2021 8:24 AM
Hierarchical calling of VerilogA models
started by on 21 Jun 2021 2:04 AM
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21 Jun 2021 9:22 AM
Missing connectLib
started by on 3 Mar 2015 7:09 PM
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15 Jun 2021 12:40 PM
getData "noise" not listed in calculator
started by on 15 Jun 2021 8:01 AM
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15 Jun 2021 8:07 AM
Error in RCX in Assura
started by on 11 Jun 2021 4:50 AM
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14 Jun 2021 11:21 PM
Multidimensional Array in Verilog-A
started by on 8 Jun 2021 10:07 AM
4
683
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14 Jun 2021 2:53 AM

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