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Welcome to the Cadence Mixed-Signal Forum!
started by on 9 Nov 2012 7:26 AM
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9 Nov 2012 7:26 AM
Error running Liberate_AMS
started by on 24 Apr 2018 8:59 AM
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24 Apr 2018 2:47 PM
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24 Apr 2018 4:28 AM
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23 Apr 2018 4:20 PM
Liberate_AMS for .lib generation.
started by on 15 Mar 2018 10:27 PM
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23 Apr 2018 12:20 AM
Verilog A ADC design
started by on 23 Mar 2018 11:55 AM
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15 Apr 2018 2:43 PM
spectre solver for veriloga
started by on 5 Apr 2018 5:14 AM
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15 Apr 2018 2:28 PM
irun is not recognizing .scs files
started by on 12 Apr 2018 10:15 PM
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13 Apr 2018 12:29 PM
Verilog-A to access wire bus of DUT
started by on 12 Apr 2018 11:27 AM
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248
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13 Apr 2018 3:44 AM
ModGen and Common Centroid Layout
started by on 12 Apr 2018 6:17 PM
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242
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13 Apr 2018 2:01 AM
Missing EEnet connect modules
started by on 3 Apr 2018 4:08 PM
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496
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5 Apr 2018 2:51 PM
PAM4 Signal using ahdllib or bmslib
started by on 21 Mar 2018 9:38 PM
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21 Mar 2018 9:47 PM
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21 Mar 2018 9:36 PM
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21 Mar 2018 9:32 PM

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