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Replacing cell in an analog on top testbench by an external HDL module that has different name

I have an analog-on-top testbench and would like to replace a specific cell with a digital module. The digital module and its submodules are defined in external files without existing cell views. I have included these files via Simulation > Options > AMS Simulator > Include Option Settings.

However, the top module name in the Verilog file differs from the name of the cell view I am replacing. How can I configure the mapping so the tool replaces this cell with the provided Verilog module file?

I am using AMS designer through ADE GUI (AVUM flow)

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