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Bad AMS simulation Accuracy for L2E Conversion

Khalid Eissa

Hello,

I am trying to simulate a PLL circuit where the input clock is coming from a Verilog model (logic) but the phase detector is schematic. So I need to convert this logic signal to electric

The issue is that after L2E conversion I get the electric clock with a delay compared to the logic clock and that delay seem to be random each cycle (subject to simulation step) This adds a lot of phase error to the PLL input and finds its way to the output of the PLL.

I want cadence to somehow always get the electric clock to be as close as possible to the logic clock, something like within 10fs of it or at least have a fixed delay that is not changing with each cycle

I am using Spectre-X CX (highest accuracy)  and I tried different connect-rules like rise/fall times to be as low as 10fs but does not seem to fix the issue. I tried APS as well but does not improve results

Any ideas how to fix this?

  • Khalid Eissa

    For doing L2E I tried the connect rules and also tried inserting a specific Verilog-AMS cell that does the L2E. I tried doing an intermediate conversion to wreal first then convert to voltage. Nothing seem to improve the accuracy at all

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