AMS/SimVision simulation

I simulated a verilog testbench with a module consisting of a synthesized gate level netlist in SimVision. It seems to be working (at least giving an output signal that looks valid)

However when I ran the same simulation in Cadence Virtuoso using the AMS simulator, the output seems to be in the High-Z/undefined state. Is there any simulation setting that I'm missing ? The testbench in Virtuoso doesnt have any analog blocks. All are verilog modules. So then I assume any setting mistakes related to the ConnectModules can be ruled out. However, the RTL code (of the corresponding gate level netlist) indeed works in Virtuoso.