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Mixed-Signal Design

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Latest Posts

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  • Discussion

    Programmable voltage/current sources

    Category: Mixed-Signal Design

    By LostBoy

    •

    started 7 months ago

    0 replies • 826 views
  • Discussion

    Period jitter and TiE Jitter simulations of RC Relaxation Oscillator

    Category: Mixed-Signal Design

    By GirishW

    •

    started 7 months ago

    0 replies • 1932 views
  • Discussion

    Including variables from a fil

    Category: Mixed-Signal Design

    By AA202510057331

    •

    updated 8 months ago by AA202510057331

    5 replies • 6187 views
  • Discussion

    rand_bit_stream not reproducible across runs despite setting seed

    Category: Mixed-Signal Design

    By MB202509174350

    •

    started 8 months ago

    0 replies • 1882 views
  • Discussion

    Simulation of VerilogA model of a VCO ?

    Category: Mixed-Signal Design

    By PE202503078250

    •

    updated 8 months ago by Andrew Beckett

    4 replies • 4325 views
  • Discussion

    max usage of CPU cores in spectre/aps++ simulation

    Category: Mixed-Signal Design

    By Tarique mohd

    •

    updated 9 months ago by Andrew Beckett

    3 replies • 3113 views
  • Discussion

    DC convergence problem with Basic ring amplifier

    Category: Mixed-Signal Design

    By SC202503236954

    •

    updated 9 months ago by SC202503236954

    2 replies • 3434 views
  • Discussion

    Attach load to a pin for AMS verification

    Category: Mixed-Signal Design

    By PedroC

    •

    started 9 months ago

    0 replies • 2409 views
  • Discussion

    White phase noise in VCO decays with frequency – not flat as expected

    Category: Mixed-Signal Design

    By brunoalexandrefraga

    •

    updated 10 months ago by Andrew Beckett

    1 replies • 3760 views
  • Discussion

    Issue on Running simulation with VerilogA and SystemVerilog in virtuoso - Z output

    Category: Mixed-Signal Design

    By AmirMasnadi

    •

    updated 11 months ago by engineer27

    1 replies • 1805 views
  • Discussion

    Illegal argument for signal access function [4.3(AMSLRM)]. Verilog AMS error.

    Category: Mixed-Signal Design

    By BS20240726490

    •

    updated 11 months ago by Saloni Chhabra

    1 replies • 1565 views
  • Discussion

    Help with Accurate Extraction of Ron and Coff for RF Switches in Ku-Band Phase Shifter Design

    Category: Mixed-Signal Design

    By BR202502181318

    •

    started over 1 year ago

    0 replies • 4029 views
  • Discussion

    Phase Interpolator Control

    Category: Mixed-Signal Design

    By JS20250531815

    •

    started over 1 year ago

    0 replies • 3358 views
  • Discussion

    Netlisting error

    Category: Mixed-Signal Design

    By PE202503078250

    •

    started over 1 year ago

    0 replies • 4984 views
  • Discussion

    wreal modeling for inductance and capacitance

    Category: Mixed-Signal Design

    By LS202412014215

    •

    updated over 1 year ago by LS202412014215

    2 replies • 4997 views
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