Mixed-Signal Design

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Discussion

Create an if else expression in ADE Assembler

Category: Mixed-Signal Design

By Aks23

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started over 1 year ago

0 replies • 3613 views
Discussion

std cells snapping and flipping with innovus rows is not working while doing layout using APR.

Category: Mixed-Signal Design

By PA202410304814

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started over 1 year ago

0 replies • 3915 views
Discussion

[AMS][plotting internal signals in a "dspf" netlist]

Category: Mixed-Signal Design

By IssacW

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started over 1 year ago

0 replies • 1449 views
Discussion

PSS + PNOISE simulation（PFD + Charge Pump）

Category: Mixed-Signal Design

By JG202412161044

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started over 1 year ago

0 replies • 1816 views
Discussion

Smith Chart S11 value

Category: Mixed-Signal Design

By mxm14

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updated over 1 year ago by mxm14

3 replies • 5798 views
Discussion

Xcelium not probing signals to waveform window

Category: Mixed-Signal Design

By swetha99

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started over 1 year ago

0 replies • 3955 views
Discussion

Interface with systemVerilogText cell

Category: Mixed-Signal Design

By Doronzzz

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updated over 1 year ago by AW202410302125

1 replies • 4163 views
Discussion

characterization using liberate

Category: Mixed-Signal Design

By TM20240913386

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updated over 1 year ago by Guangjun Cao

7 replies • 7531 views
Discussion

spectre simulation issue

Category: Mixed-Signal Design

By YH202410112147

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updated over 1 year ago by YH202410112147

1 replies • 4438 views
Discussion

does pnoise number of points affect the integrated power?

Category: Mixed-Signal Design

By NewScreenName

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started over 1 year ago

0 replies • 3730 views
Discussion

AMS Simulation: Use SystemVerilog module instantiating other submodules in SystemVerilog

Category: Mixed-Signal Design

By Mathieu Chene

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updated over 1 year ago by Mathieu Chene

4 replies • 6975 views
Discussion

Importing package in AMS simulation

Category: Mixed-Signal Design

By MostafaAbedi

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started over 1 year ago

0 replies • 4246 views
Discussion

Missing pins in symbol creation of systemVerilog module

Category: Mixed-Signal Design

By MostafaAbedi

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updated over 1 year ago by MostafaAbedi

4 replies • 6155 views
Discussion

Why my Verilog‘s digital outputs are correct in Vivado but 'x' in Cadence AMS?

Category: Mixed-Signal Design

By Cookies

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updated over 1 year ago by Cookies

4 replies • 2670 views
Discussion

Liberate-ams GUI error: (LIB-203)

Category: Mixed-Signal Design

By TM20240913386

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updated over 1 year ago by Guangjun Cao

1 replies • 4312 views

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