Mixed-Signal Design

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Discussion

AMS Designer Interface Element automation

Category: Mixed-Signal Design

By AB_1718784850873

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started over 1 year ago

0 replies • 3626 views
Discussion

[dynamic node capacitance check][couldn't find the check results]

Category: Mixed-Signal Design

By IssacW

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updated over 1 year ago by IssacW

3 replies • 1803 views
Discussion

Importing mixed-language design (Verilog + VHDL) in Virtuoso AMS

Category: Mixed-Signal Design

By AB_1719514544766

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updated over 1 year ago by Andrew Beckett

3 replies • 5296 views
Discussion

[explicit parameter sweeping][netlisting/simulation always pending]

Category: Mixed-Signal Design

By IssacW

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updated over 1 year ago by IssacW

9 replies • 3700 views
Discussion

HB simulation with multiple square-wave signal

Category: Mixed-Signal Design

By AB_1719406998389

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updated over 1 year ago by AB_1719406998389

6 replies • 5713 views
Discussion

PSS + PNOISE Simulation Problem for the PLL

Category: Mixed-Signal Design

By MtnDew12fl

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updated over 1 year ago by MtnDew12fl

2 replies • 4551 views
Discussion

[Verilog-AMS][Xcelium version]

Category: Mixed-Signal Design

By IssacW

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updated over 1 year ago by IssacW

6 replies • 4329 views
Discussion

Floorplanning Problems in Mixed-Signal Design with Digital Block Pins Optimization

Category: Mixed-Signal Design

By Layouter5338

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started over 1 year ago

0 replies • 3599 views
Discussion

xmelab: *E,CUVHNF error using Xcelium 19.09-s008

Category: Mixed-Signal Design

By markris

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updated over 1 year ago by markris

4 replies • 3735 views
Discussion

Deepprobe within systemverilog hierarchy

Category: Mixed-Signal Design

By NewScreenName

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updated over 1 year ago by NewScreenName

7 replies • 7225 views
Discussion

how to fix the cdl file import error in virtuoso, please expert help on it.

Category: Mixed-Signal Design

By axlrose2138

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started over 1 year ago

0 replies • 3970 views
Discussion

Virtuoso AMS error

Category: Mixed-Signal Design

By Emily157

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updated over 1 year ago by Emily157

7 replies • 7335 views
Discussion

AMS *F,MAXERR: Maximum error count of 50 reached (Total number of errors detected were 50).

Category: Mixed-Signal Design

By nonameirvine

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started over 1 year ago

0 replies • 1364 views
Discussion

Switched capacitance / Variable capacitor

Category: Mixed-Signal Design

By HHOSSAM

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updated over 1 year ago by Frank Wiedmann

1 replies • 4578 views
Discussion

Compile and elaborate problem with VerilogA blocks in AMS simulation

Category: Mixed-Signal Design

By zhaoyu

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started over 1 year ago

0 replies • 4518 views

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