Elaboration error in AMS simulation

I'm running an AMS simulation. I'm using a maestro view for the simulation. When I run a Monte-Carlo simulation, I get an elaboration error as shown in the log given below. However the nominal corner simulation works fine. I'm wondering why this happens when I just change the corner from nominal to Monte Carlo and simulation run mode from Single Run,Sweeps,Corners to Monte Carlo Sampling.

xmelab: *E,EXANCU: 'pv16e@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: *E,EXANCU: 'npdio@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: *E,EXANCU: 'nregbl@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: *E,EXANCU: 'ncapvaractor@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: *E,EXANCU: 'npdioj@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: *E,EXANCU: 'pregbl@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: *E,EXANCU: 'n1s@wk_paul_nov23TO_sim.TB_QCORDDS:schematic' was configured to be bound to an analog view in Cadence Hierarchy Editor. However, such a cell/instance was not found during design elaboration. It could be because either the specified cell/instance is netlisted using Spectre custom netlist procedure, or some other instance on hierarchical path to this 'capacitor' is netlisted/truncated using custom netlist procedure - which effectively removed this cell/instance of 'capacitor' from the elaborated design. If that is the case, the recommended solution is to set Bind-To-Open on such customized instance on hierarchical path to 'capacitor' instance in Hierarchy Editor. If you continue to see the error after resolving the above scenarios, contact Cadence with the error information.
xmelab: Memory Usage - Final: 39.3M, Peak: 39.3M, Peak virtual: 146.9M
xmelab: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 44.4% cpu)
xrun: *E,ELBERR: Error during elaboration (status 1), exiting.
TOOL: xrun(64) 20.09-s001: Exiting on Aug 07, 2024 at 16:37:14 CEST (total: 00:00:07)

The nominal corner simulation works fine, the similar portion log of the log is shown below.

xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Discipline resolution Pass...
xmelab: *W,IHNOPT: AMS interface element optimization is disabled due to interface elements on inherited connections.
Doing auto-insertion of connection elements...
Connect Rules applied are:
logic_cr
Building instance overlay tables: .................... Done
Using implicit TMP libraries; associated with library wk_paul_nov23TO_sim
Generating native compiled code:

.....