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Assura LVS failed for Mixed-signal design

SaranyaBalan

 I am running a top-level Assura LVS on my mixed-signal design. It has two blocks:
1. an analog block in the DFII environment with schematic, layout and symbol.
2. a digital block in which I have a post-synthesis layout in the DFII environment imported from Innovus.
When I run Assura LVS, I use the DFII as my design source for my layout.
Under Netlisting options, I put in all my verilog and CDL files required to run.
The LVS run fails with the below message in the logs
"Top cell 'Switch_Top' specified, starting from specified point...
nvn: nametbl.cc:58: const char* Assura::NameTable::toStr(NameNum) const: Assertion `aId<=beginLastWord' failed.

Finished /home/install/ASSURA41/tools.lnx86/assura/bin/nvn

*WARNING* An error occurred during Nvn PreExtraction.
LVS preprocessing requires a successful run of Nvn.
Assura will now terminate."
I’m having trouble decoding this error message. Can someone please help me? Thank you!

  • Andrew Beckett

    I found one report of this from 10 years ago and it was resolved by the customer without any information on what they resolved...

    Are you running a recently dated version of Assura?

    Please contact customer support.

    Andrew

  • SaranyaBalan
    in reply to Andrew Beckett

    Thank you for the information.

    To address your question, yes, I am currently running a Assura Release 4.1_USR6_EHF13 version.

    I have already raised a ticket with customer support regarding this issue and will follow up with them for further assistance

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