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Issue on Running simulation with VerilogA and SystemVerilog in virtuoso - Z output

I am trying to run an AMS sim in virtuoso where I do have a systemVerilog block and verilogA block instantiated in schematic view. Each block works fine stand alone but when I make a testbench together the verilogA output is all Z . Any idea what is wrong ?

engineer27 2 months ago

Check your discipline resolution. You may need "detailed" resolution. If you did not set it explicitly, you are likely using "default."

Here are a couple of articles that address the topic:

Article (20498260) Title: How are disciplines assigned/resolved in mixed-signal simulation during elaboration?
URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009EqUZEA0

Article (20485101) Title: Mixed Signal Verification - Connectivity Overview
URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006DfnQUAS
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