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rand_bit_stream not reproducible across runs despite setting seed

MB202509174350

Hi all,

I am building an LVDS RX and so needed a block to supply random data. Virtuoso ADE has a built-in Verilog-A cell called rand_bit_stream.

Even though you can set a seed value, it seems to ignore it. Different simulation runs have a totally different waveform.

Is this a known problem, or am I doing something wrong?

I am using VIrtuoso IC23.1 and Spectre 23.1.0.477.isr8 64bit.

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