AMS: how to probe signals in ADE from a schematic instantiated within a system verilog module

Hello everyone !

I have the following hierarchy for my testbench (from highest to lowest level):

1) a schematic view for my testbench which instantiates a systemverilog instance named DUT

2) inside DUT, I have instantiated a schematic cellview with the following systemverilog syntax:

myModule my_module_inst0 (
    .input_A (signal_A)
);

3) inside my_module_inst0 I have a simple schematic with a few analog signals and dc/tran sources, for example there is a net named my_net.

Now my question is: how do I probe my_net inside ADE ?
With any standard schematic hierarchy I would simply click on "Add new output" and then write "/DUT/my_module_inst0/my_net" to probe the voltage signal of that net however I tried that and it simply does not find that net.

My simulation does work and does output correct signals at the toplevel so I know the connect modules work. Also, I had to add args -ams_ucm and -sv_ms to my test to the additional arguments in the AMS options for the simulation to work.
I also checked in the config view that the hierarchy was indeed correct so that should be fine. 
I am using version IC23.1-64b.ISR8.40 of virtuoso and xrun 23.03-s011.


Seems like it should be quite a basic question unfortunately I did not find the answer in the documentation or the forums so I would be very grateful if anyone could help me out with that.

Thanks in advance and have a great day !

Mike