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Logic Design

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  • Discussion

    Logic Design Forum Posting Guidelines

    Category: Logic Design

    By tstark tstark

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    started over 8 years ago

    0 replies • 42303 views
  • Discussion

    Genus : Tool coming out with "Killed"

    Category: Logic Design

    By sharadbrcm sharadbrcm

    •

    updated 8 days ago by sharadbrcm

    1 replies • 177 views
  • Discussion

    Best library structure (worklibs)

    Category: Logic Design

    By Ryic Ryic

    •

    started 11 days ago

    0 replies • 252 views
  • Discussion

    xmvlog: *E,MULPAK

    Category: Logic Design

    By Yishay Yishay

    •

    started 1 month ago

    0 replies • 543 views
  • Discussion

    Can Joules Report on wasted power on the inputs of a gated flop?

    Category: Logic Design

    By Falanke Falanke

    •

    started 2 months ago

    0 replies • 1297 views
  • Discussion

    Genus synthesis report

    Category: Logic Design

    By Kelly Yu Kelly Yu

    •

    updated 2 months ago by Kelly Yu

    2 replies • 1817 views
  • Discussion

    What's the advantage for declaration different clock domain in Genus

    Category: Logic Design

    By NickK NickK

    •

    updated 4 months ago by samiirlore

    2 replies • 2998 views
  • Discussion

    Genus: Problem with long module name due to parameter types

    Category: Logic Design

    By pkarl pkarl

    •

    updated 5 months ago by pkarl

    1 replies • 2323 views
  • Discussion

    How to interpret area reported by Genus in mm2

    Category: Logic Design

    By abarajithan11 abarajithan11

    •

    started 7 months ago

    0 replies • 3029 views
  • Discussion

    What kind of flops does state retention synthesis take?

    Category: Logic Design

    By iamKarthikBK iamKarthikBK

    •

    started 7 months ago

    0 replies • 3042 views
  • Discussion

    How to add logic when compile

    Category: Logic Design

    By BaoP BaoP

    •

    started 9 months ago

    0 replies • 3467 views
  • Discussion

    Check Constraints Problem

    Category: Logic Design

    By Dimitris Ant Dimitris Ant

    •

    updated 10 months ago by Dimo M

    2 replies • 8210 views
  • Discussion

    Tool for generating 'documentation friendly' schematics from RTL

    Category: Logic Design

    By gretzteam gretzteam

    •

    updated 10 months ago by lstand

    1 replies • 3854 views
  • Discussion

    Default settings for cell mapping - Genus Synthesis (Legacy)

    Category: Logic Design

    By iamKarthikBK iamKarthikBK

    •

    started 11 months ago

    0 replies • 2783 views
  • Discussion

    Xcelium notation worklib:cell:view

    Category: Logic Design

    By Yakir Yakir

    •

    started 11 months ago

    0 replies • 2122 views
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