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Logic Design Forum Posting Guidelines
started by on 6 Feb 2014 8:02 AM
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3 Apr 2015 10:57 PM
problem with "REPORT RULE CHECK" command using conformal
started by on 6 Dec 2018 7:52 AM
1
137
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7 Dec 2018 9:00 AM
Inverter Chain Synthesis
started by on 5 Nov 2018 1:09 PM
0
1013
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5 Nov 2018 1:09 PM
Differences between "report power" and "report scan_power"
started by on 23 Sep 2018 6:57 AM
0
1313
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23 Sep 2018 6:57 AM
Irun driver contention with SystemVerilog port defaults (15.20.001)
started by on 2 Aug 2018 2:45 PM
0
3658
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2 Aug 2018 2:45 PM
RC compiler and ports consisting of arrays of vectors
started by on 21 Apr 2015 5:00 AM
2
48319
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18 Jul 2018 3:29 AM
port array synthesis
started by on 16 Jul 2018 6:19 AM
0
3349
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16 Jul 2018 6:19 AM
Genus UI - How to set attribute?
started by on 8 Jul 2018 5:28 PM
0
5261
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8 Jul 2018 5:28 PM
Genus : Auto_ungroup breaks functionality
started by on 26 May 2018 7:52 AM
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2292
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26 May 2018 7:52 AM
Problems with simulating counter chips
started by on 11 May 2018 11:08 AM
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3802
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11 May 2018 11:08 AM
Is there a way to set the `default_nettype directive through the command-line when running irun?
started by on 23 Mar 2018 12:07 PM
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2536
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23 Mar 2018 12:07 PM
Genus Synthesis - Cost Groups
started by on 21 Mar 2018 11:50 AM
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6539
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21 Mar 2018 11:50 AM
Delay in Or cad pspice
started by on 19 Dec 2017 9:28 PM
2
19581
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21 Jan 2018 11:01 PM
Hierarchical design component used report
started by on 5 Jan 2018 1:24 AM
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8744
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5 Jan 2018 1:24 AM
Super threading error inside RTL Compiler
started by on 12 Dec 2017 5:16 PM
0
9659
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12 Dec 2017 5:16 PM

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