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Logic Design Forum Posting Guidelines
started by
tstark
on 6 Feb 2014 8:02 AM
1
33860
By
Ahmad Raza
3 Apr 2015 10:57 PM
Simvision
started by
FNaqvi
on 10 Jan 2020 10:57 AM
0
108
By
FNaqvi
10 Jan 2020 10:57 AM
How to dump waveform, fsdb in SimVision?
started by
achang
on 8 Jan 2020 6:30 PM
0
121
By
achang
8 Jan 2020 6:30 PM
GENUS can't handle parameterized ports?
started by
GGobieski
on 20 Dec 2019 2:15 PM
0
97
By
GGobieski
20 Dec 2019 2:15 PM
genus include `define file
started by
saw235
on 25 Nov 2019 7:35 AM
2
607
By
saw235
3 Dec 2019 9:19 AM
Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC
started by
Luca Pacher
on 14 Nov 2019 11:13 AM
0
546
By
Luca Pacher
14 Nov 2019 11:13 AM
allegro 16.6 pcb export parameters error
started by
solutions
on 29 Oct 2019 5:11 AM
0
595
By
solutions
29 Oct 2019 5:11 AM
SystemVerilog package used inside VHDL-2008 design?
started by
Michal Kajan
on 17 Oct 2019 8:46 AM
0
717
By
Michal Kajan
17 Oct 2019 8:46 AM
How to customize default_hdl_checks/rules in CCD conformal constraint designer
started by
Attiq Rehman
on 3 Sep 2019 1:12 AM
0
161
By
Attiq Rehman
3 Sep 2019 1:12 AM
using ModelSim/QuestaSim VCD file in RTL compiler
started by
dkhan
on 17 Jun 2013 10:53 PM
4
65555
By
shvd
23 Aug 2019 2:44 AM
Post-synthesis Simulation Failing when lp_insert_clock_gating true
started by
GGobieski
on 14 Aug 2019 11:36 AM
1
1507
By
GGobieski
15 Aug 2019 6:42 AM
Mouse wheel and [i][o] button doesn't zoom
started by
phanvandung
on 15 Jul 2019 7:49 PM
0
604
By
phanvandung
15 Jul 2019 7:49 PM
Reuse of Schematics across different Projects
started by
akmo25
on 24 Jun 2019 7:01 AM
0
1946
By
akmo25
24 Jun 2019 7:01 AM
stretching LOW pulse signal for extra 100ns
started by
Iaf22
on 18 Jun 2019 5:02 AM
0
1975
By
Iaf22
18 Jun 2019 5:02 AM
Genus synthesis syntax Foreach
started by
yann06
on 5 Mar 2019 2:00 AM
1
2926
By
GeorgeGG
10 Jun 2019 11:38 AM
>
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