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Community Logic Design
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Logic Design

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  • Discussion

    Logic Design Forum Posting Guidelines

    Category: Logic Design

    By tstark tstark

    •

    started over 9 years ago

    0 replies • 45079 views
  • Discussion

    Genus: Generated netlist doesn't define subckts

    Category: Logic Design

    By Anas2023a95 Anas2023a95

    •

    started 15 days ago

    0 replies • 62 views
  • Discussion

    Stream in gds to virtuoso from directory other than where cds.lib exists

    Category: Logic Design

    By polymorpher polymorpher

    •

    updated 2 months ago by DimoM

    1 replies • 537 views
  • Discussion

    In Simvision, how do I change the waveform font size of the signal names?

    Category: Logic Design

    By mxlusereight mxlusereight

    •

    started 2 months ago

    0 replies • 552 views
  • Discussion

    read from text file with two values and represent that as voltage signals on two different port a and b

    Category: Logic Design

    By Hagar Hendy Hagar Hendy

    •

    updated 3 months ago by ShawnLogan

    1 replies • 811 views
  • Discussion

    Constraining some nets to route through a specific metal layer, and changing some pin/cell placements and wire directions in Cadence Innovus.

    Category: Logic Design

    By Riya C Riya C

    •

    updated 3 months ago by Riya C

    2 replies • 675 views
  • Discussion

    Digital Custom Placer Via not placing

    Category: Logic Design

    By KhanAmir KhanAmir

    •

    updated 3 months ago by realakirabutt

    3 replies • 1099 views
  • Discussion

    Instance of standard cell does not have layout?

    Category: Logic Design

    By KhanAmir KhanAmir

    •

    updated 3 months ago by DimoM

    3 replies • 1124 views
  • Discussion

    HELP WITH Integral nonlinearity (INL) and differential nonlinearity (DNL) of data converters

    Category: Logic Design

    By Saori Saori

    •

    updated 4 months ago by ShawnLogan

    1 replies • 1059 views
  • Discussion

    End cap/boundary cell in my pdk from LFoundary

    Category: Logic Design

    By KhanAmir KhanAmir

    •

    updated 4 months ago by KhanAmir

    6 replies • 632 views
  • Discussion

    Decoder standalone synthesis in Genus

    Category: Logic Design

    By KhanAmir KhanAmir

    •

    started 4 months ago

    0 replies • 1077 views
  • Discussion

    Cadence Encounter and Innovus Library Compatibility.

    Category: Logic Design

    By Riya C Riya C

    •

    updated 6 months ago by Riya C

    4 replies • 2741 views
  • Discussion

    cadence Digital design

    Category: Logic Design

    By blossom blossom

    •

    updated 6 months ago by MTYM

    1 replies • 3250 views
  • Discussion

    when i use the elc, i found these problems, please help me!

    Category: Logic Design

    By WANGZHELONG WANGZHELONG

    •

    started 8 months ago

    0 replies • 2930 views
  • Discussion

    Genus Synthesis not preserving register for sequential logic with pragma.

    Category: Logic Design

    By RichaV RichaV

    •

    started 9 months ago

    0 replies • 3136 views
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