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Logic Design Forum Posting Guidelines
started by on 6 Feb 2014 8:02 AM
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3 Apr 2015 10:57 PM
stretching LOW pulse signal for extra 100ns
started by on 18 Jun 2019 5:02 AM
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18 Jun 2019 5:02 AM
Genus synthesis syntax Foreach
started by on 5 Mar 2019 2:00 AM
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858
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10 Jun 2019 11:38 AM
List of Highest Fanouts
started by on 10 Jun 2019 11:31 AM
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111
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10 Jun 2019 11:31 AM
problem with "REPORT RULE CHECK" command using conformal
started by on 6 Dec 2018 7:52 AM
4
625
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31 May 2019 1:24 AM
Conformal ECO use cell out of spare(NO_MAP)
started by on 16 Apr 2019 12:58 AM
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123
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16 Apr 2019 12:58 AM
CONFORMAL ECO : SPARE CELLS NOT MAPPED
started by on 26 Mar 2019 7:40 AM
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699
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26 Mar 2019 7:40 AM
functional equivalence check between system verilog and schematic
started by on 14 Mar 2019 2:36 PM
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720
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14 Mar 2019 2:36 PM
Formatting of concept HDL schematic pages
started by on 7 Mar 2019 6:35 AM
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770
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7 Mar 2019 6:35 AM
Error in Cadence RTL Compiler when estimating Power using VCD
started by on 26 Feb 2019 12:44 AM
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924
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26 Feb 2019 12:44 AM
for choosing the frequency range of any digital circuit
started by on 31 Jan 2019 10:38 AM
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1075
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31 Jan 2019 10:38 AM
RTL compiler crash
started by on 29 Dec 2018 2:33 AM
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1466
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29 Dec 2018 2:33 AM
What does area reported by RTL compiler mean?
started by on 5 Apr 2013 7:29 AM
6
89161
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18 Dec 2018 5:48 AM
Differences between "report power" and "report scan_power"
started by on 23 Sep 2018 6:57 AM
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1546
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23 Sep 2018 6:57 AM
Irun driver contention with SystemVerilog port defaults (15.20.001)
started by on 2 Aug 2018 2:45 PM
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5318
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2 Aug 2018 2:45 PM

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