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Logic Design Forum Posting Guidelines
started by
tstark
on 6 Feb 2014 8:02 AM
0
38803
By
tstark
6 Feb 2014 8:02 AM
What's the advantage for declaration different clock domain in Genus
started by
NickK
on 22 Jul 2020 12:38 AM
1
1090
By
Dimo M
15 Apr 2021 4:05 AM
What is the command for opening the Xcelium Simulator ?
started by
Sandeep29
on 7 Dec 2020 10:01 PM
1
1316
By
Dimo M
14 Apr 2021 1:11 AM
Compiling Xilinx libraries using Xcleium
started by
rohanj
on 7 Apr 2021 8:01 PM
4
1092
By
rohanj
10 Apr 2021 9:25 PM
Reporting non-RC gated flops
started by
Max Bjurling
on 9 Sep 2020 5:21 AM
2
2071
By
Max Bjurling
7 Apr 2021 3:16 AM
Genus - Hierarchy
started by
Stratis
on 4 Sep 2020 2:44 AM
1
1651
By
Dimo M
6 Apr 2021 3:29 AM
VHDL IEEE Library not recognized by RTL Compiler or Genus
started by
YuntaoLiu
on 20 Oct 2020 7:30 PM
1
1879
By
Dimo M
6 Apr 2021 3:21 AM
Conformal-ECO priority of picking freed cells and sparecells
started by
Mihu
on 7 Mar 2021 7:01 PM
0
1786
By
Mihu
7 Mar 2021 7:01 PM
VHDL-613 error inside declarative region
started by
carlosgewehr
on 6 Mar 2021 7:08 PM
0
1713
By
carlosgewehr
6 Mar 2021 7:08 PM
Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC
started by
Luca Pacher
on 14 Nov 2019 11:13 AM
1
4684
By
AndreasWiener
12 Feb 2021 12:26 AM
Genus advices on how to handle power and analog signals
started by
abettati
on 1 Feb 2021 2:19 AM
0
2328
By
abettati
1 Feb 2021 2:19 AM
Error in Cadence RTL Compiler when estimating Power using VCD
started by
RileyDylan
on 18 Jan 2021 11:52 PM
0
2425
By
RileyDylan
18 Jan 2021 11:52 PM
how to debug the misbehaving scheduling of sequential logic
started by
ChrisKAustin
on 9 Jan 2021 4:08 PM
0
2417
By
ChrisKAustin
9 Jan 2021 4:08 PM
Tool for generating 'documentation friendly' schematics from RTL
started by
gretzteam
on 24 Sep 2020 7:53 AM
0
1524
By
gretzteam
24 Sep 2020 7:53 AM
Conformal LEC error
started by
Varun M J
on 8 Aug 2020 11:51 PM
0
3001
By
Varun M J
8 Aug 2020 11:51 PM
>
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