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Logic Design Forum Posting Guidelines
started by
tstark
on 6 Feb 2014 8:02 AM
1
29087
By
Ahmad Raza
3 Apr 2015 10:57 PM
Inverter Chain Synthesis
started by
Hackasim
on 5 Nov 2018 1:09 PM
0
323
By
Hackasim
5 Nov 2018 1:09 PM
Differences between "report power" and "report scan_power"
started by
nokta
on 23 Sep 2018 6:57 AM
0
967
By
nokta
23 Sep 2018 6:57 AM
Irun driver contention with SystemVerilog port defaults (15.20.001)
started by
Palaparthy
on 2 Aug 2018 2:45 PM
0
3112
By
Palaparthy
2 Aug 2018 2:45 PM
RC compiler and ports consisting of arrays of vectors
started by
MarkusK
on 21 Apr 2015 5:00 AM
2
47050
By
MarkusK
18 Jul 2018 3:29 AM
port array synthesis
started by
olalivier
on 16 Jul 2018 6:19 AM
0
2728
By
olalivier
16 Jul 2018 6:19 AM
Genus UI - How to set attribute?
started by
mbrandalero
on 8 Jul 2018 5:28 PM
0
4266
By
mbrandalero
8 Jul 2018 5:28 PM
Genus : Auto_ungroup breaks functionality
started by
Schriek
on 26 May 2018 7:52 AM
0
1887
By
Schriek
26 May 2018 7:52 AM
Problems with simulating counter chips
started by
zfan
on 11 May 2018 11:08 AM
0
3193
By
zfan
11 May 2018 11:08 AM
Is there a way to set the `default_nettype directive through the command-line when running irun?
started by
crclayton
on 23 Mar 2018 12:07 PM
0
2124
By
crclayton
23 Mar 2018 12:07 PM
Genus Synthesis - Cost Groups
started by
Heaton15
on 21 Mar 2018 11:50 AM
0
5920
By
Heaton15
21 Mar 2018 11:50 AM
Delay in Or cad pspice
started by
amrita1503
on 19 Dec 2017 9:28 PM
2
18296
By
amrita1503
21 Jan 2018 11:01 PM
Hierarchical design component used report
started by
chillman
on 5 Jan 2018 1:24 AM
0
8139
By
chillman
5 Jan 2018 1:24 AM
Super threading error inside RTL Compiler
started by
as90
on 12 Dec 2017 5:16 PM
0
9044
By
as90
12 Dec 2017 5:16 PM
Timing analysis in RTL Compiler
started by
as90
on 20 Nov 2017 3:53 PM
2
29121
By
as90
2 Dec 2017 2:16 PM
>
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