Home
:
Community
:
Forums
:
Logic Design
Logic Design Forums
Nextweb Forums Categories
All Forums
Custom IC Design
Custom IC SKILL
Digital Implementation
Functional Verification
Functional Verification Shared Code
Hardware/Software Co-Development, Verification and Integration
High-Level Synthesis
IC Packaging and SiP Design
Logic Design
Mixed-Signal Design
PCB Design
PCB SKILL
PCell Designer
RAVEL DRC Programming for IC Packaging and PCB
RF Design
Verification IP
Site - Banner
Community Search
New
All recent discussions
Unread discussions
Discussions you've participated in
Discussions you've started
Unanswered discussions
Answered discussions
By title
By last post date
By topic date
By reply count
By view count
Descending
Ascending
Topics
Replies
Views
Last Post
Logic Design Forum Posting Guidelines
started by
tstark
on 6 Feb 2014 8:02 AM
1
36017
By
Ahmad Raza
3 Apr 2015 10:57 PM
Specifying VT Ratio in Joules
started by
badeni
on 5 Jun 2020 10:44 AM
0
910
By
badeni
5 Jun 2020 10:44 AM
Slow performance with SimVision GUI
started by
imcostanzo
on 19 May 2020 8:07 PM
0
1170
By
imcostanzo
19 May 2020 8:07 PM
Adding clock to CDC tool which is not a primary input but internal to design.
started by
vaizguy
on 11 Aug 2011 8:24 PM
2
35569
By
peterkn
30 Apr 2020 8:42 AM
Allegro System Architect 17.2 Project Settings not Opening
started by
akmo25
on 8 Apr 2020 12:02 AM
0
2248
By
akmo25
8 Apr 2020 12:02 AM
About SDC file
started by
LiGer
on 27 Feb 2020 5:58 AM
0
1773
By
LiGer
27 Feb 2020 5:58 AM
About SDF file
started by
LiGer
on 27 Feb 2020 5:56 AM
0
1700
By
LiGer
27 Feb 2020 5:56 AM
map_to_mux
started by
Abhayk
on 25 Feb 2020 11:54 PM
0
1753
By
Abhayk
25 Feb 2020 11:54 PM
About SDF file after synthesis in Genus Tool
started by
LiGer
on 20 Feb 2020 1:47 AM
0
1751
By
LiGer
20 Feb 2020 1:47 AM
Simvision
started by
FNaqvi
on 10 Jan 2020 10:57 AM
0
1951
By
FNaqvi
10 Jan 2020 10:57 AM
How to dump waveform, fsdb in SimVision?
started by
achang
on 8 Jan 2020 6:30 PM
0
2217
By
achang
8 Jan 2020 6:30 PM
GENUS can't handle parameterized ports?
started by
GGobieski
on 20 Dec 2019 2:15 PM
0
545
By
GGobieski
20 Dec 2019 2:15 PM
genus include `define file
started by
saw235
on 25 Nov 2019 7:35 AM
2
2788
By
saw235
3 Dec 2019 9:19 AM
Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC
started by
Luca Pacher
on 14 Nov 2019 11:13 AM
0
2379
By
Luca Pacher
14 Nov 2019 11:13 AM
allegro 16.6 pcb export parameters error
started by
solutions
on 29 Oct 2019 5:11 AM
0
2392
By
solutions
29 Oct 2019 5:11 AM
>
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full
Community Guidelines
.