Static power consumption of domino logic and cmos logic AND gate (cadence 6.1.8)

I am comparing the performance parametrics of cmos logic and domino logic from room temperature to cryogenic temperature.

I was measuring the parameters like dynamic power consumption, static power, delay etc

Basically I am working both circuits on same schematic cell view with same Vdd, load and input frequency.

firstly i tried measuring static power consumption by shift deleting one circuit at a time in schematic as both had common vdd supply and global ground. At that time cmos has pW range power consumption in room temperature and it reduces only by few to cryogenic. Domino had more static power at room from nW and it went to pW range in cryogenic, but the decrease was not gradual, it was random fluctuating with high and low. Also at some instances it gave negative power.

While giving negative power, how to take the value, should we consider the magnitude at that temperature.

Also later i gave two vdd names separately for cmos and domino(only instances given separate, vdd value same only) with global ground for everything and no circuit change except this, but then I simulated power, the static power of cmos was more or less same, but static power of domino for 11 combination was going to uW range.

same circuit simulated with two different analysis on same condition gave 2 different results. How and why?

i am simulating static power on the flat regions of transient analysis fir input combo 00,01,10,11 for a temperature sweep from -270C to 30C with step 10 deg C.

Requesting help on this.