Ring oscillator separation gate delay and interconnect delay

Hello.

I have been reviewing the conventional methodologies for separating intrinsic gate delay and interconnect delay in ring oscillators,

such as

(1) varying the fan-out of the inverter

(2) modifying the interconnect length/width or shape

(3) changing the number of stages in the inverter chain.

However, I believe these approaches cannot rigorously decouple the two delays. This is because the overall circuit delay fundamentally results from the product of the total resistance and capacitance distributed across the entire circuit. Unless every cell is explicitly modeled as a network of R and C components and the contributions are separated at that level, the extracted delay will always contain coupled effects of both gate and interconnect. Do you think there is a feasible circuit modification or an alternative methodology that could more clearly separate gate delay and interconnect delay, beyond the conventional fan-out, interconnect geometry, or stage-count variations?

I would greatly appreciate your insights or suggestions on possible approaches. thankyou!