Our IP includes a software-controlled clock gate that drives an entire clock domain (several hundred flip-flops).

Our IP includes a software-controlled clock gate that drives an entire clock domain (several hundred flip-flops). I’ve observed that in some cases, the clock gate gets cloned after CTS, which results in a high fanout path from the enable signal to the different clones. This, in turn, causes timing violations.

Apologies if this is expected behavior — I primarily work on the RTL (Verilog) side.

I’ve searched extensively online but haven’t found a reliable way to handle this issue. The only apparent solution seems to be using directives like set_max_fanout or set_register_duplication on the enable flop. However, I’ve noticed that backend engineers often discourage the use of these constraints, though the reasons are not clearly explained.